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sim: sim_halfword: handle HLRZ/HLRZM/HLRZS, sim_core: handle HLRZI as SETZ, add unit tests
This commit is contained in:
Mikael Pettersson
parent
baa065b9a2
commit
d97d9c8efe
@ -361,6 +361,10 @@ dispatch(Core, Mem, IR, EA) ->
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8#551 -> sim_moves:handle_MOVEI(Core, Mem, IR, EA); % HRRZI = MOVEI
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8#552 -> sim_halfword:handle_HRRZM(Core, Mem, IR, EA);
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8#553 -> sim_halfword:handle_HRRZS(Core, Mem, IR, EA);
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8#554 -> sim_halfword:handle_HLRZ(Core, Mem, IR, EA);
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8#555 -> sim_boolean:handle_SETZ(Core, Mem, IR, EA); % HLRZI = HLLZI = SETZ
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8#556 -> sim_halfword:handle_HLRZM(Core, Mem, IR, EA);
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8#557 -> sim_halfword:handle_HLRZS(Core, Mem, IR, EA);
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8#560 -> sim_halfword:handle_HRRO(Core, Mem, IR, EA);
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8#561 -> sim_halfword:handle_HRROI(Core, Mem, IR, EA);
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8#562 -> sim_halfword:handle_HRROM(Core, Mem, IR, EA);
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@ -42,6 +42,9 @@
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, handle_HLRI/4
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, handle_HLRM/4
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, handle_HLRS/4
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, handle_HLRZ/4
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, handle_HLRZM/4
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, handle_HLRZS/4
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, handle_HRL/4
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, handle_HRLE/4
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, handle_HRLEI/4
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@ -649,6 +652,42 @@ handle_HLRS(Core, Mem, IR, EA) ->
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fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end)
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end.
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%% HLRZ - Half Word Left to Right, Zeros
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-spec handle_HLRZ(#core{}, sim_mem:mem(), IR :: word(), #ea{})
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-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
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handle_HLRZ(Core, Mem, IR, EA) ->
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case sim_core:c(Core, Mem, EA) of
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{ok, CE} ->
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AC = IR band 8#17,
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Word = get_left(CE),
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sim_core:next_pc(sim_core:set_ac(Core, AC, Word), Mem);
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{error, Reason} ->
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sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason,
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fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end)
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end.
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-spec handle_HLRZM(#core{}, sim_mem:mem(), IR :: word(), #ea{})
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-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
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handle_HLRZM(Core, Mem, IR, EA) ->
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AC = IR band 8#17,
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CA = sim_core:get_ac(Core, AC),
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Word = get_left(CA),
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handle_writeback(Core, Mem, EA, Word).
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-spec handle_HLRZS(#core{}, sim_mem:mem(), IR :: word(), #ea{})
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-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
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handle_HLRZS(Core, Mem, IR, EA) ->
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case sim_core:c(Core, Mem, EA) of
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{ok, CE} ->
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AC = IR band 8#17,
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Word = get_left(CE),
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handle_writeback(Core, Mem, AC, EA, Word);
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{error, Reason} ->
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sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason,
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fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end)
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end.
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%% Miscellaneous ===============================================================
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handle_writeback(Core, Mem, EA, Word) ->
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@ -89,6 +89,10 @@
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-define(OP_HRRZI, 8#551).
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-define(OP_HRRZM, 8#552).
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-define(OP_HRRZS, 8#553).
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-define(OP_HLRZ, 8#554).
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-define(OP_HLRZI, 8#555).
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-define(OP_HLRZM, 8#556).
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-define(OP_HLRZS, 8#557).
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-define(OP_HRRO, 8#560).
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-define(OP_HRROI, 8#561).
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-define(OP_HRROM, 8#562).
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@ -875,6 +879,64 @@ hlrs_no_ac_test() ->
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, {#ea{section = 1, offset = 0, islocal = false}, ?COMMA2(1, 0)} % AC0 = 1,,0
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]).
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%% HLRZ - Half Word Left to Right, Zeros
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hlrz_test() ->
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Prog =
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[ {1, 8#100, ?INSN(?OP_MOVSI, 1, 0, 0, 1)} % 1,,100/ MOVSI 1,1
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, {1, 8#101, ?INSN(?OP_HLRZ, 1, 0, 0, 8#200)} % 1,,101/ HLRZ 1,200
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, {1, 8#102, ?INSN_INVALID} % 1,,102/ <invalid>
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, {1, 8#200, ?COMMA2(1, 0)} % 1,,200/ 1,,0
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],
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expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS,
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[ {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(0, 1)} % AC1 = 0,,1
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]).
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hlrzi_test() ->
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Prog =
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[ {1, 8#100, ?INSN(?OP_MOVSI, 1, 0, 0, 1)} % 0,,100/ MOVSI 1,1
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, {1, 8#101, ?INSN(?OP_HLRZI, 1, 0, 0, 1)} % 0,,101/ HLRZI 1,1
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, {1, 8#102, ?INSN_INVALID} % 0,,102/ <invalid>
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],
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expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS,
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[ {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(0, 0)} % AC1 = 0,,0
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]).
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hlrzm_test() ->
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Prog =
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[ {1, 8#100, ?INSN(?OP_MOVSI, 1, 0, 0, 1)} % 1,,100/ MOVSI 1,1
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, {1, 8#101, ?INSN(?OP_HLRZM, 1, 0, 0, 8#200)} % 1,,101/ HLRZM 1,200
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, {1, 8#102, ?INSN_INVALID} % 1,,102/ <invalid>
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, {1, 8#200, ?COMMA2(1, 0)} % 1,,200/ 1,,0
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],
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expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS,
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[ {#ea{section = 1, offset = 8#200, islocal = false}, ?COMMA2(0, 1)} % C(1,200) = 0,,1
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]).
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hlrzs_ac_test() ->
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Prog =
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[ {1, 8#100, ?INSN(?OP_MOVSI, 1, 0, 0, 1)} % 1,,100/ MOVSI 1,1
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, {1, 8#101, ?INSN(?OP_HLRZS, 1, 0, 0, 8#200)} % 1,,101/ HLRZS 1,200
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, {1, 8#102, ?INSN_INVALID} % 1,,102/ <invalid>
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, {1, 8#200, ?COMMA2(1, 0)} % 1,,200/ 1,,0
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],
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expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS,
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[ {#ea{section = 1, offset = 8#200, islocal = false}, ?COMMA2(0, 1)} % C(1,,200) = 0,,1
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, {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(0, 1)} % AC1 = 0,,1
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]).
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hlrzs_no_ac_test() ->
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Prog =
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[ {1, 8#100, ?INSN(?OP_MOVSI, 0, 0, 0, 1)} % 1,,100/ MOVSI 0,1
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, {1, 8#101, ?INSN(?OP_HLRZS, 0, 0, 0, 8#200)} % 1,,101/ HLRZS 0,200
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, {1, 8#102, ?INSN_INVALID} % 1,,102/ <invalid>
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, {1, 8#200, ?COMMA2(1, 0)} % 1,,200/ 1,,0
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],
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expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS,
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[ {#ea{section = 1, offset = 8#200, islocal = false}, ?COMMA2(0, 1)} % C(1,,200) = 0,,1
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, {#ea{section = 1, offset = 0, islocal = false}, ?COMMA2(1, 0)} % AC0 = 0,,1
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]).
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%% Common code to run short sequences ==========================================
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expect(Prog, ACs, ExpectedPC, ExpectedFlags, ExpectedEs) ->
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