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sim: sim_shifts: handle ROT/ROTC, add unit tests
This commit is contained in:
Mikael Pettersson
parent
82ee356c37
commit
edf7257d21
@ -280,7 +280,9 @@ dispatch(Core, Mem, IR, EA) ->
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8#215 -> sim_moves:handle_MOVEI(Core, Mem, IR, EA); % MOVMI = MOVEI
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8#216 -> sim_moves:handle_MOVMM(Core, Mem, IR, EA);
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8#217 -> sim_moves:handle_MOVMS(Core, Mem, IR, EA);
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8#241 -> sim_shifts:handle_ROT(Core, Mem, IR, EA);
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8#242 -> sim_shifts:handle_LSH(Core, Mem, IR, EA);
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8#245 -> sim_shifts:handle_ROTC(Core, Mem, IR, EA);
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8#246 -> sim_shifts:handle_LSHC(Core, Mem, IR, EA);
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8#250 -> sim_moves:handle_EXCH(Core, Mem, IR, EA);
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8#251 -> sim_moves:handle_BLT(Core, Mem, IR, EA);
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@ -26,6 +26,8 @@
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-export([ handle_LSH/4
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, handle_LSHC/4
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, handle_ROT/4
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, handle_ROTC/4
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]).
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-include("sim_core.hrl").
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@ -53,6 +55,27 @@ handle_LSHC(Core, Mem, IR, EA) ->
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{Word0, Word1} = lshc(CA0, CA1, EA#ea.offset),
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set_acs_next_pc(Core, Mem, AC, Word0, Word1).
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%% ROT - Rotate
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-spec handle_ROT(#core{}, sim_mem:mem(), IR :: word(), #ea{})
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-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
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handle_ROT(Core, Mem, IR, EA) ->
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AC = IR band 8#17,
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CA = sim_core:get_ac(Core, AC),
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Word = rot(CA, EA#ea.offset),
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set_ac_next_pc(Core, Mem, AC, Word).
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%% ROTC - Rotate Combined
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-spec handle_ROTC(#core{}, sim_mem:mem(), IR :: word(), #ea{})
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-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
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handle_ROTC(Core, Mem, IR, EA) ->
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AC = IR band 8#17,
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CA0 = sim_core:get_ac(Core, AC),
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CA1 = sim_core:get_ac(Core, (AC + 1) band 8#17),
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{Word0, Word1} = rotc(CA0, CA1, EA#ea.offset),
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set_acs_next_pc(Core, Mem, AC, Word0, Word1).
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%% Miscellaneous ===============================================================
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lsh(CA, Offset) ->
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@ -98,6 +121,44 @@ lshc(CA0, CA1, Offset) ->
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end
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end.
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rot(CA, Offset) ->
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case Offset band (1 bsl 17) of
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0 -> % rotate left
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Count = (Offset band ((1 bsl 8) - 1)) rem 36,
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((CA band ((1 bsl (36 - Count)) - 1)) bsl Count) bor (CA bsr (36 - Count));
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_ -> % rotate right
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Count = ((-Offset) band ((1 bsl 8) - 1)) rem 36,
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(CA bsr Count) bor ((CA band ((1 bsl Count) - 1)) bsl (36 - Count))
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end.
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rotc(CA0, CA1, Offset) ->
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case Offset band (1 bsl 17) of
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0 -> % rotate left
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Count = (Offset band ((1 bsl 8) - 1)) rem 72,
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if Count >= 36 ->
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Count1 = Count - 36,
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Word0 = ((CA1 band ((1 bsl (36 - Count1)) - 1)) bsl Count1) bor (CA0 bsr (36 - Count1)),
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Word1 = ((CA0 band ((1 bsl (36 - Count1)) - 1)) bsl Count1) bor (CA1 bsr (36 - Count1)),
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{Word0, Word1};
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true ->
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Word0 = ((CA0 band ((1 bsl (36 - Count)) - 1)) bsl Count) bor (CA1 bsr (36 - Count)),
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Word1 = ((CA1 band ((1 bsl (36 - Count)) - 1)) bsl Count) bor (CA0 bsr (36 - Count)),
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{Word0, Word1}
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end;
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_ -> % rotate right
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Count = ((-Offset) band ((1 bsl 8) - 1)) rem 72,
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if Count >= 36 ->
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Count1 = Count - 36,
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Word0 = (CA1 bsr Count1) bor ((CA0 band ((1 bsl Count1) - 1)) bsl (36 - Count1)),
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Word1 = (CA0 bsr Count1) bor ((CA1 band ((1 bsl Count1) - 1)) bsl (36 - Count1)),
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{Word0, Word1};
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true ->
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Word0 = (CA0 bsr Count) bor ((CA1 band ((1 bsl Count) - 1)) bsl (36 - Count)),
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Word1 = (CA1 bsr Count) bor ((CA0 band ((1 bsl Count) - 1)) bsl (36 - Count)),
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{Word0, Word1}
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end
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end.
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set_acs_next_pc(Core, Mem, AC, Word0, Word1) ->
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set_ac_next_pc(sim_core:set_ac(Core, AC, Word0), Mem, (AC + 1) band 8#17, Word1).
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@ -46,7 +46,9 @@
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-define(INSN_INVALID, ?INSN(0, 0, 0, 0, 0)).
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-define(OP_ROT, 8#241).
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-define(OP_LSH, 8#242).
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-define(OP_ROTC, 8#245).
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-define(OP_LSHC, 8#246).
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%% 2.5 Shift and Rotate ========================================================
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@ -112,6 +114,67 @@ lshc_test() ->
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, {?AC(2), ?COMMA2(8#000000, 8#111222)} % AC2 = 000000111222
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]).
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%% ROT - Rotate
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rot_test() ->
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ACS =
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[ {1, ?COMMA2(8#111222, 8#333444)} % AC1 = 111222333444
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],
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Prog1 =
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[ {1, 8#100, ?INSN(?OP_ROT, 1, 0, 0, 36+9)} % 1,,100/ ROT 1,55
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, {1, 8#101, ?INSN_INVALID} % 1,,101/ <invalid>
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],
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expect(Prog1, ACS, {1, 8#101}, ?DEFAULT_FLAGS,
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[ {?AC(1), ?COMMA2(8#222333, 8#444111)} % AC1 = 222333444111
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]),
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Prog2 =
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[ {1, 8#100, ?INSN(?OP_ROT, 1, 0, 0, -(36+9))} % 1,,100/ ROT 1,-55
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, {1, 8#101, ?INSN_INVALID} % 1,,101/ <invalid>
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],
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expect(Prog2, ACS, {1, 8#101}, ?DEFAULT_FLAGS,
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[ {?AC(1), ?COMMA2(8#444111, 8#222333)} % AC1 = 444111222333
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]).
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%% ROTC - Rotate Combined
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rotc_test() ->
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ACS =
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[ {1, ?COMMA2(8#000111, 8#222333)} % AC1 = 000111222333
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, {2, ?COMMA2(8#444555, 8#666777)} % AC2 = 444555666777
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],
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Prog1 =
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[ {1, 8#100, ?INSN(?OP_ROTC, 1, 0, 0, 18)} % 1,,100/ ROTC 1,22
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, {1, 8#101, ?INSN_INVALID} % 1,,101/ <invalid>
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],
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expect(Prog1, ACS, {1, 8#101}, ?DEFAULT_FLAGS,
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[ {?AC(1), ?COMMA2(8#222333, 8#444555)} % AC1 = 222333444555
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, {?AC(2), ?COMMA2(8#666777, 8#000111)} % AC2 = 666777000111
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]),
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Prog2 =
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[ {1, 8#100, ?INSN(?OP_ROTC, 1, 0, 0, 36+18)} % 1,,100/ ROTC 1,66
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, {1, 8#101, ?INSN_INVALID} % 1,,101/ <invalid>
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],
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expect(Prog2, ACS, {1, 8#101}, ?DEFAULT_FLAGS,
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[ {?AC(1), ?COMMA2(8#666777, 8#000111)} % AC1 = 666777000111
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, {?AC(2), ?COMMA2(8#222333, 8#444555)} % AC2 = 222333444555
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]),
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Prog3 =
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[ {1, 8#100, ?INSN(?OP_ROTC, 1, 0, 0, -18)} % 1,,100/ ROTC 1,-22
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, {1, 8#101, ?INSN_INVALID} % 1,,101/ <invalid>
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],
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expect(Prog3, ACS, {1, 8#101}, ?DEFAULT_FLAGS,
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[ {?AC(1), ?COMMA2(8#666777, 8#000111)} % AC1 = 666777000111
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, {?AC(2), ?COMMA2(8#222333, 8#444555)} % AC2 = 222333444555
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]),
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Prog4 =
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[ {1, 8#100, ?INSN(?OP_ROTC, 1, 0, 0, -(36+18))} % 1,,100/ ROTC 1,-66
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, {1, 8#101, ?INSN_INVALID} % 1,,101/ <invalid>
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],
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expect(Prog4, ACS, {1, 8#101}, ?DEFAULT_FLAGS,
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[ {?AC(1), ?COMMA2(8#222333, 8#444555)} % AC1 = 222333444555
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, {?AC(2), ?COMMA2(8#666777, 8#000111)} % AC2 = 666777000111
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]).
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%% Common code to run short sequences ==========================================
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expect(Prog, ACs, ExpectedPC, ExpectedFlags, ExpectedEs) ->
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