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Add c16/c264 source

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Till Harbaum
2016-07-29 11:14:39 +02:00
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FPGATED v1.0
Copyright 2013-2016 Istvan Hegedus
MiST port by Till Harbaum
FPGATED is a cycle exact FPGA core for the MOS 7360/8360 TED chip written in verilog language.
MOS 7360/8360 is complex chip providing graphic, sound, bus and memory control for the Commodore 264
series 8 bit computers, namely the Commodore Plus4, Commodore 16 and Commodore 116.
In addition to the TED core modul FPGATED contains a simple C16 implementation using TED core and Gadget Factory's
Papilio One 500k platform with a customized IO wing called Papilio TEDWing. The 6502 CPU core of C16 is created by
Peter Wendrich in vhdl and is taken from the FPGA64 project with the permission of the author.
For more technical details and building Papilio TEDWing module visit https://hackaday.io/project/11460-fpgated
Files
basic_rom.v C16/Plus4 Basic rom module
c16.v This is the TOP module of FPGATED implementing a C16 computer
c16_testbench.v C16 testbench for simulation
c16_keymatrix.v C16/Plus4 keyboard matrix emulation module
colors_to_rgb.v TED color code conversion module to 12bit RGB values
cpu65xx_e.vhd 6502 core vhdl header
cpu65xx_fast.vhd 6502 core vhdl code
dram.v DRAM module for internal FPGA SRAM memory implementation
kernal_rom.v C16/Plus4 Kernal rom module
mos6529.v MOS 6529 IO chip emulation module
mos8501.v MOS 8501 CPU shell for 6502 core
palclockgen.v Xilinx DCM module for PAL system clock signal
ps2receiver.v PS2 keyboard receiver module
ram.v Simulated RAM for testbench
ted.v MOS 7360/8360 FPGA core
basic.hex C16/Plus4 BASIC rom hexadecimal dump
Diag264_NTSC.hex Diag264 NTSC kernal hexadecimal dump
Diag264_PAL.hex Diag264 PAL kernal hexadecimal dump
kernal_NTSC.hex C16/Plus4 NTSC Kernal rom hexadecimal dump
kernal_PAL.hex C16/PLus4 PAL Kernal rom hexadecimal dump
TEDwing.ucf Xilinx ucf file for Papilio TEDwing
bin2hex.pl Perl script for creating hex dump of binary rom image files
c16_PAL.bit A compiled PAL FPGATED core for Papilio platform using FPGATED wing
Installation instructions are for Xilinx FPGA platforms but the source files with the exception of palclockgen.v
and Xilinx ucf files can be used for other vendor's FPGAs.
Some modules are using Xilinx specific (* RAM_STYLE="BLOCK" *) directive for forcing the synthesis tool to
use FPGA internal block ram for certain arrays. In case of other vendor's FPGAs see vendor specific documentation
for generating block ram.
Building FPGATED on the Papilio Platform requires a suitable wing. One can use the Arcade megawing but it lacks
external memory and IEC bus for peripherial connections. Thus I recommend to build TEDwing designed by me. Look for
eagle PCB and schematic files in FPGATED source package.
Although FPGATED can be synthetised to a Papilio One board using Spartan3E chip, I recommend to go for Papilio Pro
platform which has external 8Mbyte SDRAM and a Spartan 6 LX9 FPGA which has more internal sram. In both cases there
are plenty of free resources on the FPGA for FPGATED (if you use external 64k ram).
Installation instructions:
1. Create a new project in Xilinx ISE Webpack and choose the proper FPGA family for the implementation.
2. Choose to use HDL verilog and vhdl for the design.
3. Add all *.v files to the project
4. Using ISE DCM wizard create a clock generator for FPGATED.
Use CLKFX output of DCM and specify 28.37515MHz PAL or 28.63636MHz for NTSC system
This will be the main FPGA clock connected to the clk signal of all modules
Modify C16.v to use proper DCM instantiation (out of scope of this document)
5. Open kernal_rom.v and uncomment the proper Kernal file (Kernal_NTSC.hex or Kernal_PAL.hex) to use.
You can even use a custom rom or JiffyDos if you own it (JiffyDos is working fine, I have tested).
Diag264 roms are included for testing purposes.
6. If you don't use TEDwing modify or replace TEDwing.ucf file for proper pinout setup
7. Video output of FPGATED is a PAL/NTSC RGBS signal so you will need a VGA->scart custom cable to
hook it up to a monitor or television. The cable is identical to minimig scart cables (see internet for wiring diagram)
Enjoy FPGATED.
See https://hackaday.io/project/11460-fpgated for detailed installation instructions.
TED module signals:
input wire clk main FPGA clock must be 4*dot clk so 28.375152MHz for PAL and 28.63636 for NTSC
input wire [15:0] addr_in 16 bits address bus in
output wire [15:0] addr_out 16 bits address bus out
input wire [7:0] data_in 8 bits data bus in
output wire [7:0] data_out 8 bits data bus out
input wire rw RW signal to TED, low during write, high during read (real TED pulls it high during reads)
output wire cpuclk this is a CPU clock out for external real CPU
output wire [6:0] color 7 bits color code using TED's color palette values
output wire csync composite sync signal for PAL/NTSC displays
output wire irq active low IRQ signal to CPU
output wire ba BA (or with other name RDY) signal to 8501 CPU
output reg mux MUX signal, identical to original
output reg ras RAS signal, identical to original
output reg cas CAS signal, identical to original
output reg cs0 CS0 signal, identical to original
output reg cs1 CS1 signal, identical to original
output reg aec AEC signal, identical to original
output wire snd Sound output. PWM modulated sound, needs a low pass filter outside the FPGA
input wire [7:0] k Keyport in, same as in original TED
output wire cpuenable a short enable signal used for synchronous FPGA 6502 CPU clocking
Still to do:
FPGATED is not ready yet. I just released it in this state because I did not want to keep it in a secret longer before someone else
creates it. I have plans to continue.
- write a plus4 shell using Papilio Pro platform
- Jostick emulation on keyboard (as TEDwing doesn't have joystick ports)
- scandoubler for VGA displays
- fix internal video shift mechanism for proper FLI emulation
- Chorma/Luma signal generation
- Try it in a real C16 or Plus4!
Contact: hegedusis@t-online.hu
Special Thanks to Levente Harsfalvi for the technical information on TED sound generators and for some other important hints!
Thanks to Laszlo Jozsef for the color conversion table and the Spartan6 board that I have never had time to build...

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Copyright 2013-2016 Istvan Hegedus
//
// FPGATED is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// FPGATED is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Create Date: 22:20:09 12/09/2014
// Module Name: basic_rom.v
// Project Name: FPGATED
// Target Devices: Xilinx Spartan 3E
//
// Description:
// Basic ROM synthetised to FPGA's internal SRAM. Xilinx ISE requires
// ROM_STYLE="BLOCK" parameter next to kernal array. For other vendor's
// device syntax refer to the FPGA vendor's documentation.
//
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module basic_rom(
input wire clk,
input wire [13:0] address_in,
output wire [7:0] data_out,
input wire cs
);
(* ROM_STYLE="BLOCK" *)
reg [7:0] basic [0:16383];
reg [7:0] data;
reg cs_prev=1'b1;
wire enable;
always@(posedge clk)
if(enable)
data<=basic[address_in];
always@(posedge clk)
cs_prev<=cs;
assign enable=~cs&cs_prev; // cs falling edge detection
assign data_out=(~cs)?data:8'hff;
initial begin
$readmemh("basic.hex",basic);
end
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Copyright 2013-2016 Istvan Hegedus
//
// FPGATED is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// FPGATED is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//
// Create Date: 12:02:05 10/24/2014
// Design Name: Commodore 16
// Module Name: C16.v
// Project Name: FPGATED
//
// Description:
// This module provides the top level framework for FPGATED. It implements a Commodore 16 computer without expansion port.
// It is written for Papilio FPGATED wing 1.x but can be easily modified for any other platforms.
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module C16(
input wire CLK28,
input wire RESET,
input wire WAIT,
output wire HSYNC,
output wire VSYNC,
output wire CSYNC,
output wire [3:0] RED,
output wire [3:0] GREEN,
output wire [3:0] BLUE,
output wire RAS,
output wire CAS,
output wire RW,
output wire [7:0] A,
input wire [7:0] DIN,
output wire [7:0] DOUT,
input [4:0] JOY0,
input [4:0] JOY1,
input PS2DAT,
input PS2CLK,
output IEC_DATAOUT,
input IEC_DATAIN,
output IEC_CLKOUT,
input IEC_CLKIN,
output IEC_ATNOUT,
//input IEC_ATNIN,
output IEC_RESET,
output AUDIO_L,
output AUDIO_R,
input [13:0] kernal_dl_addr,
input [7:0] kernal_dl_data,
input kernal_dl_write,
output PAL,
output RS232_TX,
output RGBS
);
wire [15:0] c16_addr;
wire [15:0] ted_addr;
wire [15:0] cpu_addr;
wire [7:0] c16_data,ted_data,ram_data,cpu_data,basic_data,kernal_data,port_in,port_out,keyport_data;
wire [7:0] keyboard_row,kbus,kbus_kbd;
wire [7:0] keyscancode;
wire keyreceived;
wire [6:0] c16_color;
wire mux,cpuenable;
wire aec,rdy;
wire keyboardio;
wire sound;
reg [7:0] c16_datalatch=8'b0;
reg sreset=1'b0;
reg [23:0] resetcounter=24'b0;
reg [15:0] c16_addrlatch=16'b0;
wire irq1;
wire keyreset;
// wire joysticks
wire [4:0] joy0_sel = (!c16_data[2])?{!JOY0[4],!JOY0[0],!JOY0[1],!JOY0[2],!JOY0[3]}:5'h1f;
wire [4:0] joy1_sel = (!c16_data[1])?{!JOY1[4],!JOY1[0],!JOY1[1],!JOY1[2],!JOY1[3]}:5'h1f;
assign kbus[3:0] = kbus_kbd[3:0] & joy0_sel[3:0] & joy1_sel[3:0];
assign kbus[5:4] = kbus_kbd[5:4]; // no joystick line connected here
assign kbus[6] = kbus_kbd[6] & joy0_sel[4];
assign kbus[7] = kbus_kbd[7] & joy1_sel[4];
// 8501 CPU
mos8501 cpu (
.clk(CLK28),
.reset(sreset),
.enable(cpuenable && !WAIT),
.irq_n(irq_n),
.data_in(c16_data),
.data_out(cpu_data),
.address(cpu_addr),
.gate_in(mux),
.rw(RW), // rw=high read, rw=low write
.port_in(port_in),
.port_out(port_out),
.rdy(rdy),
.aec(aec)
);
// TED 8360 instance
ted mos8360(
.clk(CLK28),
.addr_in(c16_addr),
.addr_out(ted_addr),
.data_in(c16_data),
.data_out(ted_data),
.rw(RW),
.cpuclk(cpuclk),
.color(c16_color),
.csync(CSYNC),
.hsync(HSYNC),
.vsync(VSYNC),
.irq(irq_n),
.ba(rdy),
.mux(mux),
.ras(RAS),
.cas(CAS),
.cs0(cs0),
.cs1(cs1),
.aec(aec),
.k(kbus),
.snd(sound),
.pal(PAL),
.cpuenable(cpuenable)
);
// Kernal rom
kernal_rom kernal(
.clk(CLK28),
.address_in(sreset?kernal_dl_addr:c16_addr[13:0]),
.data_out(kernal_data),
.data_in(kernal_dl_data),
.wr(kernal_dl_write),
.cs(cs1)
);
// Basic rom
basic_rom basic(
.clk(CLK28),
.address_in(c16_addr[13:0]),
.data_out(basic_data),
.cs(cs0)
);
// Color decoder to 12bit RGB
colors_to_rgb colordecode (
.clk(CLK28),
.color(c16_color),
.red(RED),
.green(GREEN),
.blue(BLUE)
);
// keyboard part
ps2receiver ps2rcv(
.clk(CLK28),
.ps2_clk(PS2CLK),
.ps2_data(PS2DAT),
.rx_done(keyreceived),
.ps2scancode(keyscancode)
);
c16_keymatrix keyboard(
.clk(CLK28),
.scancode(keyscancode),
.receiveflag(keyreceived),
.row(keyboard_row),
.kbus(kbus_kbd),
.keyreset(keyreset)
);
mos6529 keyport(
.clk(CLK28),
.data_in(c16_data),
.data_out(keyport_data),
.port_in(keyboard_row), // keyport 6529 in C16 is unidirectional however if we read it the last written data is read back so we feed back its output.
.port_out(keyboard_row),
.rw(RW),
.cs(keyboardio)
);
assign AUDIO_R=sound;
assign AUDIO_L=sound;
assign RGBS=1'bz; // VGA/RGBS jumper is not implemented in current version
assign RS232_TX=1'bz; // RS232 is not implemented in current version
assign keyboardio=(c16_addr[15:4]==12'hfd3)?1'b1:1'b0; // as we don't have PLA, keyport is identified here
// C16 additional motherboard functions
always @(posedge CLK28) // reset tries to emulate the length of a real reset
begin
if(RESET|keyreset) begin // reset can be triggered by reset button or CTRL+ALT+DEL from keyboard
resetcounter<=0;
sreset<=1;
end else begin
if(resetcounter==24'd16777215)
sreset<=0;
else begin
resetcounter<=resetcounter+1;
sreset<=1;
end
end
end
// assign VSYNC=1'b1; // set scart mode to RGB for TV
assign c16_addr=(~mux)?c16_addrlatch:cpu_addr&ted_addr; // C16 address bus
assign c16_data=(mux)?c16_datalatch:cpu_data&ted_data&ram_data&kernal_data&basic_data&keyport_data; // C16 data bus
always @(posedge CLK28) // addres and data bus latching emulates dynamic memory behaviour of these buses
begin
c16_datalatch<=c16_data;
c16_addrlatch<=c16_addr;
end
// external 4464 DRAM signal connections on Papilio FPGATED wing
assign A=(~mux)?c16_addr[15:8]:c16_addr[7:0]; // DRAM address multiplexer for TMS4464 address lines
assign DOUT=c16_data; // only drive external TMS4464 data lines when there is a write cycle
assign ram_data=(RW & ~CAS)?DIN:8'hff; // internal ram_data should be 0xff when external RAM's data line is in high impedance state
// connect IEC bus
assign IEC_DATAOUT=port_out[0];
assign port_in[7]=IEC_DATAIN;
assign IEC_CLKOUT=port_out[1];
assign port_in[6]=IEC_CLKIN;
assign IEC_ATNOUT=port_out[2];
//assign ATN=IEC_ATNIN;
assign IEC_RESET=sreset;
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Copyright 2013-2016 Istvan Hegedus
//
// FPGATED is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// FPGATED is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Create Date: 19:38:44 12/16/2015
// Module Name: c16_keymatrix.v
// Project Name: FPGATED
//
// Description: C16/Plus4 keyboard matrix emulation for PS2 keyboards.
//
// Revisions:
// 1.0 first release
//
//////////////////////////////////////////////////////////////////////////////////
module c16_keymatrix(
input clk,
input [7:0] scancode,
input receiveflag,
input [7:0] row,
output [7:0] kbus,
output keyreset
);
reg releaseflag=0;
reg extendedflag=0;
reg [7:0] colsel=0;
reg key_A=0,key_B=0,key_C=0,key_D=0,key_E=0,key_F=0,key_G=0,key_H=0,key_I=0,key_J=0,key_K=0,key_L=0,key_M=0,key_N=0,key_O=0,key_P=0,key_Q=0,key_R=0,key_S=0,key_T=0,key_U=0,key_V=0,key_W=0,key_X=0,key_Y=0,key_Z=0;
reg key_1=0,key_2=0,key_3=0,key_4=0,key_5=0,key_6=0,key_7=0,key_8=0,key_9=0,key_0=0,key_del=0,key_return=0,key_help=0,key_F1=0,key_F2=0,key_F3=0,key_AT=0,key_shift=0,key_comma=0,key_dot=0;
reg key_minus=0,key_colon=0,key_star=0,key_semicolon=0,key_esc=0,key_equal=0,key_plus=0,key_slash=0,key_control=0,key_space=0,key_runstop=0;
reg key_pound=0,key_down=0,key_up=0,key_left=0,key_right=0,key_home=0,key_commodore=0,key_alt=0;
wire [7:0] rowsel;
assign rowsel=~row;
assign keyreset=key_control&key_alt&key_del;
always @(posedge clk)
begin
if(receiveflag)
begin
if(scancode==8'hF0)
releaseflag<=1;
else if (scancode==8'hE0)
extendedflag<=1;
else
begin
releaseflag<=0;
if (~extendedflag) // base code keys
begin
case(scancode)
8'h1C: key_A<=~releaseflag;
8'h32: key_B<=~releaseflag;
8'h21: key_C<=~releaseflag;
8'h23: key_D<=~releaseflag;
8'h24: key_E<=~releaseflag;
8'h2B: key_F<=~releaseflag;
8'h34: key_G<=~releaseflag;
8'h33: key_H<=~releaseflag;
8'h43: key_I<=~releaseflag;
8'h3B: key_J<=~releaseflag;
8'h42: key_K<=~releaseflag;
8'h4B: key_L<=~releaseflag;
8'h3A: key_M<=~releaseflag;
8'h31: key_N<=~releaseflag;
8'h44: key_O<=~releaseflag;
8'h4D: key_P<=~releaseflag;
8'h15: key_Q<=~releaseflag;
8'h2D: key_R<=~releaseflag;
8'h1B: key_S<=~releaseflag;
8'h2C: key_T<=~releaseflag;
8'h3C: key_U<=~releaseflag;
8'h2A: key_V<=~releaseflag;
8'h1D: key_W<=~releaseflag;
8'h22: key_X<=~releaseflag;
8'h35: key_Y<=~releaseflag;
8'h1A: key_Z<=~releaseflag;
8'h69,
8'h16: key_1<=~releaseflag;
8'h72,
8'h1E: key_2<=~releaseflag;
8'h7A,
8'h26: key_3<=~releaseflag;
8'h6B,
8'h25: key_4<=~releaseflag;
8'h73,
8'h2E: key_5<=~releaseflag;
8'h74,
8'h36: key_6<=~releaseflag;
8'h6C,
8'h3D: key_7<=~releaseflag;
8'h75,
8'h3E: key_8<=~releaseflag;
8'h7D,
8'h46: key_9<=~releaseflag;
8'h70,
8'h45: key_0<=~releaseflag;
8'h66: key_del<=~releaseflag;
8'h5A: key_return<=~releaseflag;
8'h0C: key_help<=~releaseflag;
8'h05: key_F1<=~releaseflag;
8'h06: key_F2<=~releaseflag;
8'h04: key_F3<=~releaseflag;
8'h54: key_AT<=~releaseflag;
8'h12,
8'h59: key_shift<=~releaseflag;
8'h41: key_comma<=~releaseflag;
8'h49: key_dot<=~releaseflag;
8'h7B,
8'h4E: key_minus<=~releaseflag;
8'h4C: key_colon<=~releaseflag;
8'h7C,
8'h5B: key_star<=~releaseflag;
8'h52: key_semicolon<=~releaseflag;
8'h76: key_esc<=~releaseflag;
8'h5D: key_equal<=~releaseflag;
8'h79,
8'h55: key_plus<=~releaseflag;
8'h4A: key_slash<=~releaseflag;
8'h14: key_control<=~releaseflag;
8'h29: key_space<=~releaseflag;
8'h0D: key_runstop<=~releaseflag;
8'h11: key_alt<=~releaseflag;
default:;
endcase
end
else begin // extended code keys
extendedflag<=0;
case(scancode)
8'h2F: key_pound<=~releaseflag;
8'h72: key_down<=~releaseflag;
8'h75: key_up<=~releaseflag;
8'h6B: key_left<=~releaseflag;
8'h74: key_right<=~releaseflag;
8'h6C: key_home<=~releaseflag;
8'h14: key_control<=~releaseflag;
8'h1F: key_commodore<=~releaseflag;
8'h4A: key_slash<=~releaseflag;
8'h5A: key_return<=~releaseflag;
8'h71: key_del<=~releaseflag;
8'h11: key_alt<=~releaseflag;
default:;
endcase
end
end
end
end
always @(posedge clk)
begin
colsel[0]<=(key_del & rowsel[0]) | (key_3 & rowsel[1]) | (key_5 & rowsel[2]) | (key_7 & rowsel[3]) | (key_9 & rowsel[4]) | (key_down & rowsel[5]) | (key_left & rowsel[6]) | (key_1 & rowsel[7]);
colsel[1]<=(key_return & rowsel[0]) | (key_W & rowsel[1]) | (key_R & rowsel[2]) | (key_Y & rowsel[3]) | (key_I & rowsel[4]) | (key_P & rowsel[5]) | (key_star & rowsel[6]) | (key_home & rowsel[7]);
colsel[2]<=(key_pound & rowsel[0]) | (key_A & rowsel[1]) | (key_D & rowsel[2]) | (key_G & rowsel[3]) | (key_J & rowsel[4]) | (key_L & rowsel[5]) | (key_semicolon & rowsel[6]) | (key_control & rowsel[7]);
colsel[3]<=(key_help & rowsel[0]) | (key_4 & rowsel[1]) | (key_6 & rowsel[2]) | (key_8 & rowsel[3]) | (key_0 & rowsel[4]) | (key_up & rowsel[5]) | (key_right & rowsel[6]) | (key_2 & rowsel[7]);
colsel[4]<=(key_F1 & rowsel[0]) | (key_Z & rowsel[1]) | (key_C & rowsel[2]) | (key_B & rowsel[3]) | (key_M & rowsel[4]) | (key_dot & rowsel[5]) | (key_esc & rowsel[6]) | (key_space & rowsel[7]);
colsel[5]<=(key_F2 & rowsel[0]) | (key_S & rowsel[1]) | (key_F & rowsel[2]) | (key_H & rowsel[3]) | (key_K & rowsel[4]) | (key_colon & rowsel[5]) | (key_equal & rowsel[6]) | (key_commodore & rowsel[7]);
colsel[6]<=(key_F3 & rowsel[0]) | (key_E & rowsel[1]) | (key_T & rowsel[2]) | (key_U & rowsel[3]) | (key_O & rowsel[4]) | (key_minus & rowsel[5]) | (key_plus & rowsel[6]) | (key_Q & rowsel[7]);
colsel[7]<=(key_AT & rowsel[0]) | (key_shift & rowsel[1]) | (key_X & rowsel[2]) | (key_V & rowsel[3]) | (key_N & rowsel[4]) | (key_comma & rowsel[5]) | (key_slash & rowsel[6]) | (key_runstop & rowsel[7]);
end
assign kbus=~colsel;
endmodule

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
# Date created = 09:30:37 July 09, 2015
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "09:30:37 July 09, 2015"
# Revisions
PROJECT_REVISION = "c16_mist"

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
# Date created = 01:27:30 May 03, 2016
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# C64_MiST_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:40:24 MAY 17, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PIN_49 -to SDRAM_A[0]
set_location_assignment PIN_44 -to SDRAM_A[1]
set_location_assignment PIN_42 -to SDRAM_A[2]
set_location_assignment PIN_39 -to SDRAM_A[3]
set_location_assignment PIN_4 -to SDRAM_A[4]
set_location_assignment PIN_6 -to SDRAM_A[5]
set_location_assignment PIN_8 -to SDRAM_A[6]
set_location_assignment PIN_10 -to SDRAM_A[7]
set_location_assignment PIN_11 -to SDRAM_A[8]
set_location_assignment PIN_28 -to SDRAM_A[9]
set_location_assignment PIN_50 -to SDRAM_A[10]
set_location_assignment PIN_30 -to SDRAM_A[11]
set_location_assignment PIN_32 -to SDRAM_A[12]
set_location_assignment PIN_83 -to SDRAM_DQ[0]
set_location_assignment PIN_79 -to SDRAM_DQ[1]
set_location_assignment PIN_77 -to SDRAM_DQ[2]
set_location_assignment PIN_76 -to SDRAM_DQ[3]
set_location_assignment PIN_72 -to SDRAM_DQ[4]
set_location_assignment PIN_71 -to SDRAM_DQ[5]
set_location_assignment PIN_69 -to SDRAM_DQ[6]
set_location_assignment PIN_68 -to SDRAM_DQ[7]
set_location_assignment PIN_86 -to SDRAM_DQ[8]
set_location_assignment PIN_87 -to SDRAM_DQ[9]
set_location_assignment PIN_98 -to SDRAM_DQ[10]
set_location_assignment PIN_99 -to SDRAM_DQ[11]
set_location_assignment PIN_100 -to SDRAM_DQ[12]
set_location_assignment PIN_101 -to SDRAM_DQ[13]
set_location_assignment PIN_103 -to SDRAM_DQ[14]
set_location_assignment PIN_104 -to SDRAM_DQ[15]
set_location_assignment PIN_58 -to SDRAM_BA[0]
set_location_assignment PIN_51 -to SDRAM_BA[1]
set_location_assignment PIN_85 -to SDRAM_DQMH
set_location_assignment PIN_67 -to SDRAM_DQML
set_location_assignment PIN_60 -to SDRAM_nRAS
set_location_assignment PIN_64 -to SDRAM_nCAS
set_location_assignment PIN_66 -to SDRAM_nWE
set_location_assignment PIN_59 -to SDRAM_nCS
set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
# Classic Timing Assignments
# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name TOP_LEVEL_ENTITY c16_mist
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name SAVE_DISK_SPACE OFF
# Fitter Assignments
# ==================
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE OPTIMISTIC
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name FITTER_EFFORT "AUTO FIT"
# Assembler Assignments
# =====================
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# Advanced I/O Timing Assignments
# ===============================
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
# ------------------------
# start ENTITY(C64_MiST)
# Pin & Location Assignments
# ==========================
# Fitter Assignments
# ==================
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(C64_MiST)
# ----------------------
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[2]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[3]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[4]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[5]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[6]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[7]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[8]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[9]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[10]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[11]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[12]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[13]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[14]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[15]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[2]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[3]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[4]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[5]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[6]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[7]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[8]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[9]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[10]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[11]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[12]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[0]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[1]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[2]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[3]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[4]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[5]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[6]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[7]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[8]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[9]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[10]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[11]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[12]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[13]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[14]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[15]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[13]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[14]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[15]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQML
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQMH
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nRAS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCAS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nWE
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CKE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_HS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_VS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to CONF_DATA0
set_global_assignment -name QIP_FILE pll_ntsc.qip
set_global_assignment -name QIP_FILE pll_pal.qip
set_global_assignment -name VERILOG_FILE data_io.v
set_global_assignment -name VERILOG_FILE sdram.v
set_global_assignment -name VERILOG_FILE osd.v
set_global_assignment -name VERILOG_FILE scandoubler.v
set_global_assignment -name VHDL_FILE cpu65xx_fast.vhd
set_global_assignment -name VHDL_FILE cpu65xx_e.vhd
set_global_assignment -name VERILOG_FILE user_io.v
set_global_assignment -name VERILOG_FILE ted.v
set_global_assignment -name VERILOG_FILE mos8501.v
set_global_assignment -name VERILOG_FILE mos6529.v
set_global_assignment -name VERILOG_FILE kernal_rom.v
set_global_assignment -name VERILOG_FILE colors_to_rgb.v
set_global_assignment -name VERILOG_FILE c16_mist.v
set_global_assignment -name VERILOG_FILE c16_keymatrix.v
set_global_assignment -name VERILOG_FILE c16.v
set_global_assignment -name VERILOG_FILE basic_rom.v
set_global_assignment -name SIGNALTAP_FILE stp1.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

601
cores/c16/c16_mist.v Normal file
View File

@@ -0,0 +1,601 @@
//
// c16_mist.v - C16 for the MiST
//
// https://github.com/mist-devel
//
// Copyright (c) 2015 Till Harbaum <till@harbaum.org>
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module c16_mist (
input CLOCK_27,
// LED outputs
output LED, // LED Yellow
// SDRAM interface
inout [15:0] SDRAM_DQ, // SDRAM Data bus 16 Bits
output [12:0] SDRAM_A, // SDRAM Address bus 13 Bits
output SDRAM_DQML, // SDRAM Low-byte Data Mask
output SDRAM_DQMH, // SDRAM High-byte Data Mask
output SDRAM_nWE, // SDRAM Write Enable
output SDRAM_nCAS, // SDRAM Column Address Strobe
output SDRAM_nRAS, // SDRAM Row Address Strobe
output SDRAM_nCS, // SDRAM Chip Select
output [1:0] SDRAM_BA, // SDRAM Bank Address
output SDRAM_CLK, // SDRAM Clock
output SDRAM_CKE, // SDRAM Clock Enable
// SPI interface to arm io controller
output SPI_DO,
input SPI_DI,
input SPI_SCK,
input SPI_SS2,
input SPI_SS3,
input SPI_SS4,
input CONF_DATA0,
output AUDIO_L, // sigma-delta DAC output left
output AUDIO_R, // sigma-delta DAC output right
output VGA_HS,
output VGA_VS,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B
);
// -------------------------------------------------------------------------
// ------------------------------ user_io ----------------------------------
// -------------------------------------------------------------------------
// user_io implements a connection to the io controller and receives various
// kind of user input from there (keyboard, buttons, mouse). It is also used
// by the fake SD card to exchange data with the real sd card connected to the
// io controller
// the configuration string is returned to the io controller to allow
// it to control the menu on the OSD
parameter CONF_STR = {
"C16;PRG;",
"O2,Scanlines,Off,On;",
"O3,Joysticks,Normal,Swapped;",
"T4,Reset"
};
parameter CONF_STR_LEN = 8+20+28+8;
// the status register is controlled by the on screen display (OSD)
wire [7:0] status;
wire tv15khz;
wire scanlines = status[2];
wire joystick_swap = status[3];
wire osd_reset = status[4];
wire [1:0] buttons;
wire [7:0] js0, js1;
wire [7:0] jsA = joystick_swap?js1:js0;
wire [7:0] jsB = joystick_swap?js0:js1;
wire ps2_kbd_clk, ps2_kbd_data;
wire ps2_mouse_clk, ps2_mouse_data;
// generate ps2_clock
wire ps2_clock = ps2_clk_div[10]; // ~12khz
reg [10:0] ps2_clk_div;
always @(posedge clk28)
ps2_clk_div <= ps2_clk_div + 7'd1;
// -------------------------------------------------------------------------
// ---------------- interface to the external sdram ------------------------
// -------------------------------------------------------------------------
// SDRAM control signals
assign SDRAM_CKE = 1'b1;
// ram access signals from c16
wire [15:0] c16_sdram_addr = { c16_a_hi, c16_a_low };
wire [7:0] c16_sdram_data = c16_dout;
wire c16_sdram_wr = !c16_cas && !c16_rw;
wire c16_sdram_oe = !c16_cas && c16_rw;
// ram access signals from io controller
// ioctl_sdram_write
// ioctl_sdram_addr
// ioctl_sdram_data
// multiplex c16 and ioctl signals
wire [15:0] mux_sdram_addr = c16_wait?ioctl_sdram_addr:c16_sdram_addr;
wire [7:0] mux_sdram_data = c16_wait?ioctl_sdram_data:c16_sdram_data;
wire mux_sdram_wr = c16_wait?ioctl_sdram_write:c16_sdram_wr;
wire mux_sdram_oe = c16_wait?1'b0:c16_sdram_oe;
wire [15:0] sdram_din = { mux_sdram_data, mux_sdram_data };
wire [24:0] sdram_addr = { 10'h00, mux_sdram_addr[15:1] }; // 64k mapping
// wire [24:0] sdram_addr = { 12'h00, mux_sdram_addr[13:1] }; // 16k mapping
wire sdram_wr = mux_sdram_wr;
wire sdram_oe = mux_sdram_oe;
wire [1:0] sdram_ds = { mux_sdram_addr[0], !mux_sdram_addr[0] };
// only c16 reads from sdram
wire [15:0] sdram_dout;
wire [7:0] c16_din = zp_overwrite?zp_ovl_dout:
(c16_a_low[0]?sdram_dout[15:8]:sdram_dout[7:0]);
assign SDRAM_CLK = ~clk28;
// synchronize sdram state machine with the ras/cas phases of the c16
reg last_ras;
reg [3:0] clkdiv;
wire clkref = clkdiv[3];
always @(posedge clk28) begin
if(!c16_ras && last_ras) begin
clkdiv <= 4'd0;
last_ras <= c16_ras;
end else
clkdiv <= clkdiv + 4'd1;
end
// latch/demultiplex dram address
reg [7:0] c16_a_low;
always @(negedge c16_ras)
c16_a_low <= c16_a;
reg [7:0] c16_a_hi;
always @(negedge c16_cas)
c16_a_hi <= c16_a;
sdram sdram (
// interface to the MT48LC16M16 chip
.sd_data ( SDRAM_DQ ),
.sd_addr ( SDRAM_A ),
.sd_dqm ( {SDRAM_DQMH, SDRAM_DQML} ),
.sd_cs ( SDRAM_nCS ),
.sd_ba ( SDRAM_BA ),
.sd_we ( SDRAM_nWE ),
.sd_ras ( SDRAM_nRAS ),
.sd_cas ( SDRAM_nCAS ),
// system interface
.clk ( clk28 ),
.clkref ( clkref ),
.init ( !pll_locked ),
// cpu interface
.din ( sdram_din ),
.addr ( sdram_addr ),
.we ( sdram_wr ),
.oe ( sdram_oe ),
.ds ( sdram_ds ),
.dout ( sdram_dout )
);
// ---------------------------------------------------------------------------------
// -------------------------------------- reset ------------------------------------
// ---------------------------------------------------------------------------------
reg [31:0] reset_cnt;
wire reset = (reset_cnt != 0);
always @(posedge clk28) begin
// long reset on startup and when io controller reboots
if(status[0] || !pll_locked)
reset_cnt <= 32'd28000000;
// short reset on reset button, reset osd or when io controller is
// done downloading
else if(buttons[1] || osd_reset || rom_download)
reset_cnt <= 32'd65536;
else if(reset_cnt != 0)
reset_cnt <= reset_cnt - 32'd1;
end
// include user_io module for arm controller communication
user_io #(.STRLEN(CONF_STR_LEN)) user_io (
.conf_str ( CONF_STR ),
.SPI_CLK ( SPI_SCK ),
.SPI_SS_IO ( CONF_DATA0 ),
.SPI_MISO ( SPI_DO ),
.SPI_MOSI ( SPI_DI ),
.scandoubler_disable ( tv15khz ),
.buttons ( buttons ),
.joystick_0 ( js0 ),
.joystick_1 ( js1 ),
// ps2 interface
.ps2_clk ( ps2_clock ),
.ps2_kbd_clk ( ps2_kbd_clk ),
.ps2_kbd_data ( ps2_kbd_data ),
.ps2_mouse_clk ( ps2_mouse_clk ),
.ps2_mouse_data ( ps2_mouse_data ),
.status ( status )
);
// ---------------------------------------------------------------------------------
// ------------------------------ prg memory injection -----------------------------
// ---------------------------------------------------------------------------------
wire ioctl_wr;
wire [15:0] ioctl_addr;
wire [7:0] ioctl_data;
wire [4:0] ioctl_index;
wire ioctl_downloading;
wire rom_download = ioctl_downloading && (ioctl_index == 5'd0);
wire prg_download = ioctl_downloading && (ioctl_index == 5'd1);
// halt cpu when it's done with the current cycle
reg c16_wait;
always @(posedge c16_ras)
c16_wait <= prg_download;
data_io data_io (
// SPI interface
.sck ( SPI_SCK ),
.ss ( SPI_SS2 ),
.sdi ( SPI_DI ),
// ram interface
.downloading ( ioctl_downloading ),
.index ( ioctl_index ),
.clk ( clk28 ),
.wr ( ioctl_wr ),
.a ( ioctl_addr ),
.d ( ioctl_data )
);
// magic zero page shadow registers to allow the injector to set the
// basic program end pointers automagically after injection
reg [15:0] reg_2d;
reg [15:0] reg_2f;
reg [15:0] reg_31;
reg [15:0] reg_ae;
wire zp_2d_sel = c16_sdram_addr == 16'h002d;
wire zp_2e_sel = c16_sdram_addr == 16'h002e;
wire zp_2f_sel = c16_sdram_addr == 16'h002f;
wire zp_30_sel = c16_sdram_addr == 16'h0030;
wire zp_31_sel = c16_sdram_addr == 16'h0031;
wire zp_32_sel = c16_sdram_addr == 16'h0032;
wire zp_ae_sel = c16_sdram_addr == 16'h00ae;
wire zp_af_sel = c16_sdram_addr == 16'h00af;
wire zp_overwrite =
zp_2d_sel || zp_2e_sel || zp_2f_sel || zp_30_sel ||
zp_31_sel || zp_32_sel || zp_ae_sel || zp_af_sel;
reg zp_cas_delay, zp_sel;
reg zp_dl_delay, zp_dl;
always @(posedge clk28) begin
// write pulse one cycle after falling edge of cas to make sure address
// is stable
zp_cas_delay <= c16_cas;
zp_sel <= !c16_cas && zp_cas_delay;
zp_dl_delay <= prg_download;
zp_dl <= !prg_download && zp_dl_delay;
if(zp_dl) begin
// registers are automatically adjusted at the end of the
// download/injection
// the registers to be set have been taken from the vice emulator
reg_2d <= ioctl_sdram_addr + 16'd1;
reg_2f <= ioctl_sdram_addr + 16'd1;
reg_31 <= ioctl_sdram_addr + 16'd1;
reg_ae <= ioctl_sdram_addr + 16'd1;
end else if(zp_sel && !c16_rw) begin
// cpu writes registers
if(zp_2d_sel) reg_2d[ 7:0] <= c16_dout;
if(zp_2e_sel) reg_2d[15:8] <= c16_dout;
if(zp_2f_sel) reg_2f[ 7:0] <= c16_dout;
if(zp_30_sel) reg_2f[15:8] <= c16_dout;
if(zp_31_sel) reg_31[ 7:0] <= c16_dout;
if(zp_32_sel) reg_31[15:8] <= c16_dout;
if(zp_ae_sel) reg_ae[ 7:0] <= c16_dout;
if(zp_af_sel) reg_ae[15:8] <= c16_dout;
end
end
wire [7:0] zp_ovl_dout =
zp_2d_sel?reg_2d[7:0]:zp_2e_sel?reg_2d[15:8]:
zp_2f_sel?reg_2f[7:0]:zp_30_sel?reg_2f[15:8]:
zp_31_sel?reg_31[7:0]:zp_32_sel?reg_31[15:8]:
zp_ae_sel?reg_ae[7:0]:zp_af_sel?reg_ae[15:8]:
8'hff;
// the address taken from the first to bytes of a prg file tell
// us where the file is to go in memory
reg [15:0] ioctl_load_addr /* synthesis noprune */;
reg ioctl_ram_wr /* synthesis noprune */;
reg ioctl_sdram_write /* synthesis noprune */;
reg [15:0] ioctl_sdram_addr /* synthesis noprune */;
reg [7:0] ioctl_sdram_data /* synthesis noprune */;
always @(negedge c16_ras) begin
ioctl_sdram_write <= ioctl_ram_wr;
if(ioctl_ram_wr) begin
ioctl_sdram_addr <= ioctl_load_addr + ioctl_addr - 16'd2;
ioctl_sdram_data <= ioctl_data;
end
end
// address starts counting with 0
always @(negedge clk28) begin
if(ioctl_sdram_write)
ioctl_ram_wr <= 1'b0;
// data io has a byte for us
if(ioctl_wr) begin
if(ioctl_addr == 16'h0000)
ioctl_load_addr[7:0] <= ioctl_data;
else if (ioctl_addr == 16'h0001)
ioctl_load_addr[15:8] <= ioctl_data;
else
// io controller sent a new byte. Store it until it can be
// saved in RAM
ioctl_ram_wr <= 1'b1;
end
end
// ---------------------------------------------------------------------------------
// ------------------------------ the on screen display ----------------------------
// ---------------------------------------------------------------------------------
// in 15khz mode feed the c16 video directly into the OSD,
// bypassing the scan doubler
wire [5:0] osd_r_in = tv15khz?{c16_r, 2'b00}:video_r;
wire [5:0] osd_g_in = tv15khz?{c16_g, 2'b00}:video_g;
wire [5:0] osd_b_in = tv15khz?{c16_b, 2'b00}:video_b;
wire osd_hs_in = tv15khz?!c16_hs:video_hs;
wire osd_vs_in = tv15khz?!c16_vs:video_vs;
wire osd_clk = tv15khz?clk7:clk28;
// include the on screen display
osd #(11,0,5) osd (
.pclk ( osd_clk ),
// spi for OSD
.sdi ( SPI_DI ),
.sck ( SPI_SCK ),
.ss ( SPI_SS3 ),
.red_in ( osd_r_in ),
.green_in ( osd_g_in ),
.blue_in ( osd_b_in ),
.hs_in ( osd_hs_in ),
.vs_in ( osd_vs_in ),
.red_out ( VGA_R ),
.green_out ( VGA_G ),
.blue_out ( VGA_B )
);
// in 15khz tv mode directly use the c16's composite sync. Otherwise the VGA
// output is driven from the sync signals generated by the scan doubler. In
// 15khz mode the VS signal is used as the RGB detect signal on the SCART
// connector and thus needs to be driven to 1
assign VGA_HS = tv15khz?c16_cs:video_hs;
assign VGA_VS = tv15khz?1'b1:video_vs;
wire video_hs, video_vs;
wire [5:0] video_r;
wire [5:0] video_g;
wire [5:0] video_b;
scandoubler scandoubler (
// system interface
.clk_sys ( clk28 ),
// scanlines (00-none 01-25% 10-50% 11-75%)
.scanlines ( scanlines?2'b10:2'b00 ),
// shifter video interface
.hs_in ( !c16_hs ),
.vs_in ( !c16_vs ),
.r_in ( c16_r ),
.g_in ( c16_g ),
.b_in ( c16_b ),
// output interface
.hs_out ( video_hs ),
.vs_out ( video_vs ),
.r_out ( video_r ),
.g_out ( video_g ),
.b_out ( video_b )
);
// ---------------------------------------------------------------------------------
// ------------------------------------ c16 core -----------------------------------
// ---------------------------------------------------------------------------------
// c16 generated video signals
wire c16_hs, c16_vs, c16_cs;
wire [3:0] c16_r;
wire [3:0] c16_g;
wire [3:0] c16_b;
wire c16_pal;
// c16 generated ram access signals
wire c16_ras;
wire c16_cas;
wire c16_rw;
wire [7:0] c16_a;
wire [7:0] c16_dout;
reg kernal_dl_wr;
reg [7:0] kernal_dl_data;
reg [13:0] kernal_dl_addr;
wire ioctl_kernal_wr = rom_download && ioctl_wr;
reg last_ioctl_wr;
always @(negedge clk28) begin
last_ioctl_wr <= ioctl_kernal_wr;
if(ioctl_kernal_wr && !last_ioctl_wr) begin
kernal_dl_data <= ioctl_data;
kernal_dl_addr <= ioctl_addr[13:0];
kernal_dl_wr <= 1'b1;
end else
kernal_dl_wr <= 1'b0;
end
// include the c16 itself
C16 c16 (
.CLK28 ( clk28 ),
.RESET ( reset ),
.WAIT ( c16_wait ),
.HSYNC ( c16_hs ),
.VSYNC ( c16_vs ),
.CSYNC ( c16_cs ),
.RED ( c16_r ),
.GREEN ( c16_g ),
.BLUE ( c16_b ),
.RAS ( c16_ras ),
.CAS ( c16_cas ),
.RW ( c16_rw ),
.A ( c16_a ),
.DOUT ( c16_dout ),
.DIN ( c16_din ),
.JOY0 ( jsB[4:0] ),
.JOY1 ( jsA[4:0] ),
.PS2DAT ( ps2_kbd_data ),
.PS2CLK ( ps2_kbd_clk ),
.kernal_dl_addr ( kernal_dl_addr ),
.kernal_dl_data ( kernal_dl_data ),
.kernal_dl_write ( kernal_dl_wr),
/*
.IEC_DATAOUT ( c16_iec_data_o ),
.IEC_DATAIN ( c16_iec_data_i ),
.IEC_CLKOUT ( c16_iec_clk_o ),
.IEC_CLKIN ( c16_iec_clk_i ),
.IEC_ATNOUT ( c16_iec_atn_o ),
// .IEC_ATNIN,
.IEC_RESET ( ),
*/
.IEC_DATAIN ( 1'b1 ),
.IEC_CLKIN ( 1'b1 ),
.AUDIO_L ( AUDIO_L ),
.AUDIO_R ( AUDIO_R ),
.PAL ( c16_pal ),
.RS232_TX (),
.RGBS ()
);
// ---------------------------------------------------------------------------------
// ------------------------------- clock generation --------------------------------
// ---------------------------------------------------------------------------------
// the FPGATED uses two different clocks for NTSC and PAL mode.
// Switching the clocks may crash the system. We might need to force a reset it.
wire clk28 = c16_pal?clk28_pal:clk28_ntsc;
wire pll_locked = pll_pal_locked && pll_ntsc_locked;
// tv15hkz has quarter the pixel rate, so we need a 7mhz clock for the OSD
reg clk7;
always @(posedge clk14)
clk7 <= !clk7;
reg clk14;
always @(posedge clk28)
clk14 <= !clk14;
// A PLL to derive the system clock from the MiSTs 27MHz
wire pll_pal_locked, clk28_pal;
pll_pal pll_pal (
.inclk0( CLOCK_27 ),
.c0( clk28_pal ),
.locked( pll_pal_locked )
);
wire pll_ntsc_locked, clk28_ntsc;
pll_ntsc pll_ntsc (
.inclk0( CLOCK_27 ),
.c0( clk28_ntsc ),
.locked( pll_ntsc_locked )
);
/*
// ---------------------------------------------------------------------------------
// ----------------------------------- floppy 1541 ---------------------------------
// ---------------------------------------------------------------------------------
wire [7:0] led_disk;
assign LED = !led_disk[6];
wire c16_iec_atn_o;
wire c16_iec_data_o;
wire c16_iec_clk_o;
wire c16_iec_atn_i = !((!c16_iec_atn_o) & (!c1541_iec_atn_o) );
wire c16_iec_data_i = !((!c16_iec_data_o) & (!c1541_iec_data_o));
wire c16_iec_clk_i = !((!c16_iec_clk_o) & (!c1541_iec_clk_o) );
wire c1541_iec_atn_o;
wire c1541_iec_data_o;
wire c1541_iec_clk_o;
wire c1541_iec_atn_i = c16_iec_atn_i;
wire c1541_iec_data_i = c16_iec_data_i;
wire c1541_iec_clk_i = c16_iec_clk_i;
c1541_sd c1541_sd (
.clk32 ( clk32 ),
.clk18 ( clk28 ), // MiST uses virtual SPI SD, so any clock can be used.
.reset ( reset ),
.c1541rom_addr ( 14'h0000 ),
.c1541rom_data ( 8'h00 ),
.c1541rom_wr ( 1'b0 ),
.disk_change (),
.disk_num ( 10'd0 ), // not seletable by f8 or similar
.iec_atn_i ( c1541_iec_atn_i ),
.iec_data_i ( c1541_iec_data_i ),
.iec_clk_i ( c1541_iec_clk_i ),
.iec_atn_o ( c1541_iec_atn_o ),
.iec_data_o ( c1541_iec_data_o ),
.iec_clk_o ( c1541_iec_clk_o ),
.sd_dat ( 1'b1 ),
.sd_dat3 (),
.sd_cmd (),
.sd_clk (),
.led ( led_disk )
);
*/
endmodule

183
cores/c16/colors_to_rgb.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Copyright 2013-2016 Istvan Hegedus
//
// FPGATED is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// FPGATED is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Create Date: 22:03:30 11/20/2014
// Design Name: Commodore Plus/4 color value conversion to 12bit RGB values
// Module Name: colors_to_rgb.v
// Project Name: FPGATED
// Target Devices: Xilinx Spartan 3E
//
// Description:
// Converts TED's 7 bit color codes to 12 bit RGB values used by video DAC.
// 12 bit DAC values from Jozsef Laszlo
//
// Revisions:
// Revision 0.1 - File Created
//
//////////////////////////////////////////////////////////////////////////////////
module colors_to_rgb(
input clk,
input [6:0] color,
output [3:0] red,
output [3:0] green,
output [3:0] blue
);
reg [11:0] color_lut [127:0];
reg [11:0] rgbcolor;
initial
begin
color_lut[0]=12'b0000_0000_0000;
color_lut[1]=12'b0010_0010_0010;
color_lut[2]=12'b0101_0000_0000;
color_lut[3]=12'b0000_0011_0011;
color_lut[4]=12'b0100_0000_0101;
color_lut[5]=12'b0000_0100_0000;
color_lut[6]=12'b0001_0001_0111;
color_lut[7]=12'b0010_0010_0000;
color_lut[8]=12'b0100_0001_0000;
color_lut[9]=12'b0011_0010_0000;
color_lut[10]=12'b0001_0011_0000;
color_lut[11]=12'b0101_0000_0010;
color_lut[12]=12'b0000_0011_0001;
color_lut[13]=12'b0000_0010_0110;
color_lut[14]=12'b0001_0001_0111;
color_lut[15]=12'b0000_0011_0000;
color_lut[16]=12'b0000_0000_0000;
color_lut[17]=12'b0010_0010_0010;
color_lut[18]=12'b0110_0001_0001;
color_lut[19]=12'b0000_0100_0100;
color_lut[20]=12'b0101_0000_0110;
color_lut[21]=12'b0000_0100_0000;
color_lut[22]=12'b0010_0010_1000;
color_lut[23]=12'b0011_0011_0000;
color_lut[24]=12'b0101_0010_0000;
color_lut[25]=12'b0100_0010_0000;
color_lut[26]=12'b0010_0100_0000;
color_lut[27]=12'b0110_0001_0011;
color_lut[28]=12'b0000_0100_0010;
color_lut[29]=12'b0000_0011_0111;
color_lut[30]=12'b0010_0001_1000;
color_lut[31]=12'b0001_0100_0000;
color_lut[32]=12'b0000_0000_0000;
color_lut[33]=12'b0011_0011_0011;
color_lut[34]=12'b0110_0010_0010;
color_lut[35]=12'b0000_0101_0101;
color_lut[36]=12'b0110_0001_0111;
color_lut[37]=12'b0000_0101_0000;
color_lut[38]=12'b0010_0011_1001;
color_lut[39]=12'b0100_0100_0000;
color_lut[40]=12'b0110_0010_0000;
color_lut[41]=12'b0101_0011_0000;
color_lut[42]=12'b0010_0101_0000;
color_lut[43]=12'b0110_0001_0100;
color_lut[44]=12'b0000_0101_0011;
color_lut[45]=12'b0001_0011_1000;
color_lut[46]=12'b0011_0010_1001;
color_lut[47]=12'b0001_0101_0000;
color_lut[48]=12'b0000_0000_0000;
color_lut[49]=12'b0100_0100_0100;
color_lut[50]=12'b0111_0011_0011;
color_lut[51]=12'b0001_0110_0110;
color_lut[52]=12'b0111_0010_1000;
color_lut[53]=12'b0001_0110_0010;
color_lut[54]=12'b0100_0100_1010;
color_lut[55]=12'b0101_0101_0000;
color_lut[56]=12'b0111_0100_0001;
color_lut[57]=12'b0110_0100_0000;
color_lut[58]=12'b0011_0110_0000;
color_lut[59]=12'b0111_0011_0101;
color_lut[60]=12'b0001_0110_0100;
color_lut[61]=12'b0010_0100_1001;
color_lut[62]=12'b0100_0011_1010;
color_lut[63]=12'b0011_0110_0000;
color_lut[64]=12'b0000_0000_0000;
color_lut[65]=12'b0110_0110_0110;
color_lut[66]=12'b1010_0101_0101;
color_lut[67]=12'b0011_1000_1000;
color_lut[68]=12'b1001_0100_1010;
color_lut[69]=12'b0100_1000_0100;
color_lut[70]=12'b0110_0110_1100;
color_lut[71]=12'b0111_0111_0001;
color_lut[72]=12'b1001_0110_0011;
color_lut[73]=12'b1000_0110_0010;
color_lut[74]=12'b0110_1000_0001;
color_lut[75]=12'b1010_0101_0111;
color_lut[76]=12'b0011_1000_0110;
color_lut[77]=12'b0100_0111_1011;
color_lut[78]=12'b0110_0101_1100;
color_lut[79]=12'b0101_1000_0010;
color_lut[80]=12'b0000_0000_0000;
color_lut[81]=12'b1000_1000_1000;
color_lut[82]=12'b1011_0111_0111;
color_lut[83]=12'b0101_1001_1001;
color_lut[84]=12'b1011_0110_1011;
color_lut[85]=12'b0101_1010_0101;
color_lut[86]=12'b0111_0111_1110;
color_lut[87]=12'b1001_1001_0010;
color_lut[88]=12'b1011_0111_0101;
color_lut[89]=12'b1010_1000_0011;
color_lut[90]=12'b0111_1001_0010;
color_lut[91]=12'b1011_0110_1001;
color_lut[92]=12'b0101_1010_1000;
color_lut[93]=12'b0110_1000_1101;
color_lut[94]=12'b1000_0111_1110;
color_lut[95]=12'b0110_1010_0011;
color_lut[96]=12'b0000_0000_0000;
color_lut[97]=12'b1011_1011_1011;
color_lut[98]=12'b1110_1001_1001;
color_lut[99]=12'b1000_1100_1100;
color_lut[100]=12'b1101_1001_1110;
color_lut[101]=12'b1000_1101_1000;
color_lut[102]=12'b1010_1010_1111;
color_lut[103]=12'b1011_1011_0101;
color_lut[104]=12'b1101_1010_1000;
color_lut[105]=12'b1100_1011_0110;
color_lut[106]=12'b1010_1100_0101;
color_lut[107]=12'b1110_1001_1011;
color_lut[108]=12'b0111_1100_1010;
color_lut[109]=12'b1001_1011_1111;
color_lut[110]=12'b1010_1010_1111;
color_lut[111]=12'b1001_1100_0110;
color_lut[112]=12'b0000_0000_0000;
color_lut[113]=12'b1110_1110_1110;
color_lut[114]=12'b1111_1101_1101;
color_lut[115]=12'b1011_1111_1111;
color_lut[116]=12'b1111_1100_1111;
color_lut[117]=12'b1100_1111_1100;
color_lut[118]=12'b1110_1110_1111;
color_lut[119]=12'b1111_1111_1001;
color_lut[120]=12'b1111_1110_1011;
color_lut[121]=12'b1111_1110_1010;
color_lut[122]=12'b1110_1111_1001;
color_lut[123]=12'b1111_1101_1111;
color_lut[124]=12'b1011_1111_1110;
color_lut[125]=12'b1100_1110_1111;
color_lut[126]=12'b1110_1101_1111;
color_lut[127]=12'b1101_1111_1010;
end
always @(posedge clk)
begin
rgbcolor<=color_lut[color];
end
assign red=rgbcolor[11:8];
assign green=rgbcolor[7:4];
assign blue=rgbcolor[3:0];
endmodule

48
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-- -----------------------------------------------------------------------
--
-- FPGA 64
--
-- A fully functional commodore 64 implementation in a single FPGA
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com/fpga64.html
-- -----------------------------------------------------------------------
--
-- Interface to 6502/6510 core
--
-- -----------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity cpu65xx is
generic (
pipelineOpcode : boolean;
pipelineAluMux : boolean;
pipelineAluOut : boolean
);
port (
clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
nmi_n : in std_logic;
irq_n : in std_logic;
so_n : in std_logic := '1';
di : in unsigned(7 downto 0);
do : out unsigned(7 downto 0);
addr : out unsigned(15 downto 0);
we : out std_logic;
debugOpcode : out unsigned(7 downto 0);
debugPc : out unsigned(15 downto 0);
debugA : out unsigned(7 downto 0);
debugX : out unsigned(7 downto 0);
debugY : out unsigned(7 downto 0);
debugS : out unsigned(7 downto 0)
);
end cpu65xx;

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127
cores/c16/data_io.v Normal file
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//
// data_io.v
//
// io controller writable ram for the MiST board
// http://code.google.com/p/mist-board/
//
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module data_io (
// io controller spi interface
input sck,
input ss,
input sdi,
output downloading, // signal indicating an active download
output [15:0] size, // number of bytes in input buffer
output reg [4:0] index, // menu index used to upload the file
// external ram interface
input clk,
output reg wr,
output reg [15:0] a,
output [7:0] d
);
assign d = data;
parameter START_ADDR = 16'h0000;
assign size = addr;
// *********************************************************************************
// spi client
// *********************************************************************************
// this core supports only the display related OSD commands
// of the minimig
reg [6:0] sbuf;
reg [7:0] cmd /* synthesis noprune */;
reg [7:0] data /* synthesis noprune */;
reg [4:0] cnt /* synthesis noprune */;
reg [15:0] addr /* synthesis noprune */;
reg rclk /* synthesis noprune */;
localparam UIO_FILE_TX = 8'h53;
localparam UIO_FILE_TX_DAT = 8'h54;
localparam UIO_FILE_INDEX = 8'h55;
localparam UIO_FILE_INFO = 8'h56;
assign downloading = downloading_reg;
reg downloading_reg = 1'b0;
// data_io has its own SPI interface to the io controller
always@(posedge sck, posedge ss) begin
if(ss == 1'b1)
cnt <= 5'd0;
else begin
rclk <= 1'b0;
// don't shift in last bit. It is evaluated directly
// when writing to ram
if(cnt != 15)
sbuf <= { sbuf[5:0], sdi};
// increase target address after write
if(rclk)
addr <= addr + 16'd1;
// count 0-7 8-15 8-15 ...
if(cnt < 15) cnt <= cnt + 4'd1;
else cnt <= 4'd8;
// finished command byte
if(cnt == 7)
cmd <= {sbuf, sdi};
// prepare/end transmission
if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
// prepare
if(sdi) begin
addr <= START_ADDR;
downloading_reg <= 1'b1;
end else
downloading_reg <= 1'b0;
end
// command 0x54: UIO_FILE_TX
if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
data <= {sbuf, sdi};
rclk <= 1'b1;
a <= addr;
end
// expose file (menu) index
if((cmd == UIO_FILE_INDEX) && (cnt == 15))
index <= {sbuf[3:0], sdi};
end
end
reg rclkD, rclkD2;
always@(posedge clk) begin
// bring rclk from spi clock domain into c64 clock domain
rclkD <= rclk;
rclkD2 <= rclkD;
wr <= 1'b0;
if(rclkD && !rclkD2)
wr <= 1'b1;
end
endmodule

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GNU GENERAL PUBLIC LICENSE
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Also add information on how to contact you by electronic and paper mail.
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16384
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Copyright 2013-2016 Istvan Hegedus
//
// FPGATED is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// FPGATED is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Create Date: 17:12:57 12/05/2014
// Design Name: Commodore 16/Plus 4 Kernal ROM
// Module Name: kernal_rom
// Project Name: FPGATED
// Description:
// Kernal ROM synthetised to FPGA's internal SRAM. Xilinx ISE requires
// ROM_STYLE="BLOCK" parameter next to kernal array. For other vendor's
// device syntax refer to the FPGA vendor's documentation.
//
// Choose the proper Kernal file version depending on NTSC or PAL system
// and comment out the ones which are not needed.
// If you want to convert your own kernal image to compatible version use
// bin2hex.pl perl script to convert it to .hex format.
//////////////////////////////////////////////////////////////////////////////////
module kernal_rom(
input wire clk,
input wire [13:0] address_in,
output wire [7:0] data_out,
input wire [7:0] data_in,
input wire wr,
input wire cs
);
(* ROM_STYLE="BLOCK" *)
reg [7:0] kernal [0:16383];
reg [7:0] data;
reg cs_prev=1'b1;
wire enable;
initial begin
// uncomment the Kernal version to use
//$readmemh("Diag264_PAL.hex",kernal);
//$readmemh("Diag264_NTSC.hex",kernal);
$readmemh("kernal_PAL.hex",kernal);
//$readmemh("kernal_NTSC.hex",kernal);
//$readmemh("Jiffy_PAL.hex",kernal);
// Note that Jiffy DOS is not free so Jiffy_PAL.hex is not included with FPGATED source code
end
always@(posedge clk) begin
if (wr)
kernal[address_in] <= data_in;
if(enable)
data<=kernal[address_in];
end
always@(posedge clk)
cs_prev<=cs;
assign enable=~cs&cs_prev; // cs falling edge detection
assign data_out=(~cs)?data:8'hff;
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Copyright 2013-2016 Istvan Hegedus
//
// FPGATED is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// FPGATED is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Create Date: 09:08:17 12/17/2015
// Design Name: FPGATED
// Module Name: mos6529.v
// Description: MOS 6529 IC emulation.
//
// Revision:
// 0.1 first release
// 1.0 chip read bug fixed 5/04/2016
//
// Additional Comments:
// CS signal is high active while in real IC it is low active.
//////////////////////////////////////////////////////////////////////////////////
module mos6529(
input clk,
input [7:0] data_in,
output wire [7:0] data_out,
input [7:0] port_in,
output wire [7:0] port_out,
input rw,
input cs
);
reg [7:0] iodata=0;
assign port_out=iodata;
assign data_out=(cs & rw)?iodata:8'hff;
always @(posedge clk)
begin
if(cs)
if(rw)
iodata<=port_in;
else
iodata<=data_in;
end
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Copyright 2013-2016 Istvan Hegedus
//
// FPGATED is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// FPGATED is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Create Date: 16:36:31 12/10/2014
// Module Name: mos8501
// Project Name: FPGATED
// Target Devices: Xilinx Spartan 3E
//
// Description:
//
// Dependencies:
// This module contains an instance of Peter Wendrich's 6502 CPU core from FPGA64 project.
// The CPU core is used and included with Peter's permission and not developed by me.
// The mos8501 shell around the CPU core is written by me, but inspired by fpga64 6510 CPU
// shell. It might shows certain similarities.
//
// Revision history:
// 0.1 first release using incorrect 6502 core from fpga64 project
// 1.0 CPU core replaced to cpu65xx_fast.vhd from fpga64 project
//
//////////////////////////////////////////////////////////////////////////////////
module mos8501(
input clk,
input reset,
input enable,
input irq_n,
input [7:0] data_in,
output wire [7:0] data_out,
output [15:0] address,
input gate_in,
output rw,
input [7:0] port_in,
output [7:0] port_out,
input rdy,
input aec
);
wire we,enable_cpu;
wire [15:0] core_address;
wire [7:0] core_data_out;
wire port_access;
reg [7:0] data_out_reg,core_data_in,port_io;
reg [7:0] port_dir=8'b0;
reg [7:0] port_data=8'b0;
reg rw_reg,aec_reg;
// 6502 CPU core
cpu65xx #(.pipelineOpcode("\false"),.pipelineAluMux("\false"),.pipelineAluOut("\false"))
cpu_core(
.clk(clk),
.reset(reset),
.enable(enable_cpu),
.nmi_n(1'b1),
.irq_n(irq_n),
.di(core_data_in),
.do(core_data_out),
.addr(core_address),
.we(we),
.so_n(1'b1),
.debugOpcode(),
.debugPc(),
.debugA(),
.debugX(),
.debugY(),
.debugS()
);
assign address=(aec)?core_address:16'hffff; // address tri state emulated for easy bus signal combining
always @(posedge clk)
begin
if(gate_in)
begin
if(port_access==1'b1 && we==1'b1)
if(address[0]==1'b0) // when port direction register is written, data on bus is last read byte which is 0x00
data_out_reg<=8'h00;
else // when port register is written, data on bus is last read byte which is 0x01
data_out_reg<=8'h01;
else
data_out_reg<=core_data_out; // when mux is high, data out register is updated
end
else
begin
data_out_reg<=data_out_reg; // hold off data out during write cycle
end
end
always @(posedge clk)
begin
if(gate_in)
rw_reg<=~we;
end
always @(posedge clk) // registering aec for 1 clk cycle delay
begin
aec_reg<=aec;
end
assign rw=(~aec_reg)?1'b1:rw_reg;
assign data_out=(~aec_reg | gate_in | rw)?8'hff:data_out_reg; // when mux is low data out register is allowed to outside
assign port_access=(address[15:1]==0)?1'b1:1'b0;
// IO port part of cpu
always @(posedge clk) //writing port registers
begin
if(reset)
begin
port_dir<=0;
port_data<=0;
end
else if (enable)
if(port_access & we)
if(address[0]==0)
port_dir<=core_data_out;
else
port_data<=core_data_out;
end
always @* // reading port registers
begin
core_data_in=data_in;
if (port_access & ~we)
if(address[0]==0)
core_data_in=port_dir;
else
core_data_in=port_io;
end
// if direction bit is 0 then data is from chip's port
// if direction bit is 1 then data is from data port register filled earlier by CPU
always @*
begin
if(port_dir[0]==1'b0)
port_io[0]=port_in[0];
else
port_io[0]=port_data[0];
if(port_dir[1]==1'b0)
port_io[1]=port_in[1];
else
port_io[1]=port_data[1];
if(port_dir[2]==1'b0)
port_io[2]=port_in[2];
else
port_io[2]=port_data[2];
if(port_dir[3]==1'b0)
port_io[3]=port_in[3];
else
port_io[3]=port_data[3];
if(port_dir[4]==1'b0)
port_io[4]=port_in[4];
else
port_io[4]=port_data[4];
if(port_dir[5]==1'b0)
port_io[5]=port_in[5];
else
port_io[5]=port_data[5];
if(port_dir[6]==1'b0)
port_io[6]=port_in[6];
else
port_io[6]=port_data[6];
if(port_dir[7]==1'b0)
port_io[7]=port_in[7];
else
port_io[7]=port_data[7];
end
assign port_out=port_data;
assign enable_cpu=(~rdy & ~we)?1'b0:enable; // When RDY is low and cpu would do a read, halt cpu
endmodule

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//
// osd.v
//
// A simple OSD implementation. Can be hooked up between a cores
// VGA output and the physical VGA pins
//
// Sinclair QL for the MiST
// https://github.com/mist-devel
//
// Copyright (c) 2015 Till Harbaum <till@harbaum.org>
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module osd (
// OSDs pixel clock, should be synchronous to cores pixel clock to
// avoid jitter.
input pclk,
// SPI interface
input sck,
input ss,
input sdi,
// VGA signals coming from core
input [5:0] red_in,
input [5:0] green_in,
input [5:0] blue_in,
input hs_in,
input vs_in,
// VGA signals going to video connector
output [5:0] red_out,
output [5:0] green_out,
output [5:0] blue_out,
output hs_out,
output vs_out
);
parameter OSD_X_OFFSET = 10'd0;
parameter OSD_Y_OFFSET = 10'd0;
parameter OSD_COLOR = 3'd0;
localparam OSD_WIDTH = 10'd256;
localparam OSD_HEIGHT = 10'd128;
// *********************************************************************************
// spi client
// *********************************************************************************
// this core supports only the display related OSD commands
// of the minimig
reg [7:0] sbuf;
reg [7:0] cmd;
reg [4:0] cnt;
reg [10:0] bcnt;
reg osd_enable;
reg [7:0] osd_buffer [2047:0]; // the OSD buffer itself
// the OSD has its own SPI interface to the io controller
always@(posedge sck, posedge ss) begin
if(ss == 1'b1) begin
cnt <= 5'd0;
bcnt <= 11'd0;
end else begin
sbuf <= { sbuf[6:0], sdi};
// 0:7 is command, rest payload
if(cnt < 15)
cnt <= cnt + 4'd1;
else
cnt <= 4'd8;
if(cnt == 7) begin
cmd <= {sbuf[6:0], sdi};
// lower three command bits are line address
bcnt <= { sbuf[1:0], sdi, 8'h00};
// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
if(sbuf[6:3] == 4'b0100)
osd_enable <= sdi;
end
// command 0x20: OSDCMDWRITE
if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
osd_buffer[bcnt] <= {sbuf[6:0], sdi};
bcnt <= bcnt + 11'd1;
end
end
end
// *********************************************************************************
// video timing and sync polarity anaylsis
// *********************************************************************************
// horizontal counter
reg [9:0] h_cnt;
reg hsD, hsD2;
reg [9:0] hs_low, hs_high;
wire hs_pol = hs_high < hs_low;
wire [9:0] h_dsp_width = hs_pol?hs_low:hs_high;
wire [9:0] h_dsp_ctr = { 1'b0, h_dsp_width[9:1] };
always @(posedge pclk) begin
// bring hsync into local clock domain
hsD <= hs_in;
hsD2 <= hsD;
// falling edge of hs_in
if(!hsD && hsD2) begin
h_cnt <= 10'd0;
hs_high <= h_cnt;
end
// rising edge of hs_in
else if(hsD && !hsD2) begin
h_cnt <= 10'd0;
hs_low <= h_cnt;
end
else
h_cnt <= h_cnt + 10'd1;
end
// vertical counter
reg [9:0] v_cnt;
reg vsD, vsD2;
reg [9:0] vs_low, vs_high;
wire vs_pol = vs_high < vs_low;
wire [9:0] v_dsp_width = vs_pol?vs_low:vs_high;
wire [9:0] v_dsp_ctr = { 1'b0, v_dsp_width[9:1] };
always @(posedge hs_in) begin
// bring vsync into local clock domain
vsD <= vs_in;
vsD2 <= vsD;
// falling edge of vs_in
if(!vsD && vsD2) begin
v_cnt <= 10'd0;
vs_high <= v_cnt;
end
// rising edge of vs_in
else if(vsD && !vsD2) begin
v_cnt <= 10'd0;
vs_low <= v_cnt;
end
else
v_cnt <= v_cnt + 10'd1;
end
// area in which OSD is being displayed
wire [9:0] h_osd_start = h_dsp_ctr + OSD_X_OFFSET - (OSD_WIDTH >> 1);
wire [9:0] h_osd_end = h_dsp_ctr + OSD_X_OFFSET + (OSD_WIDTH >> 1) - 1;
wire [9:0] v_osd_start = v_dsp_ctr + OSD_Y_OFFSET - (OSD_HEIGHT >> 1);
wire [9:0] v_osd_end = v_dsp_ctr + OSD_Y_OFFSET + (OSD_HEIGHT >> 1) - 1;
reg h_osd_active, v_osd_active;
always @(posedge pclk) begin
if(hs_in != hs_pol) begin
if(h_cnt == h_osd_start) h_osd_active <= 1'b1;
if(h_cnt == h_osd_end) h_osd_active <= 1'b0;
end
if(vs_in != vs_pol) begin
if(v_cnt == v_osd_start) v_osd_active <= 1'b1;
if(v_cnt == v_osd_end) v_osd_active <= 1'b0;
end
end
wire osd_de = osd_enable && h_osd_active && v_osd_active;
wire [7:0] osd_hcnt = h_cnt - h_osd_start + 7'd1; // one pixel offset for osd_byte register
wire [6:0] osd_vcnt = v_cnt - v_osd_start;
wire osd_pixel = osd_byte[osd_vcnt[3:1]];
reg [7:0] osd_byte;
always @(posedge pclk)
osd_byte <= osd_buffer[{osd_vcnt[6:4], osd_hcnt}];
wire [2:0] osd_color = OSD_COLOR;
assign red_out = !osd_de?red_in: {osd_pixel, osd_pixel, osd_color[2], red_in[5:3] };
assign green_out = !osd_de?green_in:{osd_pixel, osd_pixel, osd_color[1], green_in[5:3]};
assign blue_out = !osd_de?blue_in: {osd_pixel, osd_pixel, osd_color[0], blue_in[5:3] };
assign hs_out = hs_in;
assign vs_out = vs_in;
endmodule

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cores/c16/pll.ppf Normal file
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<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone III" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
<global>
<pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="c0" direction="output" scope="external" source="clock" />
<pin name="c1" direction="output" scope="external" source="clock" />
<pin name="locked" direction="output" scope="external" />
</global>
</pinplan>

4
cores/c16/pll_ntsc.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_ntsc.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_ntsc.ppf"]

309
cores/c16/pll_ntsc.v Normal file
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// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll_ntsc.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll_ntsc (
inclk0,
c0,
locked);
input inclk0;
output c0;
output locked;
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire5 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire locked = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.inclk (sub_wire4),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 270000,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 286363,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_ntsc",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "183"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "28.636299"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "191"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.63630000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_ntsc.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.000"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "270000"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "286363"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

4
cores/c16/pll_pal.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_pal.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_pal.ppf"]

309
cores/c16/pll_pal.v Normal file
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@@ -0,0 +1,309 @@
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll_pal.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll_pal (
inclk0,
c0,
locked);
input inclk0;
output c0;
output locked;
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire5 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire locked = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.inclk (sub_wire4),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 39,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 41,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_pal",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "39"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "28.384615"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "41"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.37500000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_pal.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.000"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "39"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "41"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Copyright 2013-2016 Istvan Hegedus
//
// FPGATED is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// FPGATED is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Create Date: 11:30:06 12/14/2015
// Module Name: ps2receiver.v
// Project Name: FPGATED
// Description: PS2 keyboard receiver
//
//
//
// Revision:
// Revision 1.0 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ps2receiver(
input clk,
input ps2_clk,
input ps2_data,
output reg rx_done,
output reg [7:0] ps2scancode
);
reg ps2clkreg=1'b0,prev_ps2clkreg=1'b0;
reg [3:0] receivedbits=4'b0;
reg [11:0] watchdog=12'd2900; // ~ 100us watchdog period with 28MHz clock
reg [7:0] ps2clkfilter;
reg [10:0] shiftreg;
always @(posedge clk) // filtering ps2 clock line glitches
begin
ps2clkfilter<={ps2clkfilter[6:0],ps2_clk};
if(ps2clkfilter==8'h00)
ps2clkreg<=0;
else if (ps2clkfilter==8'hff)
ps2clkreg<=1;
prev_ps2clkreg<=ps2clkreg; // this is needed for clock edge detection
end
always @(posedge clk)
begin
rx_done<=0; // rx_done is active only for one clk cycle
if(watchdog==0) // when watchdog timer expires, reset received bits
receivedbits<=0;
else watchdog<=watchdog-1;
if(prev_ps2clkreg & ~ps2clkreg) // falling edge of ps2 clock
begin
watchdog<=12'd2900; // reload watchdog timer
shiftreg<={ps2_data,shiftreg[10:1]};
receivedbits<=receivedbits+1;
end
if(receivedbits==4'd11)
begin
ps2scancode<=shiftreg[9:1];
rx_done<=1;
receivedbits<=0;
end
end
endmodule

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//
// scandoubler.v
//
// Copyright (c) 2015 Till Harbaum <till@harbaum.org>
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
// TODO: Delay vsync one line
module scandoubler
(
// system interface
input clk_sys,
// scanlines (00-none 01-25% 10-50% 11-75%)
input [1:0] scanlines,
// shifter video interface
input hs_in,
input vs_in,
input [3:0] r_in,
input [3:0] g_in,
input [3:0] b_in,
// output interface
output reg hs_out,
output reg vs_out,
output reg [5:0] r_out,
output reg [5:0] g_out,
output reg [5:0] b_out
);
// try to detect changes in input signal and lock input clock gate
// it
reg last_hs_in;
reg [1:0] i_div;
wire ce_x1 = (i_div == 2'b01);
wire ce_x2 = i_div[0];
always @(posedge clk_sys) begin
if(last_hs_in != hs_in) begin
i_div <= 2'b00;
last_hs_in <= hs_in;
end else begin
i_div <= i_div + 2'd1;
end
end
// --------------------- create output signals -----------------
// latch everything once more to make it glitch free and apply scanline effect
reg scanline;
always @(posedge clk_sys) begin
if(ce_x2) begin
hs_out <= hs_sd;
vs_out <= vs_in;
// reset scanlines at every new screen
if(vs_out != vs_in) scanline <= 0;
// toggle scanlines at begin of every hsync
if(hs_out && !hs_sd) scanline <= !scanline;
// if no scanlines or not a scanline
if(!scanline || !scanlines) begin
r_out <= { sd_out[11:8], 2'b00 };
g_out <= { sd_out[7:4], 2'b00 };
b_out <= { sd_out[3:0], 2'b00 };
end else begin
case(scanlines)
1: begin // reduce 25% = 1/2 + 1/4
r_out <= {1'b0, sd_out[11:8], 1'b0} + {2'b00, sd_out[11:8]};
g_out <= {1'b0, sd_out[7:4], 1'b0} + {2'b00, sd_out[7:4] };
b_out <= {1'b0, sd_out[3:0], 1'b0} + {2'b00, sd_out[3:0] };
end
2: begin // reduce 50% = 1/2
r_out <= {1'b0, sd_out[11:8], 1'b0};
g_out <= {1'b0, sd_out[7:4], 1'b0};
b_out <= {1'b0, sd_out[3:0], 1'b0};
end
3: begin // reduce 75% = 1/4
r_out <= {2'b00, sd_out[11:8]};
g_out <= {2'b00, sd_out[7:4]};
b_out <= {2'b00, sd_out[3:0]};
end
endcase
end
end
end
// scan doubler output register
reg [11:0] sd_out;
// ==================================================================
// ======================== the line buffers ========================
// ==================================================================
// 2 lines of 512 pixels 3*4 bit RGB
(* ramstyle = "no_rw_check" *) reg [11:0] sd_buffer[1023:0];
// use alternating sd_buffers when storing/reading data
reg line_toggle;
// total hsync time (in 16MHz cycles), hs_total reaches 1024
reg [8:0] hs_max;
reg [8:0] hs_rise;
reg [8:0] hcnt;
always @(posedge clk_sys) begin
reg hsD, vsD;
if(ce_x1) begin
hsD <= hs_in;
// falling edge of hsync indicates start of line
if(hsD && !hs_in) begin
hs_max <= hcnt;
hcnt <= 9'd0;
end else begin
hcnt <= hcnt + 9'd1;
end
// save position of rising edge
if(!hsD && hs_in) hs_rise <= hcnt;
vsD <= vs_in;
if(vsD != vs_in) line_toggle <= 0;
// begin of incoming hsync
if(hsD && !hs_in) line_toggle <= !line_toggle;
sd_buffer[{line_toggle, hcnt}] <= {r_in, g_in, b_in};
end
end
// ==================================================================
// ==================== output timing generation ====================
// ==================================================================
reg [8:0] sd_hcnt;
reg hs_sd;
// timing generation runs 32 MHz (twice the input signal analysis speed)
always @(posedge clk_sys) begin
reg hsD;
if(ce_x2) begin
hsD <= hs_in;
// output counter synchronous to input and at twice the rate
sd_hcnt <= sd_hcnt + 9'd1;
if(hsD && !hs_in) sd_hcnt <= hs_max;
if(sd_hcnt == hs_max) sd_hcnt <= 0;
// replicate horizontal sync at twice the speed
if(sd_hcnt == hs_max) hs_sd <= 0;
if(sd_hcnt == hs_rise) hs_sd <= 1;
// read data from line sd_buffer
sd_out <= sd_buffer[{~line_toggle, sd_hcnt}];
end
end
endmodule

150
cores/c16/sdram.v Normal file
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//
// sdram.v
//
// sdram controller implementation for the MiST board
// https://github.com/mist-devel
//
// Copyright (c) 2015 Till Harbaum <till@harbaum.org>
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module sdram (
// interface to the MT48LC16M16 chip
inout [15:0] sd_data, // 16 bit bidirectional data bus
output reg [12:0] sd_addr, // 13 bit multiplexed address bus
output reg [1:0] sd_dqm, // two byte masks
output reg[1:0] sd_ba, // two banks
output sd_cs, // a single chip select
output sd_we, // write enable
output sd_ras, // row address select
output sd_cas, // columns address select
// cpu/chipset interface
input init, // init signal after FPGA config to initialize RAM
input clk, // sdram is accessed at up to 128MHz
input clkref, // reference clock to sync to
input [15:0] din, // data input from chipset/cpu
output [15:0] dout, // data output to chipset/cpu
input [24:0] addr, // 25 bit word address
input [1:0] ds, // data strobe for hi/low byte
input oe, // cpu/chipset requests read
input we // cpu/chipset requests write
);
// no burst configured
localparam RASCAS_DELAY = 3'd2; // tRCD>=20ns -> 2 cycles@64MHz
localparam BURST_LENGTH = 3'b000; // 000=none, 001=2, 010=4, 011=8
localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
localparam CAS_LATENCY = 3'd3; // 2/3 allowed
localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
// ---------------------------------------------------------------------
// ------------------------ cycle state machine ------------------------
// ---------------------------------------------------------------------
localparam STATE_IDLE = 4'd0; // first state in cycle
localparam STATE_CMD_START = 4'd1; // state in which a new command can be started
localparam STATE_CMD_CONT = STATE_CMD_START + RASCAS_DELAY - 3'd1; // 4 command can be continued
localparam STATE_LAST = 4'd15; // last state in cycle
reg [3:0] q /* synthesis noprune */;
always @(posedge clk) begin
// 32Mhz counter synchronous to 4 Mhz clock
// force counter to pass state 5->6 exactly after the rising edge of clkref
// since clkref is two clocks early
if(((q == 14) && ( clkref == 0)) ||
((q == 15) && ( clkref == 1)) ||
((q != 14) && (q != 15)))
q <= q + 4'd1;
end
// ---------------------------------------------------------------------
// --------------------------- startup/reset ---------------------------
// ---------------------------------------------------------------------
// wait 1ms (32 clkref cycles) after FPGA config is done before going
// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
reg [4:0] reset;
always @(posedge clk) begin
if(init) reset <= 5'h1f;
else if((q == STATE_LAST) && (reset != 0))
reset <= reset - 5'd1;
end
// ---------------------------------------------------------------------
// ------------------ generate ram control signals ---------------------
// ---------------------------------------------------------------------
// all possible commands
localparam CMD_INHIBIT = 4'b1111;
localparam CMD_NOP = 4'b0111;
localparam CMD_ACTIVE = 4'b0011;
localparam CMD_READ = 4'b0101;
localparam CMD_WRITE = 4'b0100;
localparam CMD_BURST_TERMINATE = 4'b0110;
localparam CMD_PRECHARGE = 4'b0010;
localparam CMD_AUTO_REFRESH = 4'b0001;
localparam CMD_LOAD_MODE = 4'b0000;
reg [3:0] sd_cmd; // current command sent to sd ram
// drive control signals according to current command
assign sd_cs = sd_cmd[3];
assign sd_ras = sd_cmd[2];
assign sd_cas = sd_cmd[1];
assign sd_we = sd_cmd[0];
assign sd_data = we?din:16'bZZZZZZZZZZZZZZZZ;
assign dout = sd_data;
always @(posedge clk) begin
sd_cmd <= CMD_INHIBIT;
if(reset != 0) begin
sd_ba <= 2'b00;
sd_dqm <= 2'b00;
if(reset == 13) sd_addr <= 13'b0010000000000;
else sd_addr <= MODE;
if(q == STATE_IDLE) begin
if(reset == 13) sd_cmd <= CMD_PRECHARGE;
if(reset == 2) sd_cmd <= CMD_LOAD_MODE;
end
end else begin
if(q <= STATE_CMD_START) begin
sd_addr <= addr[20:8];
sd_ba <= addr[22:21];
sd_dqm <= { !ds[1], !ds[0] };
end else
sd_addr <= { 4'b0010, addr[23], addr[7:0]};
if(q == STATE_IDLE) begin
if(we || oe) sd_cmd <= CMD_ACTIVE;
else sd_cmd <= CMD_AUTO_REFRESH;
end else if(q == STATE_CMD_CONT) begin
if(we) sd_cmd <= CMD_WRITE;
else if(oe) sd_cmd <= CMD_READ;
end
end
end
endmodule

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//
// user_io.v - interface to MIST arm io controller
//
// Sinclair QL for the MiST
// https://github.com/mist-devel
//
// Copyright (c) 2015 Till Harbaum <till@harbaum.org>
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// parameter STRLEN and the actual length of conf_str have to match
module user_io #(parameter STRLEN=0) (
input [(8*STRLEN)-1:0] conf_str,
input SPI_CLK,
input SPI_SS_IO,
output reg SPI_MISO,
input SPI_MOSI,
output reg [7:0] joystick_0,
output reg [7:0] joystick_1,
output reg [15:0] joystick_analog_0,
output reg [15:0] joystick_analog_1,
output [1:0] buttons,
output [1:0] switches,
output scandoubler_disable,
output reg [7:0] status,
// connection to sd card emulation
input [31:0] sd_lba,
input sd_rd,
input sd_wr,
output reg sd_ack,
input sd_conf,
input sd_sdhc,
output [7:0] sd_dout, // valid on rising edge of sd_dout_strobe
output reg sd_dout_strobe,
input [7:0] sd_din,
output reg sd_din_strobe,
output reg sd_change,
// ps2 keyboard emulation
input ps2_clk, // 12-16khz provided by core
output ps2_kbd_clk,
output reg ps2_kbd_data,
output ps2_mouse_clk,
output reg ps2_mouse_data,
// serial com port
input [7:0] serial_data,
input serial_strobe
);
reg [6:0] sbuf;
reg [7:0] cmd;
reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
reg [7:0] byte_cnt; // counts bytes
reg [5:0] joystick0;
reg [5:0] joystick1;
reg [7:0] but_sw;
reg [2:0] stick_idx;
assign buttons = but_sw[1:0];
assign switches = but_sw[3:2];
assign scandoubler_disable = but_sw[4];
assign sd_dout = { sbuf, SPI_MOSI};
// this variant of user_io is for 8 bit cores (type == a4) only
wire [7:0] core_type = 8'ha4;
// command byte read by the io controller
wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd };
// filter spi clock. the 8 bit gate delay is ~2.5ns in total
wire [7:0] spi_sck_D = { spi_sck_D[6:0], SPI_CLK } /* synthesis keep */;
wire spi_sck = (spi_sck && spi_sck_D != 8'h00) || (!spi_sck && spi_sck_D == 8'hff);
// drive MISO only when transmitting core id
always@(negedge spi_sck or posedge SPI_SS_IO) begin
if(SPI_SS_IO == 1) begin
SPI_MISO <= 1'bZ;
end else begin
// first byte returned is always core type, further bytes are
// command dependent
if(byte_cnt == 0) begin
SPI_MISO <= core_type[~bit_cnt];
end else begin
// reading serial fifo
if(cmd == 8'h1b) begin
// send alternating flag byte and data
if(byte_cnt[0]) SPI_MISO <= serial_out_status[~bit_cnt];
else SPI_MISO <= serial_out_byte[~bit_cnt];
end
// reading config string
else if(cmd == 8'h14) begin
// returning a byte from string
if(byte_cnt < STRLEN + 1)
SPI_MISO <= conf_str[{STRLEN - byte_cnt,~bit_cnt}];
else
SPI_MISO <= 1'b0;
end
// reading sd card status
else if(cmd == 8'h16) begin
if(byte_cnt == 1)
SPI_MISO <= sd_cmd[~bit_cnt];
else if((byte_cnt >= 2) && (byte_cnt < 6))
SPI_MISO <= sd_lba[{5-byte_cnt, ~bit_cnt}];
else
SPI_MISO <= 1'b0;
end
// reading sd card write data
else if(cmd == 8'h18)
SPI_MISO <= sd_din[~bit_cnt];
else
SPI_MISO <= 1'b0;
end
end
end
// ---------------- PS2 ---------------------
// 8 byte fifos to store ps2 bytes
localparam PS2_FIFO_BITS = 3;
// keyboard
reg [7:0] ps2_kbd_fifo [(2**PS2_FIFO_BITS)-1:0];
reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
// ps2 transmitter state machine
reg [3:0] ps2_kbd_tx_state;
reg [7:0] ps2_kbd_tx_byte;
reg ps2_kbd_parity;
assign ps2_kbd_clk = ps2_clk || (ps2_kbd_tx_state == 0);
// ps2 transmitter
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
reg ps2_kbd_r_inc;
always@(posedge ps2_clk) begin
ps2_kbd_r_inc <= 1'b0;
if(ps2_kbd_r_inc)
ps2_kbd_rptr <= ps2_kbd_rptr + 1;
// transmitter is idle?
if(ps2_kbd_tx_state == 0) begin
// data in fifo present?
if(ps2_kbd_wptr != ps2_kbd_rptr) begin
// load tx register from fifo
ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
ps2_kbd_r_inc <= 1'b1;
// reset parity
ps2_kbd_parity <= 1'b1;
// start transmitter
ps2_kbd_tx_state <= 4'd1;
// put start bit on data line
ps2_kbd_data <= 1'b0; // start bit is 0
end
end else begin
// transmission of 8 data bits
if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits
ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
if(ps2_kbd_tx_byte[0])
ps2_kbd_parity <= !ps2_kbd_parity;
end
// transmission of parity
if(ps2_kbd_tx_state == 9)
ps2_kbd_data <= ps2_kbd_parity;
// transmission of stop bit
if(ps2_kbd_tx_state == 10)
ps2_kbd_data <= 1'b1; // stop bit is 1
// advance state machine
if(ps2_kbd_tx_state < 11)
ps2_kbd_tx_state <= ps2_kbd_tx_state + 4'd1;
else
ps2_kbd_tx_state <= 4'd0;
end
end
// mouse
reg [7:0] ps2_mouse_fifo [(2**PS2_FIFO_BITS)-1:0];
reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
// ps2 transmitter state machine
reg [3:0] ps2_mouse_tx_state;
reg [7:0] ps2_mouse_tx_byte;
reg ps2_mouse_parity;
assign ps2_mouse_clk = ps2_clk || (ps2_mouse_tx_state == 0);
// ps2 transmitter
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
reg ps2_mouse_r_inc;
always@(posedge ps2_clk) begin
ps2_mouse_r_inc <= 1'b0;
if(ps2_mouse_r_inc)
ps2_mouse_rptr <= ps2_mouse_rptr + 1;
// transmitter is idle?
if(ps2_mouse_tx_state == 0) begin
// data in fifo present?
if(ps2_mouse_wptr != ps2_mouse_rptr) begin
// load tx register from fifo
ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
ps2_mouse_r_inc <= 1'b1;
// reset parity
ps2_mouse_parity <= 1'b1;
// start transmitter
ps2_mouse_tx_state <= 4'd1;
// put start bit on data line
ps2_mouse_data <= 1'b0; // start bit is 0
end
end else begin
// transmission of 8 data bits
if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits
ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
if(ps2_mouse_tx_byte[0])
ps2_mouse_parity <= !ps2_mouse_parity;
end
// transmission of parity
if(ps2_mouse_tx_state == 9)
ps2_mouse_data <= ps2_mouse_parity;
// transmission of stop bit
if(ps2_mouse_tx_state == 10)
ps2_mouse_data <= 1'b1; // stop bit is 1
// advance state machine
if(ps2_mouse_tx_state < 11)
ps2_mouse_tx_state <= ps2_mouse_tx_state + 4'd1;
else
ps2_mouse_tx_state <= 4'd0;
end
end
// fifo to receive serial data from core to be forwarded to io controller
// 16 byte fifo to store serial bytes
localparam SERIAL_OUT_FIFO_BITS = 6;
reg [7:0] serial_out_fifo [(2**SERIAL_OUT_FIFO_BITS)-1:0];
reg [SERIAL_OUT_FIFO_BITS-1:0] serial_out_wptr;
reg [SERIAL_OUT_FIFO_BITS-1:0] serial_out_rptr;
wire serial_out_data_available = serial_out_wptr != serial_out_rptr;
wire [7:0] serial_out_byte = serial_out_fifo[serial_out_rptr] /* synthesis keep */;
wire [7:0] serial_out_status = { 7'b1000000, serial_out_data_available};
// status[0] is reset signal from io controller and is thus used to flush
// the fifo
always @(posedge serial_strobe or posedge status[0]) begin
if(status[0] == 1) begin
serial_out_wptr <= 0;
end else begin
serial_out_fifo[serial_out_wptr] <= serial_data;
serial_out_wptr <= serial_out_wptr + 1;
end
end
always@(negedge spi_sck or posedge status[0]) begin
if(status[0] == 1) begin
serial_out_rptr <= 0;
end else begin
if((byte_cnt != 0) && (cmd == 8'h1b)) begin
// read last bit -> advance read pointer
if((bit_cnt == 7) && !byte_cnt[0] && serial_out_data_available)
serial_out_rptr <= serial_out_rptr + 1;
end
end
end
// SPI receiver
always@(posedge spi_sck or posedge SPI_SS_IO) begin
if(SPI_SS_IO == 1) begin
bit_cnt <= 3'd0;
byte_cnt <= 8'd0;
sd_ack <= 1'b0;
sd_dout_strobe <= 1'b0;
sd_din_strobe <= 1'b0;
sd_change <= 1'b0;
end else begin
sd_dout_strobe <= 1'b0;
sd_din_strobe <= 1'b0;
if(bit_cnt != 7)
sbuf[6:0] <= { sbuf[5:0], SPI_MOSI };
bit_cnt <= bit_cnt + 3'd1;
if((bit_cnt == 7)&&(byte_cnt != 8'd255))
byte_cnt <= byte_cnt + 8'd1;
// finished reading command byte
if(bit_cnt == 7) begin
if(byte_cnt == 0) begin
cmd <= { sbuf, SPI_MOSI};
// fetch first byte when sectore FPGA->IO command has been seen
if({ sbuf, SPI_MOSI} == 8'h18)
sd_din_strobe <= 1'b1;
if(({ sbuf, SPI_MOSI} == 8'h17) || ({ sbuf, SPI_MOSI} == 8'h18))
sd_ack <= 1'b1;
end else begin
// buttons and switches
if(cmd == 8'h01)
but_sw <= { sbuf, SPI_MOSI };
if(cmd == 8'h02)
joystick_0 <= { sbuf, SPI_MOSI };
if(cmd == 8'h03)
joystick_1 <= { sbuf, SPI_MOSI };
if(cmd == 8'h04) begin
// store incoming ps2 mouse bytes
ps2_mouse_fifo[ps2_mouse_wptr] <= { sbuf, SPI_MOSI };
ps2_mouse_wptr <= ps2_mouse_wptr + 1;
end
if(cmd == 8'h05) begin
// store incoming ps2 keyboard bytes
ps2_kbd_fifo[ps2_kbd_wptr] <= { sbuf, SPI_MOSI };
ps2_kbd_wptr <= ps2_kbd_wptr + 1;
end
if(cmd == 8'h15)
status <= { sbuf[6:0], SPI_MOSI };
// send sector IO -> FPGA
if(cmd == 8'h17) begin
// flag that download begins
sd_dout_strobe <= 1'b1;
end
// send sector FPGA -> IO
if(cmd == 8'h18)
sd_din_strobe <= 1'b1;
// send SD config IO -> FPGA
if(cmd == 8'h19) begin
// flag that download begins
// sd card knows data is config if sd_dout_strobe is asserted
// with sd_ack still being inactive (low)
sd_dout_strobe <= 1'b1;
end
// joystick analog
if(cmd == 8'h1a) begin
// first byte is joystick indes
if(byte_cnt == 1)
stick_idx <= { sbuf[1:0], SPI_MOSI };
else if(byte_cnt == 2) begin
// second byte is x axis
if(stick_idx == 0)
joystick_analog_0[15:8] <= { sbuf, SPI_MOSI };
else if(stick_idx == 1)
joystick_analog_1[15:8] <= { sbuf, SPI_MOSI };
end else if(byte_cnt == 3) begin
// third byte is y axis
if(stick_idx == 0)
joystick_analog_0[7:0] <= { sbuf, SPI_MOSI };
else if(stick_idx == 1)
joystick_analog_1[7:0] <= { sbuf, SPI_MOSI };
end
end
// set sd card status. The fact that this register is being
// set by the arm controller indicates a possible disk change
if(cmd == 8'h1c)
sd_change <= 1'b1;
end
end
end
end
endmodule