Merge pull request #61 from gyurco/c16

C16 disk + cpu updates

cores/c16/c1541/c1541_logic.vhd

@@ -123,8 +123,8 @@ begin
         clk_1M_pulse <= '1';
       end if;
       -- if count = "000100000" then -- DAR divide by 33 (otherwise real c64 miss EOI acknowledge)
-      if count = "000011110" then -- TH divide by 31
-      count := (others => '0');   -- DAR	
+      if count = "000011111" then -- TH - C16 MiST: zero after 31, restart from 1
+      count := (0 => '1', others => '0');
 			else                        -- DAR
       count := std_logic_vector(unsigned(count) + 1);
 			end if;                     -- DAR

cores/c16/c16_mist.qsf

@@ -323,6 +323,7 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
 set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to CONF_DATA0
 set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001
 set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 set_global_assignment -name VHDL_FILE gen_ram.vhd
 set_global_assignment -name QIP_FILE pll_ntsc.qip
 set_global_assignment -name QIP_FILE pll_pal.qip
@@ -330,8 +331,6 @@ set_global_assignment -name VERILOG_FILE data_io.v
 set_global_assignment -name VERILOG_FILE sdram.v
 set_global_assignment -name VERILOG_FILE osd.v
 set_global_assignment -name VERILOG_FILE scandoubler.v
-set_global_assignment -name VHDL_FILE cpu65xx_fast.vhd
-set_global_assignment -name VHDL_FILE cpu65xx_e.vhd
 set_global_assignment -name VERILOG_FILE user_io.v
 set_global_assignment -name VERILOG_FILE ted.v
 set_global_assignment -name VERILOG_FILE mos8501.v
@@ -354,5 +353,4 @@ set_global_assignment -name SYSTEMVERILOG_FILE c1541/mist_sd_card.sv
 set_global_assignment -name VHDL_FILE t65/T65_Pack.vhd
 set_global_assignment -name VHDL_FILE t65/T65_MCode.vhd
 set_global_assignment -name VHDL_FILE t65/T65_ALU.vhd
-set_global_assignment -name VHDL_FILE t65/T65.vhd
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name VHDL_FILE t65/T65.vhd

cores/c16/cpu65xx_e.vhd

@@ -1,48 +0,0 @@
--- -----------------------------------------------------------------------
---
---                                 FPGA 64
---
---     A fully functional commodore 64 implementation in a single FPGA
---
--- -----------------------------------------------------------------------
--- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
--- http://www.syntiac.com/fpga64.html
--- -----------------------------------------------------------------------
---
--- Interface to 6502/6510 core
---
--- -----------------------------------------------------------------------
-
-library IEEE;
-use ieee.std_logic_1164.ALL;
-use ieee.numeric_std.ALL;
-
--- -----------------------------------------------------------------------
-
-entity cpu65xx is
-	generic (
-		pipelineOpcode : boolean;
-		pipelineAluMux : boolean;
-		pipelineAluOut : boolean
-	);
-	port (
-		clk : in std_logic;
-		enable : in std_logic;
-		reset : in std_logic;
-		nmi_n : in std_logic;
-		irq_n : in std_logic;
-		so_n : in std_logic := '1';
-
-		di : in unsigned(7 downto 0);
-		do : out unsigned(7 downto 0);
-		addr : out unsigned(15 downto 0);
-		we : out std_logic;
-		
-		debugOpcode : out unsigned(7 downto 0);
-		debugPc : out unsigned(15 downto 0);
-		debugA : out unsigned(7 downto 0);
-		debugX : out unsigned(7 downto 0);
-		debugY : out unsigned(7 downto 0);
-		debugS : out unsigned(7 downto 0)
-	);
-end cpu65xx;

cores/c16/mos8501.v

@@ -59,26 +59,25 @@ reg [7:0] port_data=8'b0;
 reg rw_reg,aec_reg;
 
 // 6502 CPU core
+wire we_n;
+assign we = ~we_n;
 
-	cpu65xx #(.pipelineOpcode("\false"),.pipelineAluMux("\false"),.pipelineAluOut("\false")) 
-		cpu_core(
-		.clk(clk), 
-		.reset(reset), 
-		.enable(enable_cpu), 
-		.nmi_n(1'b1), 
-		.irq_n(irq_n), 
-		.di(core_data_in), 
-		.do(core_data_out), 
-		.addr(core_address), 
-		.we(we),
-		.so_n(1'b1),
-		.debugOpcode(),
-		.debugPc(),
-		.debugA(),
-		.debugX(),
-		.debugY(),
-		.debugS()
-	);
+T65 cpu_core(
+	
+	.Mode (2'b00),
+	.Res_n (~reset),
+	.Enable(enable_cpu),
+	.Clk(clk),
+	.Rdy(enable_cpu),
+	.Abort_n(1),
+	.IRQ_n(irq_n),
+	.NMI_n(1),
+	.SO_n(1),
+	.R_w_n(we_n),
+	.A(core_address),
+	.DI(core_data_in),
+	.DO(core_data_out)
+);
 
 assign address=(aec)?core_address:16'hffff;		// address tri state emulated for easy bus signal combining
 

cores/c16/osd.v

@@ -109,26 +109,25 @@ end
 
 // horizontal counter
 reg [9:0] h_cnt;
-reg hsD, hsD2;
 reg [9:0] hs_low, hs_high;
 wire hs_pol = hs_high < hs_low;
 wire [9:0] h_dsp_width = hs_pol?hs_low:hs_high;
 wire [9:0] h_dsp_ctr = { 1'b0, h_dsp_width[9:1] };
 
 always @(posedge clk_sys) begin
+	reg hsD;
+
 	if (ce_pix) begin
-		// bring hsync into local clock domain
 		hsD <= hs_in;
-		hsD2 <= hsD;
 
 		// falling edge of hs_in
-		if(!hsD && hsD2) begin
+		if(!hs_in && hsD) begin
 			h_cnt <= 10'd0;
 			hs_high <= h_cnt;
 		end
 
 		// rising edge of hs_in
-		else if(hsD && !hsD2) begin
+		else if(hs_in && !hsD) begin
 			h_cnt <= 10'd0;
 			hs_low <= h_cnt;
 		end
@@ -140,30 +139,27 @@ end
 
 // vertical counter
 reg [9:0] v_cnt;
-reg vsD, vsD2;
 reg [9:0] vs_low, vs_high;
 wire vs_pol = vs_high < vs_low;
 wire [9:0] v_dsp_width = vs_pol?vs_low:vs_high;
 wire [9:0] v_dsp_ctr = { 1'b0, v_dsp_width[9:1] };
 
 always @(posedge clk_sys) begin
-	reg hsD;
+	reg hsD, vsD;
 	
 	hsD <= hs_in;
 	
 	if (~hsD & hs_in) begin
-		// bring vsync into local clock domain
 		vsD <= vs_in;
-		vsD2 <= vsD;
 
 		// falling edge of vs_in
-		if(!vsD && vsD2) begin
+		if(!vs_in && vsD) begin
 			v_cnt <= 10'd0;
 			vs_high <= v_cnt;
 		end
 
 		// rising edge of vs_in
-		else if(vsD && !vsD2) begin
+		else if(vs_in && !vsD) begin
 			v_cnt <= 10'd0;
 			vs_low <= v_cnt;
 		end