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https://github.com/mist-devel/mist-board.git
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[C64] Generate stable TOD clock from 32MHz clock
As originally it comes from the AC frequency
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@@ -125,6 +125,7 @@ entity fpga64_sid_iec is
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-- CIA
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cia_mode : in std_logic;
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todclk : in std_logic;
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disk_num : out std_logic_vector(7 downto 0);
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@@ -693,7 +694,7 @@ div1m: process(clk32) -- this process devides 32 MHz to 1MHz (for the SID)
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cnt_out => cnt1_out,
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pc_n => open,
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tod => vicVSync,
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tod => todclk,
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irq_n => irq_cia1
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);
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@@ -723,7 +724,7 @@ div1m: process(clk32) -- this process devides 32 MHz to 1MHz (for the SID)
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cnt_out => cnt2_out,
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pc_n => pc2_n,
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tod => vicVSync,
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tod => todclk,
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irq_n => irq_cia2
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);
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@@ -456,6 +456,9 @@ end component cartridge;
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signal hq2x160 : std_logic;
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signal osdclk : std_logic;
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signal clkdiv : std_logic_vector(9 downto 0);
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signal todclk : std_logic;
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signal toddiv : std_logic_vector(19 downto 0);
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signal toddiv3 : std_logic_vector(1 downto 0);
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signal ram_ce : std_logic;
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signal ram_we : std_logic;
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@@ -978,6 +981,7 @@ begin
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pb_in => pb_in,
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pb_out => pb_out,
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flag2_n => flag2_n,
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todclk => todclk,
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cia_mode => status(4),
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disk_num => open,
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c64rom_addr => c64rom_addr,
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@@ -1010,6 +1014,25 @@ begin
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end if;
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end process;
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-- generate TOD clock from stable 32 MHz
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process(clk32, reset_n)
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begin
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if reset_n = '0' then
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todclk <= '0';
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toddiv <= (others => '0');
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elsif rising_edge(clk32) then
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toddiv <= toddiv + 1;
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if (ntsc_init_mode_d2 = '1' and toddiv = 266665 and toddiv3 = "00") or
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(ntsc_init_mode_d2 = '1' and toddiv = 266666 and toddiv3 /= "00") or
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toddiv = 319999 then
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toddiv <= (others => '0');
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todclk <= not todclk;
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toddiv3 <= toddiv3 + 1;
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if toddiv3 = "10" then toddiv3 <= "00"; end if;
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end if;
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end if;
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end process;
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disk_readonly <= status(16);
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c64_iec_data_i <= c1541_iec_data_o;
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