mirror of
https://github.com/mist-devel/mist-board.git
synced 2026-02-05 23:54:41 +00:00
[C16] Reconfigurable PLL for PAL/NTSC modes
This commit is contained in:
Gyorgy Szombathelyi
@@ -127,7 +127,7 @@ set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
|
||||
# Analysis & Synthesis Assignments
|
||||
# ================================
|
||||
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
|
||||
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED
|
||||
set_global_assignment -name FAMILY "Cyclone III"
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY c16_mist
|
||||
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
|
||||
@@ -144,7 +144,7 @@ set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
|
||||
set_global_assignment -name DEVICE EP3C25E144C8
|
||||
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
|
||||
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
|
||||
@@ -324,8 +324,6 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to CONF_DATA0
|
||||
set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001
|
||||
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
|
||||
set_global_assignment -name VHDL_FILE gen_ram.vhd
|
||||
set_global_assignment -name QIP_FILE pll_ntsc.qip
|
||||
set_global_assignment -name QIP_FILE pll_pal.qip
|
||||
set_global_assignment -name VERILOG_FILE data_io.v
|
||||
set_global_assignment -name VERILOG_FILE sdram.v
|
||||
set_global_assignment -name VERILOG_FILE osd.v
|
||||
@@ -353,4 +351,10 @@ set_global_assignment -name VHDL_FILE t65/T65_ALU.vhd
|
||||
set_global_assignment -name VHDL_FILE t65/T65.vhd
|
||||
set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rgb2ypbpr.sv
|
||||
set_global_assignment -name QIP_FILE pll_c1541.qip
|
||||
set_global_assignment -name QIP_FILE pll_c16.qip
|
||||
set_global_assignment -name QIP_FILE rom_reconfig_pal.qip
|
||||
set_global_assignment -name QIP_FILE rom_reconfig_ntsc.qip
|
||||
set_global_assignment -name QIP_FILE pll_reconfig.qip
|
||||
set_global_assignment -name ENABLE_DRC_SETTINGS ON
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
@@ -33,21 +33,22 @@ derive_pll_clocks -create_base_clocks
|
||||
derive_clock_uncertainty
|
||||
|
||||
# Clock groups
|
||||
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[*]}]
|
||||
set_clock_groups -asynchronous -group [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[1]}] -group [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[0]}]
|
||||
set_clock_groups -asynchronous -group [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[1]}] -group [get_clocks {pll_ntsc|altpll_component|auto_generated|pll1|clk[0]}]
|
||||
|
||||
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll_c1541|altpll_component|auto_generated|pll1|clk[*]}]
|
||||
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[*]}]
|
||||
set_clock_groups -asynchronous -group [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[*]}] -group [get_clocks {pll_c1541|altpll_component|auto_generated|pll1|clk[*]}]
|
||||
|
||||
# Some relaxed constrain to the VGA pins. The signals should arrive together, the delay is not really important.
|
||||
set_output_delay -clock [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[0]}] -max 0 [get_ports {VGA_*}]
|
||||
set_output_delay -clock [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[0]}] -min -5 [get_ports {VGA_*}]
|
||||
set_output_delay -clock [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[0]}] -max 0 [get_ports {VGA_*}]
|
||||
set_output_delay -clock [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[0]}] -min -5 [get_ports {VGA_*}]
|
||||
|
||||
# SDRAM delays
|
||||
set_input_delay -clock [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[0]}] -max 6.4 [get_ports SDRAM_DQ[*]]
|
||||
set_input_delay -clock [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[0]}] -min 3.2 [get_ports SDRAM_DQ[*]]
|
||||
set_input_delay -clock [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[0]}] -max 6.4 [get_ports SDRAM_DQ[*]]
|
||||
set_input_delay -clock [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[0]}] -min 3.2 [get_ports SDRAM_DQ[*]]
|
||||
|
||||
set_output_delay -clock [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[0]}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
|
||||
set_output_delay -clock [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[0]}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
|
||||
set_output_delay -clock [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[0]}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
|
||||
set_output_delay -clock [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[0]}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
|
||||
set_output_delay -clock [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[0]}] -max 1.5 [get_ports {SDRAM_CLK}]
|
||||
set_output_delay -clock [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[0]}] -min -0.8 [get_ports {SDRAM_CLK}]
|
||||
|
||||
set_false_path -to [get_ports {AUDIO_L}]
|
||||
set_false_path -to [get_ports {AUDIO_R}]
|
||||
|
||||
@@ -57,7 +57,6 @@ module c16_mist (
|
||||
output [5:0] VGA_B
|
||||
);
|
||||
|
||||
parameter MODE_PAL = 1'b1;
|
||||
// -------------------------------------------------------------------------
|
||||
// ------------------------------ user_io ----------------------------------
|
||||
// -------------------------------------------------------------------------
|
||||
@@ -519,7 +518,7 @@ always @(negedge clk28) begin
|
||||
end
|
||||
|
||||
// include the c16 itself
|
||||
C16 #(.MODE_PAL(MODE_PAL)) c16 (
|
||||
C16 c16 (
|
||||
.CLK28 ( clk28 ),
|
||||
.RESET ( reset ),
|
||||
.WAIT ( c16_wait ),
|
||||
@@ -571,8 +570,8 @@ C16 #(.MODE_PAL(MODE_PAL)) c16 (
|
||||
|
||||
// the FPGATED uses two different clocks for NTSC and PAL mode.
|
||||
// Switching the clocks may crash the system. We might need to force a reset it.
|
||||
wire clk28 = MODE_PAL?clk28_pal:clk28_ntsc;
|
||||
wire pll_locked = pll_pal_locked && pll_ntsc_locked;
|
||||
wire pll_locked = pll_c1541_locked && pll_c16_locked;
|
||||
wire ntsc = ~c16_pal;
|
||||
|
||||
// tv15hkz has quarter the pixel rate, so we need a 7mhz clock for the OSD
|
||||
reg clk7;
|
||||
@@ -588,22 +587,127 @@ always @(posedge clk28) begin
|
||||
end
|
||||
|
||||
// A PLL to derive the system clock from the MiSTs 27MHz
|
||||
wire clk32;
|
||||
wire pll_pal_locked, clk28_pal;
|
||||
pll_pal pll_pal (
|
||||
.inclk0( CLOCK_27 ),
|
||||
.c0( clk28_pal ),
|
||||
.c1( clk32 ),
|
||||
.locked( pll_pal_locked )
|
||||
wire pll_c1541_locked, clk32;
|
||||
pll_c1541 pll_c1541 (
|
||||
.inclk0 ( CLOCK_27 ),
|
||||
.c0 ( clk32 ),
|
||||
.locked ( pll_c1541_locked )
|
||||
);
|
||||
|
||||
wire pll_ntsc_locked, clk28_ntsc;
|
||||
pll_ntsc pll_ntsc (
|
||||
.inclk0( CLOCK_27 ),
|
||||
.c0( clk28_ntsc ),
|
||||
.locked( pll_ntsc_locked )
|
||||
wire pll_c16_locked, clk28;
|
||||
pll_c16 pll_c16 (
|
||||
.inclk0(CLOCK_27),
|
||||
.c0(clk28),
|
||||
.areset(pll_areset),
|
||||
.scanclk(pll_scanclk),
|
||||
.scandata(pll_scandata),
|
||||
.scanclkena(pll_scanclkena),
|
||||
.configupdate(pll_configupdate),
|
||||
.scandataout(pll_scandataout),
|
||||
.scandone(pll_scandone),
|
||||
.locked(pll_c16_locked)
|
||||
);
|
||||
|
||||
wire pll_reconfig_busy;
|
||||
wire pll_areset;
|
||||
wire pll_configupdate;
|
||||
wire pll_scanclk;
|
||||
wire pll_scanclkena;
|
||||
wire pll_scandata;
|
||||
wire pll_scandataout;
|
||||
wire pll_scandone;
|
||||
reg pll_reconfig_reset;
|
||||
wire [7:0] pll_rom_address;
|
||||
wire pll_rom_q;
|
||||
reg pll_write_from_rom;
|
||||
wire pll_write_rom_ena;
|
||||
reg pll_reconfig;
|
||||
wire q_reconfig_ntsc;
|
||||
wire q_reconfig_pal;
|
||||
|
||||
rom_reconfig_pal rom_reconfig_pal
|
||||
(
|
||||
.address(pll_rom_address),
|
||||
.clock(clk32),
|
||||
.rden(pll_write_rom_ena),
|
||||
.q(q_reconfig_pal)
|
||||
);
|
||||
|
||||
rom_reconfig_ntsc rom_reconfig_ntsc
|
||||
(
|
||||
.address(pll_rom_address),
|
||||
.clock(clk32),
|
||||
.rden(pll_write_rom_ena),
|
||||
.q(q_reconfig_ntsc)
|
||||
);
|
||||
|
||||
assign pll_rom_q = ntsc ? q_reconfig_ntsc : q_reconfig_pal;
|
||||
|
||||
pll_reconfig pll_reconfig_inst
|
||||
(
|
||||
.busy(pll_reconfig_busy),
|
||||
.clock(clk32),
|
||||
.counter_param(0),
|
||||
.counter_type(0),
|
||||
.data_in(0),
|
||||
.pll_areset(pll_areset),
|
||||
.pll_areset_in(0),
|
||||
.pll_configupdate(pll_configupdate),
|
||||
.pll_scanclk(pll_scanclk),
|
||||
.pll_scanclkena(pll_scanclkena),
|
||||
.pll_scandata(pll_scandata),
|
||||
.pll_scandataout(pll_scandataout),
|
||||
.pll_scandone(pll_scandone),
|
||||
.read_param(0),
|
||||
.reconfig(pll_reconfig),
|
||||
.reset(pll_reconfig_reset),
|
||||
.reset_rom_address(0),
|
||||
.rom_address_out(pll_rom_address),
|
||||
.rom_data_in(pll_rom_q),
|
||||
.write_from_rom(pll_write_from_rom),
|
||||
.write_param(0),
|
||||
.write_rom_ena(pll_write_rom_ena)
|
||||
);
|
||||
|
||||
always @(posedge clk32) begin
|
||||
reg ntsc_d, ntsc_d2, ntsc_d3;
|
||||
reg [1:0] pll_reconfig_state = 0;
|
||||
reg [9:0] pll_reconfig_timeout;
|
||||
|
||||
ntsc_d <= ntsc;
|
||||
ntsc_d2 <= ntsc_d;
|
||||
pll_write_from_rom <= 0;
|
||||
pll_reconfig <= 0;
|
||||
pll_reconfig_reset <= 0;
|
||||
case (pll_reconfig_state)
|
||||
2'b00:
|
||||
begin
|
||||
ntsc_d3 <= ntsc_d2;
|
||||
if (ntsc_d2 ^ ntsc_d3) begin
|
||||
pll_write_from_rom <= 1;
|
||||
pll_reconfig_state <= 2'b01;
|
||||
end
|
||||
end
|
||||
2'b01: pll_reconfig_state <= 2'b10;
|
||||
2'b10:
|
||||
if (~pll_reconfig_busy) begin
|
||||
pll_reconfig <= 1;
|
||||
pll_reconfig_state <= 2'b11;
|
||||
pll_reconfig_timeout <= 10'd1000;
|
||||
end
|
||||
2'b11:
|
||||
begin
|
||||
pll_reconfig_timeout <= pll_reconfig_timeout - 1'd1;
|
||||
if (pll_reconfig_timeout == 10'd1) begin
|
||||
// pll_reconfig stuck in busy state
|
||||
pll_reconfig_reset <= 1;
|
||||
pll_reconfig_state <= 2'b00;
|
||||
end
|
||||
if (~pll_reconfig & ~pll_reconfig_busy) pll_reconfig_state <= 2'b00;
|
||||
end
|
||||
default: ;
|
||||
endcase
|
||||
end
|
||||
// ---------------------------------------------------------------------------------
|
||||
// ----------------------------------- floppy 1541 ---------------------------------
|
||||
// ---------------------------------------------------------------------------------
|
||||
|
||||
10
cores/c16/pll_c1541.ppf
Normal file
10
cores/c16/pll_c1541.ppf
Normal file
@@ -0,0 +1,10 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone III" variation_name="pll_c1541" megafunction_name="ALTPLL" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="inclk0" direction="input" scope="external" source="clock" />
|
||||
<pin name="c0" direction="output" scope="external" source="clock" />
|
||||
<pin name="locked" direction="output" scope="external" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
@@ -1,4 +1,4 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_ntsc.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_ntsc.ppf"]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_c1541.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_c1541.ppf"]
|
||||
@@ -4,7 +4,7 @@
|
||||
// MODULE: altpll
|
||||
|
||||
// ============================================================
|
||||
// File Name: pll_ntsc.v
|
||||
// File Name: pll_c1541.v
|
||||
// Megafunction Name(s):
|
||||
// altpll
|
||||
//
|
||||
@@ -36,7 +36,7 @@
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module pll_ntsc (
|
||||
module pll_c1541 (
|
||||
inclk0,
|
||||
c0,
|
||||
locked);
|
||||
@@ -94,14 +94,14 @@ module pll_ntsc (
|
||||
.vcounderrange ());
|
||||
defparam
|
||||
altpll_component.bandwidth_type = "AUTO",
|
||||
altpll_component.clk0_divide_by = 270000,
|
||||
altpll_component.clk0_divide_by = 27,
|
||||
altpll_component.clk0_duty_cycle = 50,
|
||||
altpll_component.clk0_multiply_by = 286363,
|
||||
altpll_component.clk0_multiply_by = 32,
|
||||
altpll_component.clk0_phase_shift = "0",
|
||||
altpll_component.compensate_clock = "CLK0",
|
||||
altpll_component.inclk0_input_frequency = 37037,
|
||||
altpll_component.intended_device_family = "Cyclone III",
|
||||
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_ntsc",
|
||||
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_c1541",
|
||||
altpll_component.lpm_type = "altpll",
|
||||
altpll_component.operation_mode = "NORMAL",
|
||||
altpll_component.pll_type = "AUTO",
|
||||
@@ -171,9 +171,9 @@ endmodule
|
||||
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "183"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "28.636299"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "32.000000"
|
||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
@@ -196,9 +196,9 @@ endmodule
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "191"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.63630000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "32.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
@@ -216,7 +216,7 @@ endmodule
|
||||
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_ntsc.mif"
|
||||
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_c1541.mif"
|
||||
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
@@ -224,7 +224,7 @@ endmodule
|
||||
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.000"
|
||||
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
@@ -237,9 +237,9 @@ endmodule
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "270000"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "286363"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "32"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
||||
@@ -298,12 +298,12 @@ endmodule
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.ppf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc_bb.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c1541.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c1541.ppf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c1541.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c1541.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c1541.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c1541_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c1541_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
// Retrieval info: CBX_MODULE_PREFIX: ON
|
||||
17
cores/c16/pll_c16.ppf
Normal file
17
cores/c16/pll_c16.ppf
Normal file
@@ -0,0 +1,17 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone III" variation_name="pll_c16" megafunction_name="ALTPLL" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="areset" direction="input" scope="external" />
|
||||
<pin name="configupdate" direction="input" scope="external" />
|
||||
<pin name="inclk0" direction="input" scope="external" source="clock" />
|
||||
<pin name="scanclk" direction="input" scope="external" source="clock" />
|
||||
<pin name="scanclkena" direction="input" scope="external" />
|
||||
<pin name="scandata" direction="input" scope="external" />
|
||||
<pin name="c0" direction="output" scope="external" source="clock" />
|
||||
<pin name="locked" direction="output" scope="external" />
|
||||
<pin name="scandataout" direction="output" scope="external" />
|
||||
<pin name="scandone" direction="output" scope="external" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
@@ -1,4 +1,4 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_pal.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_pal.ppf"]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_c16.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_c16.ppf"]
|
||||
@@ -4,7 +4,7 @@
|
||||
// MODULE: altpll
|
||||
|
||||
// ============================================================
|
||||
// File Name: pll_pal.v
|
||||
// File Name: pll_c16.v
|
||||
// Megafunction Name(s):
|
||||
// altpll
|
||||
//
|
||||
@@ -36,39 +36,68 @@
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module pll_pal (
|
||||
module pll_c16 (
|
||||
areset,
|
||||
configupdate,
|
||||
inclk0,
|
||||
scanclk,
|
||||
scanclkena,
|
||||
scandata,
|
||||
c0,
|
||||
c1,
|
||||
locked);
|
||||
locked,
|
||||
scandataout,
|
||||
scandone);
|
||||
|
||||
input areset;
|
||||
input configupdate;
|
||||
input inclk0;
|
||||
input scanclk;
|
||||
input scanclkena;
|
||||
input scandata;
|
||||
output c0;
|
||||
output c1;
|
||||
output locked;
|
||||
output scandataout;
|
||||
output scandone;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_off
|
||||
`endif
|
||||
tri0 areset;
|
||||
tri0 configupdate;
|
||||
tri0 scanclkena;
|
||||
tri0 scandata;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_on
|
||||
`endif
|
||||
|
||||
wire [4:0] sub_wire0;
|
||||
wire sub_wire2;
|
||||
wire [0:0] sub_wire6 = 1'h0;
|
||||
wire [0:0] sub_wire3 = sub_wire0[0:0];
|
||||
wire [1:1] sub_wire1 = sub_wire0[1:1];
|
||||
wire c1 = sub_wire1;
|
||||
wire locked = sub_wire2;
|
||||
wire c0 = sub_wire3;
|
||||
wire sub_wire4 = inclk0;
|
||||
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
|
||||
wire sub_wire3;
|
||||
wire sub_wire4;
|
||||
wire [0:0] sub_wire7 = 1'h0;
|
||||
wire [0:0] sub_wire1 = sub_wire0[0:0];
|
||||
wire c0 = sub_wire1;
|
||||
wire scandataout = sub_wire2;
|
||||
wire scandone = sub_wire3;
|
||||
wire locked = sub_wire4;
|
||||
wire sub_wire5 = inclk0;
|
||||
wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
|
||||
|
||||
altpll altpll_component (
|
||||
.inclk (sub_wire5),
|
||||
.areset (areset),
|
||||
.configupdate (configupdate),
|
||||
.inclk (sub_wire6),
|
||||
.scanclk (scanclk),
|
||||
.scanclkena (scanclkena),
|
||||
.scandata (scandata),
|
||||
.clk (sub_wire0),
|
||||
.locked (sub_wire2),
|
||||
.scandataout (sub_wire2),
|
||||
.scandone (sub_wire3),
|
||||
.locked (sub_wire4),
|
||||
.activeclock (),
|
||||
.areset (1'b0),
|
||||
.clkbad (),
|
||||
.clkena ({6{1'b1}}),
|
||||
.clkloss (),
|
||||
.clkswitch (1'b0),
|
||||
.configupdate (1'b0),
|
||||
.enable0 (),
|
||||
.enable1 (),
|
||||
.extclk (),
|
||||
@@ -85,11 +114,6 @@ module pll_pal (
|
||||
.phaseupdown (1'b1),
|
||||
.pllena (1'b1),
|
||||
.scanaclr (1'b0),
|
||||
.scanclk (1'b0),
|
||||
.scanclkena (1'b1),
|
||||
.scandata (1'b0),
|
||||
.scandataout (),
|
||||
.scandone (),
|
||||
.scanread (1'b0),
|
||||
.scanwrite (1'b0),
|
||||
.sclkout0 (),
|
||||
@@ -98,28 +122,24 @@ module pll_pal (
|
||||
.vcounderrange ());
|
||||
defparam
|
||||
altpll_component.bandwidth_type = "AUTO",
|
||||
altpll_component.clk0_divide_by = 39,
|
||||
altpll_component.clk0_divide_by = 27000000,
|
||||
altpll_component.clk0_duty_cycle = 50,
|
||||
altpll_component.clk0_multiply_by = 41,
|
||||
altpll_component.clk0_multiply_by = 28375151,
|
||||
altpll_component.clk0_phase_shift = "0",
|
||||
altpll_component.clk1_divide_by = 27,
|
||||
altpll_component.clk1_duty_cycle = 50,
|
||||
altpll_component.clk1_multiply_by = 32,
|
||||
altpll_component.clk1_phase_shift = "0",
|
||||
altpll_component.compensate_clock = "CLK0",
|
||||
altpll_component.inclk0_input_frequency = 37037,
|
||||
altpll_component.intended_device_family = "Cyclone III",
|
||||
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_pal",
|
||||
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_c16",
|
||||
altpll_component.lpm_type = "altpll",
|
||||
altpll_component.operation_mode = "NORMAL",
|
||||
altpll_component.pll_type = "AUTO",
|
||||
altpll_component.port_activeclock = "PORT_UNUSED",
|
||||
altpll_component.port_areset = "PORT_UNUSED",
|
||||
altpll_component.port_areset = "PORT_USED",
|
||||
altpll_component.port_clkbad0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkbad1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkloss = "PORT_UNUSED",
|
||||
altpll_component.port_clkswitch = "PORT_UNUSED",
|
||||
altpll_component.port_configupdate = "PORT_UNUSED",
|
||||
altpll_component.port_configupdate = "PORT_USED",
|
||||
altpll_component.port_fbin = "PORT_UNUSED",
|
||||
altpll_component.port_inclk0 = "PORT_USED",
|
||||
altpll_component.port_inclk1 = "PORT_UNUSED",
|
||||
@@ -131,15 +151,15 @@ module pll_pal (
|
||||
altpll_component.port_phaseupdown = "PORT_UNUSED",
|
||||
altpll_component.port_pllena = "PORT_UNUSED",
|
||||
altpll_component.port_scanaclr = "PORT_UNUSED",
|
||||
altpll_component.port_scanclk = "PORT_UNUSED",
|
||||
altpll_component.port_scanclkena = "PORT_UNUSED",
|
||||
altpll_component.port_scandata = "PORT_UNUSED",
|
||||
altpll_component.port_scandataout = "PORT_UNUSED",
|
||||
altpll_component.port_scandone = "PORT_UNUSED",
|
||||
altpll_component.port_scanclk = "PORT_USED",
|
||||
altpll_component.port_scanclkena = "PORT_USED",
|
||||
altpll_component.port_scandata = "PORT_USED",
|
||||
altpll_component.port_scandataout = "PORT_USED",
|
||||
altpll_component.port_scandone = "PORT_USED",
|
||||
altpll_component.port_scanread = "PORT_UNUSED",
|
||||
altpll_component.port_scanwrite = "PORT_UNUSED",
|
||||
altpll_component.port_clk0 = "PORT_USED",
|
||||
altpll_component.port_clk1 = "PORT_USED",
|
||||
altpll_component.port_clk1 = "PORT_UNUSED",
|
||||
altpll_component.port_clk2 = "PORT_UNUSED",
|
||||
altpll_component.port_clk3 = "PORT_UNUSED",
|
||||
altpll_component.port_clk4 = "PORT_UNUSED",
|
||||
@@ -155,7 +175,8 @@ module pll_pal (
|
||||
altpll_component.port_extclk2 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk3 = "PORT_UNUSED",
|
||||
altpll_component.self_reset_on_loss_lock = "OFF",
|
||||
altpll_component.width_clock = 5;
|
||||
altpll_component.width_clock = 5,
|
||||
altpll_component.scan_chain_mif_file = "pll_c16_pal.mif";
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -179,12 +200,9 @@ endmodule
|
||||
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "39"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "28.384615"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "32.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "28.375153"
|
||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
@@ -205,28 +223,20 @@ endmodule
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
|
||||
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "41"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.37500000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "32.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.37515200"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
|
||||
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
|
||||
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
@@ -235,38 +245,31 @@ endmodule
|
||||
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_pal.mif"
|
||||
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_c16_pal.mif"
|
||||
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "1"
|
||||
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.000"
|
||||
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "39"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27000000"
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "41"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "28375151"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
|
||||
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "32"
|
||||
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
@@ -274,12 +277,12 @@ endmodule
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
@@ -291,15 +294,15 @@ endmodule
|
||||
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
@@ -316,22 +319,38 @@ endmodule
|
||||
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
|
||||
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
// Retrieval info: CONSTANT: scan_chain_mif_file STRING "pll_c16_pal.mif"
|
||||
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
// Retrieval info: USED_PORT: configupdate 0 0 0 0 INPUT GND "configupdate"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||
// Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk"
|
||||
// Retrieval info: USED_PORT: scanclkena 0 0 0 0 INPUT GND "scanclkena"
|
||||
// Retrieval info: USED_PORT: scandata 0 0 0 0 INPUT GND "scandata"
|
||||
// Retrieval info: USED_PORT: scandataout 0 0 0 0 OUTPUT VCC "scandataout"
|
||||
// Retrieval info: USED_PORT: scandone 0 0 0 0 OUTPUT VCC "scandone"
|
||||
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
|
||||
// Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
|
||||
// Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0
|
||||
// Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal.ppf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal_bb.v FALSE
|
||||
// Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0
|
||||
// Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16.ppf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16_bb.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16.mif FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16_ntsc.mif TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16_pal.mif TRUE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
// Retrieval info: CBX_MODULE_PREFIX: ON
|
||||
174
cores/c16/pll_c16_ntsc.mif
Normal file
174
cores/c16/pll_c16_ntsc.mif
Normal file
@@ -0,0 +1,174 @@
|
||||
-- Copyright (C) 1991-2014 Altera Corporation
|
||||
-- Your use of Altera Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Altera Program License
|
||||
-- Subscription Agreement, Altera MegaCore Function License
|
||||
-- Agreement, or other applicable license agreement, including,
|
||||
-- without limitation, that your use is for the sole purpose of
|
||||
-- programming logic devices manufactured by Altera and sold by
|
||||
-- Altera or its authorized distributors. Please refer to the
|
||||
-- applicable agreement for further details.
|
||||
|
||||
-- MIF file representing initial state of PLL Scan Chain
|
||||
-- Device Family: Cyclone III
|
||||
-- Device Part: -
|
||||
-- Device Speed Grade: 8
|
||||
-- PLL Scan Chain: Fast PLL (144 bits)
|
||||
-- File Name: /home/gyurco/git/mist-board/cores/c16/pll_c16_ntsc.mif
|
||||
-- Generated: Thu Feb 14 11:24:12 2019
|
||||
|
||||
WIDTH=1;
|
||||
DEPTH=144;
|
||||
|
||||
ADDRESS_RADIX=UNS;
|
||||
DATA_RADIX=UNS;
|
||||
|
||||
CONTENT BEGIN
|
||||
0 : 0; -- Reserved Bits = 0 (1 bit(s))
|
||||
1 : 0; -- Reserved Bits = 0 (1 bit(s))
|
||||
2 : 0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0)
|
||||
3 : 0;
|
||||
4 : 1; -- Loop Filter Resistance = 16 (5 bit(s)) (Setting 16)
|
||||
5 : 0;
|
||||
6 : 0;
|
||||
7 : 0;
|
||||
8 : 0;
|
||||
9 : 0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2)
|
||||
10 : 0; -- Reserved Bits = 0 (5 bit(s))
|
||||
11 : 0;
|
||||
12 : 0;
|
||||
13 : 0;
|
||||
14 : 0;
|
||||
15 : 0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1)
|
||||
16 : 0;
|
||||
17 : 1;
|
||||
18 : 0; -- N counter: Bypass = 0 (1 bit(s))
|
||||
19 : 0; -- N counter: High Count = 2 (8 bit(s))
|
||||
20 : 0;
|
||||
21 : 0;
|
||||
22 : 0;
|
||||
23 : 0;
|
||||
24 : 0;
|
||||
25 : 1;
|
||||
26 : 0;
|
||||
27 : 1; -- N counter: Odd Division = 1 (1 bit(s))
|
||||
28 : 0; -- N counter: Low Count = 1 (8 bit(s))
|
||||
29 : 0;
|
||||
30 : 0;
|
||||
31 : 0;
|
||||
32 : 0;
|
||||
33 : 0;
|
||||
34 : 0;
|
||||
35 : 1;
|
||||
36 : 0; -- M counter: Bypass = 0 (1 bit(s))
|
||||
37 : 0; -- M counter: High Count = 35 (8 bit(s))
|
||||
38 : 0;
|
||||
39 : 1;
|
||||
40 : 0;
|
||||
41 : 0;
|
||||
42 : 0;
|
||||
43 : 1;
|
||||
44 : 1;
|
||||
45 : 0; -- M counter: Odd Division = 0 (1 bit(s))
|
||||
46 : 0; -- M counter: Low Count = 35 (8 bit(s))
|
||||
47 : 0;
|
||||
48 : 1;
|
||||
49 : 0;
|
||||
50 : 0;
|
||||
51 : 0;
|
||||
52 : 1;
|
||||
53 : 1;
|
||||
54 : 0; -- clk0 counter: Bypass = 0 (1 bit(s))
|
||||
55 : 0; -- clk0 counter: High Count = 11 (8 bit(s))
|
||||
56 : 0;
|
||||
57 : 0;
|
||||
58 : 0;
|
||||
59 : 1;
|
||||
60 : 0;
|
||||
61 : 1;
|
||||
62 : 1;
|
||||
63 : 0; -- clk0 counter: Odd Division = 0 (1 bit(s))
|
||||
64 : 0; -- clk0 counter: Low Count = 11 (8 bit(s))
|
||||
65 : 0;
|
||||
66 : 0;
|
||||
67 : 0;
|
||||
68 : 1;
|
||||
69 : 0;
|
||||
70 : 1;
|
||||
71 : 1;
|
||||
72 : 1; -- clk1 counter: Bypass = 1 (1 bit(s))
|
||||
73 : 0; -- clk1 counter: High Count = 0 (8 bit(s))
|
||||
74 : 0;
|
||||
75 : 0;
|
||||
76 : 0;
|
||||
77 : 0;
|
||||
78 : 0;
|
||||
79 : 0;
|
||||
80 : 0;
|
||||
81 : 0; -- clk1 counter: Odd Division = 0 (1 bit(s))
|
||||
82 : 0; -- clk1 counter: Low Count = 0 (8 bit(s))
|
||||
83 : 0;
|
||||
84 : 0;
|
||||
85 : 0;
|
||||
86 : 0;
|
||||
87 : 0;
|
||||
88 : 0;
|
||||
89 : 0;
|
||||
90 : 1; -- clk2 counter: Bypass = 1 (1 bit(s))
|
||||
91 : 0; -- clk2 counter: High Count = 0 (8 bit(s))
|
||||
92 : 0;
|
||||
93 : 0;
|
||||
94 : 0;
|
||||
95 : 0;
|
||||
96 : 0;
|
||||
97 : 0;
|
||||
98 : 0;
|
||||
99 : 0; -- clk2 counter: Odd Division = 0 (1 bit(s))
|
||||
100 : 0; -- clk2 counter: Low Count = 0 (8 bit(s))
|
||||
101 : 0;
|
||||
102 : 0;
|
||||
103 : 0;
|
||||
104 : 0;
|
||||
105 : 0;
|
||||
106 : 0;
|
||||
107 : 0;
|
||||
108 : 1; -- clk3 counter: Bypass = 1 (1 bit(s))
|
||||
109 : 0; -- clk3 counter: High Count = 0 (8 bit(s))
|
||||
110 : 0;
|
||||
111 : 0;
|
||||
112 : 0;
|
||||
113 : 0;
|
||||
114 : 0;
|
||||
115 : 0;
|
||||
116 : 0;
|
||||
117 : 0; -- clk3 counter: Odd Division = 0 (1 bit(s))
|
||||
118 : 0; -- clk3 counter: Low Count = 0 (8 bit(s))
|
||||
119 : 0;
|
||||
120 : 0;
|
||||
121 : 0;
|
||||
122 : 0;
|
||||
123 : 0;
|
||||
124 : 0;
|
||||
125 : 0;
|
||||
126 : 1; -- clk4 counter: Bypass = 1 (1 bit(s))
|
||||
127 : 0; -- clk4 counter: High Count = 0 (8 bit(s))
|
||||
128 : 0;
|
||||
129 : 0;
|
||||
130 : 0;
|
||||
131 : 0;
|
||||
132 : 0;
|
||||
133 : 0;
|
||||
134 : 0;
|
||||
135 : 0; -- clk4 counter: Odd Division = 0 (1 bit(s))
|
||||
136 : 0; -- clk4 counter: Low Count = 0 (8 bit(s))
|
||||
137 : 0;
|
||||
138 : 0;
|
||||
139 : 0;
|
||||
140 : 0;
|
||||
141 : 0;
|
||||
142 : 0;
|
||||
143 : 0;
|
||||
END;
|
||||
174
cores/c16/pll_c16_pal.mif
Normal file
174
cores/c16/pll_c16_pal.mif
Normal file
@@ -0,0 +1,174 @@
|
||||
-- Copyright (C) 1991-2014 Altera Corporation
|
||||
-- Your use of Altera Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Altera Program License
|
||||
-- Subscription Agreement, Altera MegaCore Function License
|
||||
-- Agreement, or other applicable license agreement, including,
|
||||
-- without limitation, that your use is for the sole purpose of
|
||||
-- programming logic devices manufactured by Altera and sold by
|
||||
-- Altera or its authorized distributors. Please refer to the
|
||||
-- applicable agreement for further details.
|
||||
|
||||
-- MIF file representing initial state of PLL Scan Chain
|
||||
-- Device Family: Cyclone III
|
||||
-- Device Part: -
|
||||
-- Device Speed Grade: 8
|
||||
-- PLL Scan Chain: Fast PLL (144 bits)
|
||||
-- File Name: /home/gyurco/git/mist-board/cores/c16/pll_c16_pal.mif
|
||||
-- Generated: Thu Feb 14 11:25:48 2019
|
||||
|
||||
WIDTH=1;
|
||||
DEPTH=144;
|
||||
|
||||
ADDRESS_RADIX=UNS;
|
||||
DATA_RADIX=UNS;
|
||||
|
||||
CONTENT BEGIN
|
||||
0 : 0; -- Reserved Bits = 0 (1 bit(s))
|
||||
1 : 0; -- Reserved Bits = 0 (1 bit(s))
|
||||
2 : 0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0)
|
||||
3 : 0;
|
||||
4 : 1; -- Loop Filter Resistance = 20 (5 bit(s)) (Setting 20)
|
||||
5 : 0;
|
||||
6 : 1;
|
||||
7 : 0;
|
||||
8 : 0;
|
||||
9 : 0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2)
|
||||
10 : 0; -- Reserved Bits = 0 (5 bit(s))
|
||||
11 : 0;
|
||||
12 : 0;
|
||||
13 : 0;
|
||||
14 : 0;
|
||||
15 : 0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1)
|
||||
16 : 0;
|
||||
17 : 1;
|
||||
18 : 0; -- N counter: Bypass = 0 (1 bit(s))
|
||||
19 : 0; -- N counter: High Count = 2 (8 bit(s))
|
||||
20 : 0;
|
||||
21 : 0;
|
||||
22 : 0;
|
||||
23 : 0;
|
||||
24 : 0;
|
||||
25 : 1;
|
||||
26 : 0;
|
||||
27 : 1; -- N counter: Odd Division = 1 (1 bit(s))
|
||||
28 : 0; -- N counter: Low Count = 1 (8 bit(s))
|
||||
29 : 0;
|
||||
30 : 0;
|
||||
31 : 0;
|
||||
32 : 0;
|
||||
33 : 0;
|
||||
34 : 0;
|
||||
35 : 1;
|
||||
36 : 0; -- M counter: Bypass = 0 (1 bit(s))
|
||||
37 : 0; -- M counter: High Count = 21 (8 bit(s))
|
||||
38 : 0;
|
||||
39 : 0;
|
||||
40 : 1;
|
||||
41 : 0;
|
||||
42 : 1;
|
||||
43 : 0;
|
||||
44 : 1;
|
||||
45 : 1; -- M counter: Odd Division = 1 (1 bit(s))
|
||||
46 : 0; -- M counter: Low Count = 20 (8 bit(s))
|
||||
47 : 0;
|
||||
48 : 0;
|
||||
49 : 1;
|
||||
50 : 0;
|
||||
51 : 1;
|
||||
52 : 0;
|
||||
53 : 0;
|
||||
54 : 0; -- clk0 counter: Bypass = 0 (1 bit(s))
|
||||
55 : 0; -- clk0 counter: High Count = 7 (8 bit(s))
|
||||
56 : 0;
|
||||
57 : 0;
|
||||
58 : 0;
|
||||
59 : 0;
|
||||
60 : 1;
|
||||
61 : 1;
|
||||
62 : 1;
|
||||
63 : 1; -- clk0 counter: Odd Division = 1 (1 bit(s))
|
||||
64 : 0; -- clk0 counter: Low Count = 6 (8 bit(s))
|
||||
65 : 0;
|
||||
66 : 0;
|
||||
67 : 0;
|
||||
68 : 0;
|
||||
69 : 1;
|
||||
70 : 1;
|
||||
71 : 0;
|
||||
72 : 1; -- clk1 counter: Bypass = 1 (1 bit(s))
|
||||
73 : 0; -- clk1 counter: High Count = 0 (8 bit(s))
|
||||
74 : 0;
|
||||
75 : 0;
|
||||
76 : 0;
|
||||
77 : 0;
|
||||
78 : 0;
|
||||
79 : 0;
|
||||
80 : 0;
|
||||
81 : 0; -- clk1 counter: Odd Division = 0 (1 bit(s))
|
||||
82 : 0; -- clk1 counter: Low Count = 0 (8 bit(s))
|
||||
83 : 0;
|
||||
84 : 0;
|
||||
85 : 0;
|
||||
86 : 0;
|
||||
87 : 0;
|
||||
88 : 0;
|
||||
89 : 0;
|
||||
90 : 1; -- clk2 counter: Bypass = 1 (1 bit(s))
|
||||
91 : 0; -- clk2 counter: High Count = 0 (8 bit(s))
|
||||
92 : 0;
|
||||
93 : 0;
|
||||
94 : 0;
|
||||
95 : 0;
|
||||
96 : 0;
|
||||
97 : 0;
|
||||
98 : 0;
|
||||
99 : 0; -- clk2 counter: Odd Division = 0 (1 bit(s))
|
||||
100 : 0; -- clk2 counter: Low Count = 0 (8 bit(s))
|
||||
101 : 0;
|
||||
102 : 0;
|
||||
103 : 0;
|
||||
104 : 0;
|
||||
105 : 0;
|
||||
106 : 0;
|
||||
107 : 0;
|
||||
108 : 1; -- clk3 counter: Bypass = 1 (1 bit(s))
|
||||
109 : 0; -- clk3 counter: High Count = 0 (8 bit(s))
|
||||
110 : 0;
|
||||
111 : 0;
|
||||
112 : 0;
|
||||
113 : 0;
|
||||
114 : 0;
|
||||
115 : 0;
|
||||
116 : 0;
|
||||
117 : 0; -- clk3 counter: Odd Division = 0 (1 bit(s))
|
||||
118 : 0; -- clk3 counter: Low Count = 0 (8 bit(s))
|
||||
119 : 0;
|
||||
120 : 0;
|
||||
121 : 0;
|
||||
122 : 0;
|
||||
123 : 0;
|
||||
124 : 0;
|
||||
125 : 0;
|
||||
126 : 1; -- clk4 counter: Bypass = 1 (1 bit(s))
|
||||
127 : 0; -- clk4 counter: High Count = 0 (8 bit(s))
|
||||
128 : 0;
|
||||
129 : 0;
|
||||
130 : 0;
|
||||
131 : 0;
|
||||
132 : 0;
|
||||
133 : 0;
|
||||
134 : 0;
|
||||
135 : 0; -- clk4 counter: Odd Division = 0 (1 bit(s))
|
||||
136 : 0; -- clk4 counter: Low Count = 0 (8 bit(s))
|
||||
137 : 0;
|
||||
138 : 0;
|
||||
139 : 0;
|
||||
140 : 0;
|
||||
141 : 0;
|
||||
142 : 0;
|
||||
143 : 0;
|
||||
END;
|
||||
3
cores/c16/pll_reconfig.qip
Normal file
3
cores/c16/pll_reconfig.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL_RECONFIG"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_reconfig.v"]
|
||||
1624
cores/c16/pll_reconfig.v
Normal file
1624
cores/c16/pll_reconfig.v
Normal file
File diff suppressed because it is too large
Load Diff
3
cores/c16/rom_reconfig_ntsc.qip
Normal file
3
cores/c16/rom_reconfig_ntsc.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "rom_reconfig_ntsc.v"]
|
||||
164
cores/c16/rom_reconfig_ntsc.v
Normal file
164
cores/c16/rom_reconfig_ntsc.v
Normal file
@@ -0,0 +1,164 @@
|
||||
// megafunction wizard: %ROM: 1-PORT%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altsyncram
|
||||
|
||||
// ============================================================
|
||||
// File Name: rom_reconfig_ntsc.v
|
||||
// Megafunction Name(s):
|
||||
// altsyncram
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2014 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module rom_reconfig_ntsc (
|
||||
address,
|
||||
clock,
|
||||
rden,
|
||||
q);
|
||||
|
||||
input [7:0] address;
|
||||
input clock;
|
||||
input rden;
|
||||
output [0:0] q;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_off
|
||||
`endif
|
||||
tri1 clock;
|
||||
tri1 rden;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_on
|
||||
`endif
|
||||
|
||||
wire [0:0] sub_wire0;
|
||||
wire [0:0] q = sub_wire0[0:0];
|
||||
|
||||
altsyncram altsyncram_component (
|
||||
.address_a (address),
|
||||
.clock0 (clock),
|
||||
.rden_a (rden),
|
||||
.q_a (sub_wire0),
|
||||
.aclr0 (1'b0),
|
||||
.aclr1 (1'b0),
|
||||
.address_b (1'b1),
|
||||
.addressstall_a (1'b0),
|
||||
.addressstall_b (1'b0),
|
||||
.byteena_a (1'b1),
|
||||
.byteena_b (1'b1),
|
||||
.clock1 (1'b1),
|
||||
.clocken0 (1'b1),
|
||||
.clocken1 (1'b1),
|
||||
.clocken2 (1'b1),
|
||||
.clocken3 (1'b1),
|
||||
.data_a (1'b1),
|
||||
.data_b (1'b1),
|
||||
.eccstatus (),
|
||||
.q_b (),
|
||||
.rden_b (1'b1),
|
||||
.wren_a (1'b0),
|
||||
.wren_b (1'b0));
|
||||
defparam
|
||||
altsyncram_component.address_aclr_a = "NONE",
|
||||
altsyncram_component.clock_enable_input_a = "BYPASS",
|
||||
altsyncram_component.clock_enable_output_a = "BYPASS",
|
||||
altsyncram_component.init_file = "pll_c16_ntsc.mif",
|
||||
altsyncram_component.intended_device_family = "Cyclone III",
|
||||
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
|
||||
altsyncram_component.lpm_type = "altsyncram",
|
||||
altsyncram_component.numwords_a = 256,
|
||||
altsyncram_component.operation_mode = "ROM",
|
||||
altsyncram_component.outdata_aclr_a = "NONE",
|
||||
altsyncram_component.outdata_reg_a = "CLOCK0",
|
||||
altsyncram_component.widthad_a = 8,
|
||||
altsyncram_component.width_a = 1,
|
||||
altsyncram_component.width_byteena_a = 1;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
|
||||
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Clken NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
|
||||
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
||||
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: MIFfilename STRING "pll_c16_ntsc.mif"
|
||||
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
|
||||
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
|
||||
// Retrieval info: PRIVATE: WidthData NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: rden NUMERIC "1"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: INIT_FILE STRING "pll_c16_ntsc.mif"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
||||
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
|
||||
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
|
||||
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
|
||||
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
|
||||
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
|
||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
|
||||
// Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL "q[0..0]"
|
||||
// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
|
||||
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
|
||||
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
|
||||
// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
|
||||
// Retrieval info: CONNECT: q 0 0 1 0 @q_a 0 0 1 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_ntsc.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_ntsc.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_ntsc.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_ntsc.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_ntsc_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_ntsc_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
3
cores/c16/rom_reconfig_pal.qip
Normal file
3
cores/c16/rom_reconfig_pal.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "rom_reconfig_pal.v"]
|
||||
164
cores/c16/rom_reconfig_pal.v
Normal file
164
cores/c16/rom_reconfig_pal.v
Normal file
@@ -0,0 +1,164 @@
|
||||
// megafunction wizard: %ROM: 1-PORT%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altsyncram
|
||||
|
||||
// ============================================================
|
||||
// File Name: rom_reconfig_pal.v
|
||||
// Megafunction Name(s):
|
||||
// altsyncram
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2014 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module rom_reconfig_pal (
|
||||
address,
|
||||
clock,
|
||||
rden,
|
||||
q);
|
||||
|
||||
input [7:0] address;
|
||||
input clock;
|
||||
input rden;
|
||||
output [0:0] q;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_off
|
||||
`endif
|
||||
tri1 clock;
|
||||
tri1 rden;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_on
|
||||
`endif
|
||||
|
||||
wire [0:0] sub_wire0;
|
||||
wire [0:0] q = sub_wire0[0:0];
|
||||
|
||||
altsyncram altsyncram_component (
|
||||
.address_a (address),
|
||||
.clock0 (clock),
|
||||
.rden_a (rden),
|
||||
.q_a (sub_wire0),
|
||||
.aclr0 (1'b0),
|
||||
.aclr1 (1'b0),
|
||||
.address_b (1'b1),
|
||||
.addressstall_a (1'b0),
|
||||
.addressstall_b (1'b0),
|
||||
.byteena_a (1'b1),
|
||||
.byteena_b (1'b1),
|
||||
.clock1 (1'b1),
|
||||
.clocken0 (1'b1),
|
||||
.clocken1 (1'b1),
|
||||
.clocken2 (1'b1),
|
||||
.clocken3 (1'b1),
|
||||
.data_a (1'b1),
|
||||
.data_b (1'b1),
|
||||
.eccstatus (),
|
||||
.q_b (),
|
||||
.rden_b (1'b1),
|
||||
.wren_a (1'b0),
|
||||
.wren_b (1'b0));
|
||||
defparam
|
||||
altsyncram_component.address_aclr_a = "NONE",
|
||||
altsyncram_component.clock_enable_input_a = "BYPASS",
|
||||
altsyncram_component.clock_enable_output_a = "BYPASS",
|
||||
altsyncram_component.init_file = "pll_c16_pal.mif",
|
||||
altsyncram_component.intended_device_family = "Cyclone III",
|
||||
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
|
||||
altsyncram_component.lpm_type = "altsyncram",
|
||||
altsyncram_component.numwords_a = 256,
|
||||
altsyncram_component.operation_mode = "ROM",
|
||||
altsyncram_component.outdata_aclr_a = "NONE",
|
||||
altsyncram_component.outdata_reg_a = "CLOCK0",
|
||||
altsyncram_component.widthad_a = 8,
|
||||
altsyncram_component.width_a = 1,
|
||||
altsyncram_component.width_byteena_a = 1;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
|
||||
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Clken NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
|
||||
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
||||
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: MIFfilename STRING "pll_c16_pal.mif"
|
||||
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
|
||||
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
|
||||
// Retrieval info: PRIVATE: WidthData NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: rden NUMERIC "1"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: INIT_FILE STRING "pll_c16_pal.mif"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
||||
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
|
||||
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
|
||||
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
|
||||
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
|
||||
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
|
||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
|
||||
// Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL "q[0..0]"
|
||||
// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
|
||||
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
|
||||
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
|
||||
// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
|
||||
// Retrieval info: CONNECT: q 0 0 1 0 @q_a 0 0 1 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_pal.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_pal.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_pal.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_pal.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_pal_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_pal_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
Reference in New Issue
Block a user