C64: port switchable SID6580/8580 from MiSTer

cores/c64/C64_mist.qsf

@@ -336,10 +336,6 @@ set_global_assignment -name VERILOG_FILE rtl/cartridge.v
 set_global_assignment -name VHDL_FILE rtl/rom_c64_chargen.vhd
 set_global_assignment -name VHDL_FILE rtl/rom_C64.vhd
 set_global_assignment -name VHDL_FILE rtl/rom_GS64.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/sid8580.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/sid_voice.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/sid_filters.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/sid_envelope.sv
 set_global_assignment -name VERILOG_FILE rtl/sigma_delta_dac.v
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
 set_global_assignment -name VERILOG_FILE rtl/sdram.v
@@ -352,6 +348,22 @@ set_global_assignment -name VHDL_FILE rtl/io_ps2_keyboard.vhd
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
 set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
 set_global_assignment -name VHDL_FILE rtl/composite_sync.vhd
+set_global_assignment -name VHDL_FILE rtl/sid/wave_map.vhd
+set_global_assignment -name VHDL_FILE rtl/sid/sid_top.vhd
+set_global_assignment -name VHDL_FILE rtl/sid/sid_regs.vhd
+set_global_assignment -name VHDL_FILE rtl/sid/sid_mixer.vhd
+set_global_assignment -name VHDL_FILE rtl/sid/sid_filter.vhd
+set_global_assignment -name VHDL_FILE rtl/sid/sid_debug_pkg.vhd
+set_global_assignment -name VHDL_FILE rtl/sid/sid_ctrl.vhd
+set_global_assignment -name VHDL_FILE rtl/sid/Q_table.vhd
+set_global_assignment -name VHDL_FILE rtl/sid/oscillator.vhd
+set_global_assignment -name VHDL_FILE rtl/sid/my_math_pkg.vhd
+set_global_assignment -name VHDL_FILE rtl/sid/mult_acc.vhd
+set_global_assignment -name VHDL_FILE rtl/sid/adsr_multi.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/sid8580/sid_voice.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/sid8580/sid_filters.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/sid8580/sid_envelope.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/sid8580/sid8580.sv
 set_global_assignment -name VHDL_FILE rtl/c1541/via6522.vhd
 set_global_assignment -name VHDL_FILE rtl/c1541/spram.vhd
 set_global_assignment -name VHDL_FILE rtl/c1541/spi_controller.vhd

cores/c64/rtl/c64_mist.vhd

@@ -130,6 +130,7 @@ constant CONF_STR : string :=
 --	"F,T64,Load File;"&--5
 	"O2,Video standard,PAL,NTSC;"&
 	"O8A,Scandoubler Fx,None,HQ2x-320,HQ2x-160,CRT 25%,CRT 50%;"&
+	"OD,SID,6581,8580;"&
 	"O3,Joysticks,normal,swapped;"&
 	"O6,Audio filter,On,Off;"&
 --	"OB,BIOS,C64,C64GS;" &
@@ -481,7 +482,7 @@ end component cartridge;
 	signal hsync_out : std_logic;
 	signal vsync_out : std_logic;
 	
-	signal audio_data : std_logic_vector(15 downto 0);
+	signal audio_data : std_logic_vector(17 downto 0);
 	
 	signal reset_counter    : integer;
 	signal reset_n          : std_logic;
@@ -817,8 +818,8 @@ begin
    dac : sigma_delta_dac
     port map (
       clk => clk32,
-      ldatasum => audio_data(15 downto 1),
-		rdatasum => audio_data(15 downto 1),
+      ldatasum => audio_data(17 downto 3),
+		rdatasum => audio_data(17 downto 3),
 		aleft => AUDIO_L,
 		aright => AUDIO_R
  	);
@@ -868,6 +869,7 @@ begin
 		idle => idle,
 		audio_data => audio_data,
 		extfilter_en => not status(6),
+		sid_ver => status(13),
 		iec_data_o => c64_iec_data_o,
 		iec_atn_o  => c64_iec_atn_o,
 		iec_clk_o  => c64_iec_clk_o,

cores/c64/rtl/fpga64_sid_iec.vhd

@@ -93,8 +93,9 @@ entity fpga64_sid_iec is
 		--Connector to the SID
 		SIDclk      : buffer std_logic;
 		still       : out unsigned(15 downto 0);
-		audio_data  : out std_logic_vector(15 downto 0);
+		audio_data  : out std_logic_vector(17 downto 0);
 		extfilter_en: in  std_logic;
+		sid_ver     : in  std_logic;
 
 		-- IEC
 		iec_data_o	: out std_logic;
@@ -179,6 +180,8 @@ architecture rtl of fpga64_sid_iec is
 	
 	-- SID signals
 	signal sid_do : std_logic_vector(7 downto 0);
+	signal sid_do6581 : std_logic_vector(7 downto 0);
+	signal sid_do8580 : std_logic_vector(7 downto 0);
 
 	-- CIA signals
 	signal enableCia : std_logic;
@@ -255,6 +258,7 @@ architecture rtl of fpga64_sid_iec is
 	signal voice_volume : signed(17 downto 0);
 	signal pot_x        : std_logic_vector(7 downto 0);
 	signal pot_y        : std_logic_vector(7 downto 0);
+	signal audio_8580 : std_logic_vector(15 downto 0);
 
 	component sid8580
 		port (
@@ -561,7 +565,36 @@ div1m: process(clk32)				-- this process devides 32 MHz to 1MHz (for the SID)
 		end if;
 	end process;
 
-sid_8580 : sid8580
+	audio_data <= std_logic_vector(voice_volume) when sid_ver='0' else (audio_8580 & "00");
+	sid_do     <= sid_do6581                     when sid_ver='0' else sid_do8580;
+
+	pot_x <= X"FF" when ((cia1_pao(7) and JoyA(5)) or (cia1_pao(6) and JoyB(5))) = '0' else X"00";
+	pot_y <= X"FF" when ((cia1_pao(7) and JoyA(6)) or (cia1_pao(6) and JoyB(6))) = '0' else X"00";
+
+	sid_6581: entity work.sid_top
+	port map (
+		clock => clk32,
+		reset => reset,
+
+		addr => "000" & cpuAddr(4 downto 0),
+		wren => pulseWrRam and phi0_cpu and cs_sid,
+		wdata => std_logic_vector(cpuDo),
+		rdata => sid_do6581,
+
+		potx => pot_x(0),
+		poty => pot_y(0),
+
+		comb_wave_l => '0',
+		comb_wave_r => '0',
+
+		extfilter_en => extfilter_en,
+
+		start_iter => clk_1MHz(31),
+		sample_left => voice_volume,
+		sample_right => open
+	);
+
+	sid_8580 : sid8580
 	port map (
 		reset => reset,
 		clk => clk32,
@@ -569,15 +602,13 @@ sid_8580 : sid8580
 		we => pulseWrRam and phi0_cpu and cs_sid,
 		addr => std_logic_vector(cpuAddr(4 downto 0)),
 		data_in => std_logic_vector(cpuDo),
-		data_out => sid_do,
+		data_out => sid_do8580,
 		pot_x => pot_x,
 		pot_y => pot_y,
-		audio_data => audio_data,
+		audio_data => audio_8580,
 		extfilter_en => extfilter_en
-	);
+); 
 	
-	pot_x <= X"FF" when ((cia1_pao(7) and JoyA(5)) or (cia1_pao(6) and JoyB(5))) = '0' else X"00";
-	pot_y <= X"FF" when ((cia1_pao(7) and JoyA(6)) or (cia1_pao(6) and JoyB(6))) = '0' else X"00";
 -- -----------------------------------------------------------------------
 -- CIAs
 -- -----------------------------------------------------------------------