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BBC: add YPbPr
This commit is contained in:
Gyorgy Szombathelyi
@@ -159,7 +159,14 @@ set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
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set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
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set_global_assignment -name VERILOG_FILE bbc_mist_top.v
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set_global_assignment -name SYSTEMVERILOG_FILE rgb2ypbpr.sv
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set_global_assignment -name VERILOG_FILE sdram.v
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set_global_assignment -name VERILOG_FILE sd_card.v
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set_global_assignment -name VERILOG_FILE user_io.v
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@@ -199,10 +206,4 @@ set_global_assignment -name QIP_FILE os12.qip
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set_global_assignment -name QIP_FILE basic2.qip
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set_global_assignment -name QIP_FILE dfs09.qip
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set_global_assignment -name SDC_FILE bbc_mist.sdc
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set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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@@ -109,7 +109,8 @@ always @(posedge clk_24m)
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clk_12m <= !clk_12m;
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wire ce_pix = scandoubler_disable?clk_12m:1'd1;
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wire [5:0] osd_r_o, osd_g_o, osd_b_o;
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osd #(0,0,4) OSD (
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.clk_sys ( clk_24m ),
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.ce_pix ( ce_pix ),
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@@ -123,22 +124,37 @@ osd #(0,0,4) OSD (
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.green_in ( scandoubler_disable? {5{video_g[0]}} : {3{video_g}} ),
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.blue_in ( scandoubler_disable? {5{video_b[0]}} : {3{video_b}} ),
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.hs_in ( video_hs ),
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.vs_in ( video_vs ),
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.hs_in ( video_hs ),
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.vs_in ( video_vs ),
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.red_out ( VGA_R ),
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.green_out ( VGA_G ),
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.blue_out ( VGA_B ),
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.red_out ( osd_r_o ),
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.green_out ( osd_g_o ),
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.blue_out ( osd_b_o ),
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.hs_out ( v_hs ),
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.vs_out ( v_vs )
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);
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wire [5:0] Y, Pb, Pr;
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rgb2ypbpr rgb2ypbpr
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(
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.red ( osd_r_o ),
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.green ( osd_g_o ),
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.blue ( osd_b_o ),
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.y ( Y ),
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.pb ( Pb ),
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.pr ( Pr )
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);
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wire v_hs, v_vs;
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// create composite sync for 15khz
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wire csync = !(v_vs ^ v_hs);
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assign VGA_HS = scandoubler_disable?csync:v_hs;
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assign VGA_VS = scandoubler_disable?1'b1:v_vs;
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assign VGA_HS = (scandoubler_disable || ypbpr) ?csync:v_hs;
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assign VGA_VS = (scandoubler_disable || ypbpr) ?1'b1:v_vs;
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assign VGA_R = ypbpr?Pr:osd_r_o;
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assign VGA_G = ypbpr? Y:osd_g_o;
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assign VGA_B = ypbpr?Pb:osd_b_o;
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// conections between user_io (implementing the SPIU communication
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// to the io controller) and the legacy
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@@ -163,6 +179,7 @@ wire [15:0] joystick_analog_0;
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wire [15:0] joystick_analog_1;
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wire scandoubler_disable;
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wire ypbpr;
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user_io #(.STRLEN(CONF_STR_LEN)) user_io(
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.conf_str ( CONF_STR ),
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@@ -185,6 +202,7 @@ user_io #(.STRLEN(CONF_STR_LEN)) user_io(
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.switches ( switches ),
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.buttons ( buttons ),
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.scandoubler_disable ( scandoubler_disable ),
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.ypbpr ( ypbpr ),
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// interface to embedded legacy sd card wrapper
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.sd_lba ( sd_lba ),
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55
cores/bbc/fpga/mist/rgb2ypbpr.sv
Normal file
55
cores/bbc/fpga/mist/rgb2ypbpr.sv
Normal file
@@ -0,0 +1,55 @@
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module rgb2ypbpr (
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input [5:0] red,
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input [5:0] green,
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input [5:0] blue,
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output [5:0] y,
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output [5:0] pb,
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output [5:0] pr
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);
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wire [5:0] yuv_full[225] = '{
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6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1,
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6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4,
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6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6,
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6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8,
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6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
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6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
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6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
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6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
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6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
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6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
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6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
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6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
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6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
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6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
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6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
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6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
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6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
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6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
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6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
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6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
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6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
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6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
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6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
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6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
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6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
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6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
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6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
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6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
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6'd63
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};
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wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
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wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
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wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
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wire [7:0] y_i = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8];
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wire [7:0] pb_i = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
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wire [7:0] pr_i = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
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assign pr = yuv_full[pr_i - 8'd16];
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assign y = yuv_full[y_i - 8'd16];
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assign pb = yuv_full[pb_i - 8'd16];
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endmodule
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