mirror of
https://github.com/mist-devel/mist-board.git
synced 2026-02-05 23:54:41 +00:00
[Archie] Restore VIDC enhancer
- 24, 25, 36 MHz pixel clock via reconfigurable PLL - 24 MHz mode gets composite sync
This commit is contained in:
Gyorgy Szombathelyi
@@ -136,7 +136,7 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_*
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_*
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set_global_assignment -name ENABLE_SIGNALTAP OFF
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set_global_assignment -name USE_SIGNALTAP_FILE signal_tap.stp
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set_global_assignment -name USE_SIGNALTAP_FILE output_files/vidc.stp
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
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set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
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set_global_assignment -name ENABLE_NCE_PIN OFF
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@@ -161,7 +161,7 @@ set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
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set_location_assignment PIN_7 -to LED
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set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
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set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
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set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
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set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
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@@ -172,6 +172,10 @@ set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
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set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
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set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
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set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
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set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[*]
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set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[*]
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set_global_assignment -name SEED 2
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set_global_assignment -name ENABLE_DRC_SETTINGS OFF
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set_global_assignment -name VERILOG_FILE archimedes_mist_top.v
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set_global_assignment -name SYSTEMVERILOG_FILE rgb2ypbpr.sv
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set_global_assignment -name VERILOG_FILE sigma_delta_dac.v
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@@ -218,6 +222,11 @@ set_global_assignment -name VERILOG_FILE ../../rtl/amber/a23_alu.v
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set_global_assignment -name VERILOG_FILE ../../rtl/archimedes_top.v
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set_global_assignment -name VERILOG_FILE ../../rtl/sdram/sdram_top.v
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set_global_assignment -name VERILOG_FILE ../../rtl/sdram/sdram_init.v
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set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[*]
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set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[*]
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set_global_assignment -name QIP_FILE rom_reconfig_24.qip
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set_global_assignment -name QIP_FILE rom_reconfig_25.qip
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set_global_assignment -name QIP_FILE pll_reconfig.qip
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set_location_assignment PLL_1 -to CLOCKS|altpll_component|auto_generated|pll1
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set_global_assignment -name QIP_FILE rom_reconfig_36.qip
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set_global_assignment -name QIP_FILE pll_vidc.qip
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set_global_assignment -name SIGNALTAP_FILE output_files/vidc.stp
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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@@ -75,16 +75,16 @@ set_output_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1
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set_output_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[3]}] -max 1.5 [get_ports DRAM_CLK]
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set_output_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[3]}] -min -0.8 [get_ports DRAM_CLK]
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set_output_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[2]}] -max 0 [get_ports {VGA_*}]
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set_output_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[2]}] -min -5 [get_ports {VGA_*}]
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set_output_delay -clock [get_clocks {CLOCKS_VIDC|altpll_component|auto_generated|pll1|clk[0]}] -max 0 [get_ports {VGA_*}]
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set_output_delay -clock [get_clocks {CLOCKS_VIDC|altpll_component|auto_generated|pll1|clk[0]}] -min -5 [get_ports {VGA_*}]
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#**************************************************************
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# Set Clock Groups
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#**************************************************************
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set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {CLOCKS|*}]
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set_clock_groups -asynchronous -group [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[0]}] -group [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[2]}]
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set_clock_groups -asynchronous -group [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[1]}] -group [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[2]}]
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set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {CLOCKS_VIDC|*}]
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set_clock_groups -asynchronous -group [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[0]}] -group [get_clocks {CLOCKS_VIDC|altpll_component|auto_generated|pll1|clk[0]}]
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#**************************************************************
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# Set False Path
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@@ -103,8 +103,8 @@ set_false_path -to [get_ports {LED}]
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set_multicycle_path -from [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[1]}] -setup 4
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set_multicycle_path -from [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[1]}] -hold 3
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set_multicycle_path -to {VGA_*[*]} -setup 2
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set_multicycle_path -to {VGA_*[*]} -hold 1
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set_multicycle_path -to {VGA_*[*]} -setup 4
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set_multicycle_path -to {VGA_*[*]} -hold 3
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#**************************************************************
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# Set Maximum Delay
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@@ -65,14 +65,14 @@ wire [7:0] kbd_in_data;
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wire kbd_in_strobe;
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// generated clocks
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wire clk_pix = clk_50m;
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wire clk_pix;
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wire ce_pix;
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wire clk_32m /* synthesis keep */ ;
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wire clk_128m /* synthesis keep */ ;
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wire clk_50m /* synthesis keep */ ;
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//wire clk_8m /* synthesis keep */ ;
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wire pll_ready;
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wire pll_vidc_ready;
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wire ram_ready;
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// core's raw video
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@@ -105,12 +105,134 @@ wire ypbpr;
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clockgen CLOCKS(
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.inclk0 (CLOCK_27[0]),
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.c0 (clk_32m),
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.c1 (clk_128m),
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.c2 (clk_50m),
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.c1 (clk_128m),
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// .c2 (clk_50m),
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.c3 (DRAM_CLK),
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.locked (pll_ready) // pll locked output
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);
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pll_vidc CLOCKS_VIDC(
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.inclk0 (CLOCK_27[0]),
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.c0 (clk_pix),
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.areset(pll_areset),
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.scanclk(pll_scanclk),
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.scandata(pll_scandata),
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.scanclkena(pll_scanclkena),
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.configupdate(pll_configupdate),
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.scandataout(pll_scandataout),
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.scandone(pll_scandone),
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.locked (pll_vidc_ready) // pll locked output
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);
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wire pll_reconfig_busy;
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wire pll_areset;
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wire pll_configupdate;
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wire pll_scanclk;
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wire pll_scanclkena;
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wire pll_scandata;
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wire pll_scandataout;
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wire pll_scandone;
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reg pll_reconfig_reset;
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wire [7:0] pll_rom_address;
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wire pll_rom_q;
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reg pll_write_from_rom;
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wire pll_write_rom_ena;
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reg pll_reconfig;
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wire q_reconfig_25;
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wire q_reconfig_24;
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wire q_reconfig_36;
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rom_reconfig_25 rom_reconfig_25
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(
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.address(pll_rom_address),
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.clock(CLOCK_27[0]),
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.rden(pll_write_rom_ena),
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.q(q_reconfig_25)
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);
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rom_reconfig_24 rom_reconfig_24
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(
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.address(pll_rom_address),
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.clock(CLOCK_27[0]),
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.rden(pll_write_rom_ena),
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.q(q_reconfig_24)
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);
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rom_reconfig_36 rom_reconfig_36
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(
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.address(pll_rom_address),
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.clock(CLOCK_27[0]),
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.rden(pll_write_rom_ena),
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.q(q_reconfig_36)
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);
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assign pll_rom_q = pixbaseclk_select == 2'b01 ? q_reconfig_25 :
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pixbaseclk_select == 2'b10 ? q_reconfig_36 : q_reconfig_24;
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pll_reconfig pll_reconfig_inst
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(
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.busy(pll_reconfig_busy),
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.clock(CLOCK_27[0]),
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.counter_param(0),
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.counter_type(0),
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.data_in(0),
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.pll_areset(pll_areset),
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.pll_areset_in(0),
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.pll_configupdate(pll_configupdate),
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.pll_scanclk(pll_scanclk),
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.pll_scanclkena(pll_scanclkena),
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.pll_scandata(pll_scandata),
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.pll_scandataout(pll_scandataout),
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.pll_scandone(pll_scandone),
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.read_param(0),
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.reconfig(pll_reconfig),
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.reset(pll_reconfig_reset),
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.reset_rom_address(0),
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.rom_address_out(pll_rom_address),
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.rom_data_in(pll_rom_q),
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.write_from_rom(pll_write_from_rom),
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.write_param(0),
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.write_rom_ena(pll_write_rom_ena)
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);
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always @(posedge CLOCK_27[0]) begin
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reg [1:0] pixbaseclk_select_d;
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reg [1:0] pll_reconfig_state = 0;
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reg [9:0] pll_reconfig_timeout;
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pll_write_from_rom <= 0;
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pll_reconfig <= 0;
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pll_reconfig_reset <= 0;
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case (pll_reconfig_state)
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2'b00:
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begin
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pixbaseclk_select_d <= pixbaseclk_select;
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if (pixbaseclk_select_d != pixbaseclk_select) begin
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pll_write_from_rom <= 1;
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pll_reconfig_state <= 2'b01;
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end
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end
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2'b01: pll_reconfig_state <= 2'b10;
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2'b10:
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if (~pll_reconfig_busy) begin
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pll_reconfig <= 1;
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pll_reconfig_state <= 2'b11;
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pll_reconfig_timeout <= 10'd1000;
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end
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2'b11:
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begin
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pll_reconfig_timeout <= pll_reconfig_timeout - 1'd1;
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if (pll_reconfig_timeout == 10'd1) begin
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// pll_reconfig stuck in busy state
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pll_reconfig_reset <= 1;
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pll_reconfig_state <= 2'b00;
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end
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if (~pll_reconfig & ~pll_reconfig_busy) pll_reconfig_state <= 2'b00;
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end
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default: ;
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endcase
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end
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wire [5:0] osd_r_o, osd_g_o, osd_b_o;
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osd #(0,0,4) OSD (
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@@ -148,8 +270,9 @@ assign VGA_R = ypbpr?Pr:osd_r_o;
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assign VGA_G = ypbpr? Y:osd_g_o;
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assign VGA_B = ypbpr?Pb:osd_b_o;
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wire CSync = ~(core_hs ^ core_vs);
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assign VGA_HS = (scandoubler_disable | ypbpr) ? CSync : core_hs;
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assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : core_vs;
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//24 MHz modes get composite sync automatically
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assign VGA_HS = ((pixbaseclk_select[0] == pixbaseclk_select[1]) | ypbpr) ? CSync : core_hs;
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assign VGA_VS = ((pixbaseclk_select[0] == pixbaseclk_select[1]) | ypbpr) ? 1'b1 : core_vs;
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// de-multiplex spi outputs from user_io and data_io
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assign SPI_DO = (CONF_DATA0==0)?user_io_sdo:(SPI_SS2==0)?data_io_sdo:1'bZ;
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@@ -2,10 +2,10 @@
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<!DOCTYPE pinplan>
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<pinplan intended_family="Cyclone III" variation_name="clockgen" megafunction_name="ALTPLL" specifies="all_ports">
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<global>
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<pin name="areset" direction="input" scope="external" />
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<pin name="inclk0" direction="input" scope="external" source="clock" />
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<pin name="c0" direction="output" scope="external" source="clock" />
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<pin name="c1" direction="output" scope="external" source="clock" />
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<pin name="c2" direction="output" scope="external" source="clock" />
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<pin name="c3" direction="output" scope="external" source="clock" />
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<pin name="locked" direction="output" scope="external" />
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@@ -1,5 +1,4 @@
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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
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set_global_assignment -name IP_TOOL_VERSION "13.1"
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "clockgen.v"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clockgen_bb.v"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clockgen.ppf"]
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@@ -37,24 +37,30 @@
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module clockgen (
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areset,
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inclk0,
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c0,
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c1,
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c2,
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c3,
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locked);
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input areset;
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input inclk0;
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output c0;
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output c1;
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output c2;
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output c3;
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output locked;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri0 areset;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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wire [4:0] sub_wire0;
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wire sub_wire3;
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wire [0:0] sub_wire8 = 1'h0;
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wire [2:2] sub_wire5 = sub_wire0[2:2];
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wire [0:0] sub_wire7 = 1'h0;
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wire [0:0] sub_wire4 = sub_wire0[0:0];
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wire [3:3] sub_wire2 = sub_wire0[3:3];
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wire [1:1] sub_wire1 = sub_wire0[1:1];
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@@ -62,16 +68,15 @@ module clockgen (
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wire c3 = sub_wire2;
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wire locked = sub_wire3;
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wire c0 = sub_wire4;
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wire c2 = sub_wire5;
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wire sub_wire6 = inclk0;
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wire [1:0] sub_wire7 = {sub_wire8, sub_wire6};
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wire sub_wire5 = inclk0;
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wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
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altpll altpll_component (
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.inclk (sub_wire7),
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.areset (areset),
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.inclk (sub_wire6),
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.clk (sub_wire0),
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.locked (sub_wire3),
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.activeclock (),
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.areset (1'b0),
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.clkbad (),
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.clkena ({6{1'b1}}),
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.clkloss (),
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@@ -105,7 +110,7 @@ module clockgen (
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.vcooverrange (),
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.vcounderrange ());
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defparam
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altpll_component.bandwidth_type = "LOW",
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altpll_component.bandwidth_type = "AUTO",
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altpll_component.clk0_divide_by = 27,
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altpll_component.clk0_duty_cycle = 50,
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altpll_component.clk0_multiply_by = 32,
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@@ -114,14 +119,10 @@ module clockgen (
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altpll_component.clk1_duty_cycle = 50,
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altpll_component.clk1_multiply_by = 128,
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altpll_component.clk1_phase_shift = "0",
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altpll_component.clk2_divide_by = 90,
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altpll_component.clk2_duty_cycle = 50,
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altpll_component.clk2_multiply_by = 167,
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altpll_component.clk2_phase_shift = "0",
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altpll_component.clk3_divide_by = 27,
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altpll_component.clk3_duty_cycle = 50,
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altpll_component.clk3_multiply_by = 128,
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altpll_component.clk3_phase_shift = "-3700",
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altpll_component.clk3_phase_shift = "-1845",
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altpll_component.compensate_clock = "CLK0",
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altpll_component.inclk0_input_frequency = 37037,
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altpll_component.intended_device_family = "Cyclone III",
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@@ -130,7 +131,7 @@ module clockgen (
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altpll_component.operation_mode = "NORMAL",
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altpll_component.pll_type = "AUTO",
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altpll_component.port_activeclock = "PORT_UNUSED",
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altpll_component.port_areset = "PORT_UNUSED",
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altpll_component.port_areset = "PORT_USED",
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altpll_component.port_clkbad0 = "PORT_UNUSED",
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altpll_component.port_clkbad1 = "PORT_UNUSED",
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altpll_component.port_clkloss = "PORT_UNUSED",
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||||
@@ -156,7 +157,7 @@ module clockgen (
|
||||
altpll_component.port_scanwrite = "PORT_UNUSED",
|
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altpll_component.port_clk0 = "PORT_USED",
|
||||
altpll_component.port_clk1 = "PORT_USED",
|
||||
altpll_component.port_clk2 = "PORT_USED",
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||||
altpll_component.port_clk2 = "PORT_UNUSED",
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||||
altpll_component.port_clk3 = "PORT_USED",
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||||
altpll_component.port_clk4 = "PORT_UNUSED",
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||||
altpll_component.port_clk5 = "PORT_UNUSED",
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||||
@@ -184,8 +185,8 @@ endmodule
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||||
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
@@ -197,15 +198,12 @@ endmodule
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "32.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "128.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "50.099998"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "128.000000"
|
||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
@@ -228,43 +226,35 @@ endmodule
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
|
||||
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "32.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "128.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "50.10000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "128.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "-3700.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "-1844.61000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
|
||||
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
|
||||
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
@@ -273,7 +263,6 @@ endmodule
|
||||
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clockgen.mif"
|
||||
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
|
||||
@@ -286,23 +275,20 @@ endmodule
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW"
|
||||
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "32"
|
||||
@@ -311,14 +297,10 @@ endmodule
|
||||
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "128"
|
||||
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "90"
|
||||
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "167"
|
||||
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "27"
|
||||
// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "128"
|
||||
// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "-3700"
|
||||
// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "-1845"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
@@ -326,7 +308,7 @@ endmodule
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
@@ -352,7 +334,7 @@ endmodule
|
||||
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
@@ -369,17 +351,17 @@ endmodule
|
||||
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
|
||||
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
|
||||
// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
|
||||
// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
|
||||
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL clockgen.v TRUE
|
||||
@@ -388,6 +370,7 @@ endmodule
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL clockgen.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL clockgen.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL clockgen_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL clockgen_bb.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL clockgen_bb.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL clockgen.mif FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
// Retrieval info: CBX_MODULE_PREFIX: ON
|
||||
|
||||
3
cores/archie/fpga/mist/pll_reconfig.qip
Normal file
3
cores/archie/fpga/mist/pll_reconfig.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL_RECONFIG"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_reconfig.v"]
|
||||
1621
cores/archie/fpga/mist/pll_reconfig.v
Normal file
1621
cores/archie/fpga/mist/pll_reconfig.v
Normal file
File diff suppressed because it is too large
Load Diff
17
cores/archie/fpga/mist/pll_vidc.ppf
Normal file
17
cores/archie/fpga/mist/pll_vidc.ppf
Normal file
@@ -0,0 +1,17 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone III" variation_name="pll_vidc" megafunction_name="ALTPLL" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="areset" direction="input" scope="external" />
|
||||
<pin name="configupdate" direction="input" scope="external" />
|
||||
<pin name="inclk0" direction="input" scope="external" source="clock" />
|
||||
<pin name="scanclk" direction="input" scope="external" source="clock" />
|
||||
<pin name="scanclkena" direction="input" scope="external" />
|
||||
<pin name="scandata" direction="input" scope="external" />
|
||||
<pin name="c0" direction="output" scope="external" source="clock" />
|
||||
<pin name="locked" direction="output" scope="external" />
|
||||
<pin name="scandataout" direction="output" scope="external" />
|
||||
<pin name="scandone" direction="output" scope="external" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
4
cores/archie/fpga/mist/pll_vidc.qip
Normal file
4
cores/archie/fpga/mist/pll_vidc.qip
Normal file
@@ -0,0 +1,4 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_vidc.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_vidc.ppf"]
|
||||
@@ -1,10 +1,10 @@
|
||||
// megafunction wizard: %ALTPLL%VBB%
|
||||
// megafunction wizard: %ALTPLL%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altpll
|
||||
|
||||
// ============================================================
|
||||
// File Name: clockgen.v
|
||||
// File Name: pll_vidc.v
|
||||
// Megafunction Name(s):
|
||||
// altpll
|
||||
//
|
||||
@@ -17,6 +17,7 @@
|
||||
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2014 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
@@ -31,20 +32,152 @@
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
module clockgen (
|
||||
inclk0,
|
||||
c0,
|
||||
c1,
|
||||
c2,
|
||||
c3,
|
||||
locked);
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module pll_vidc (
|
||||
areset,
|
||||
configupdate,
|
||||
inclk0,
|
||||
scanclk,
|
||||
scanclkena,
|
||||
scandata,
|
||||
c0,
|
||||
locked,
|
||||
scandataout,
|
||||
scandone);
|
||||
|
||||
input areset;
|
||||
input configupdate;
|
||||
input inclk0;
|
||||
input scanclk;
|
||||
input scanclkena;
|
||||
input scandata;
|
||||
output c0;
|
||||
output c1;
|
||||
output c2;
|
||||
output c3;
|
||||
output locked;
|
||||
output scandataout;
|
||||
output scandone;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_off
|
||||
`endif
|
||||
tri0 areset;
|
||||
tri0 configupdate;
|
||||
tri0 scanclkena;
|
||||
tri0 scandata;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_on
|
||||
`endif
|
||||
|
||||
wire [4:0] sub_wire0;
|
||||
wire sub_wire2;
|
||||
wire sub_wire3;
|
||||
wire sub_wire4;
|
||||
wire [0:0] sub_wire7 = 1'h0;
|
||||
wire [0:0] sub_wire1 = sub_wire0[0:0];
|
||||
wire c0 = sub_wire1;
|
||||
wire scandataout = sub_wire2;
|
||||
wire scandone = sub_wire3;
|
||||
wire locked = sub_wire4;
|
||||
wire sub_wire5 = inclk0;
|
||||
wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
|
||||
|
||||
altpll altpll_component (
|
||||
.areset (areset),
|
||||
.configupdate (configupdate),
|
||||
.inclk (sub_wire6),
|
||||
.scanclk (scanclk),
|
||||
.scanclkena (scanclkena),
|
||||
.scandata (scandata),
|
||||
.clk (sub_wire0),
|
||||
.scandataout (sub_wire2),
|
||||
.scandone (sub_wire3),
|
||||
.locked (sub_wire4),
|
||||
.activeclock (),
|
||||
.clkbad (),
|
||||
.clkena ({6{1'b1}}),
|
||||
.clkloss (),
|
||||
.clkswitch (1'b0),
|
||||
.enable0 (),
|
||||
.enable1 (),
|
||||
.extclk (),
|
||||
.extclkena ({4{1'b1}}),
|
||||
.fbin (1'b1),
|
||||
.fbmimicbidir (),
|
||||
.fbout (),
|
||||
.fref (),
|
||||
.icdrclk (),
|
||||
.pfdena (1'b1),
|
||||
.phasecounterselect ({4{1'b1}}),
|
||||
.phasedone (),
|
||||
.phasestep (1'b1),
|
||||
.phaseupdown (1'b1),
|
||||
.pllena (1'b1),
|
||||
.scanaclr (1'b0),
|
||||
.scanread (1'b0),
|
||||
.scanwrite (1'b0),
|
||||
.sclkout0 (),
|
||||
.sclkout1 (),
|
||||
.vcooverrange (),
|
||||
.vcounderrange ());
|
||||
defparam
|
||||
altpll_component.bandwidth_type = "LOW",
|
||||
altpll_component.clk0_divide_by = 3,
|
||||
altpll_component.clk0_duty_cycle = 50,
|
||||
altpll_component.clk0_multiply_by = 8,
|
||||
altpll_component.clk0_phase_shift = "0",
|
||||
altpll_component.compensate_clock = "CLK0",
|
||||
altpll_component.inclk0_input_frequency = 37037,
|
||||
altpll_component.intended_device_family = "Cyclone III",
|
||||
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_vidc",
|
||||
altpll_component.lpm_type = "altpll",
|
||||
altpll_component.operation_mode = "SOURCE_SYNCHRONOUS",
|
||||
altpll_component.pll_type = "AUTO",
|
||||
altpll_component.port_activeclock = "PORT_UNUSED",
|
||||
altpll_component.port_areset = "PORT_USED",
|
||||
altpll_component.port_clkbad0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkbad1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkloss = "PORT_UNUSED",
|
||||
altpll_component.port_clkswitch = "PORT_UNUSED",
|
||||
altpll_component.port_configupdate = "PORT_USED",
|
||||
altpll_component.port_fbin = "PORT_UNUSED",
|
||||
altpll_component.port_inclk0 = "PORT_USED",
|
||||
altpll_component.port_inclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_locked = "PORT_USED",
|
||||
altpll_component.port_pfdena = "PORT_UNUSED",
|
||||
altpll_component.port_phasecounterselect = "PORT_UNUSED",
|
||||
altpll_component.port_phasedone = "PORT_UNUSED",
|
||||
altpll_component.port_phasestep = "PORT_UNUSED",
|
||||
altpll_component.port_phaseupdown = "PORT_UNUSED",
|
||||
altpll_component.port_pllena = "PORT_UNUSED",
|
||||
altpll_component.port_scanaclr = "PORT_UNUSED",
|
||||
altpll_component.port_scanclk = "PORT_USED",
|
||||
altpll_component.port_scanclkena = "PORT_USED",
|
||||
altpll_component.port_scandata = "PORT_USED",
|
||||
altpll_component.port_scandataout = "PORT_USED",
|
||||
altpll_component.port_scandone = "PORT_USED",
|
||||
altpll_component.port_scanread = "PORT_UNUSED",
|
||||
altpll_component.port_scanwrite = "PORT_UNUSED",
|
||||
altpll_component.port_clk0 = "PORT_USED",
|
||||
altpll_component.port_clk1 = "PORT_UNUSED",
|
||||
altpll_component.port_clk2 = "PORT_UNUSED",
|
||||
altpll_component.port_clk3 = "PORT_UNUSED",
|
||||
altpll_component.port_clk4 = "PORT_UNUSED",
|
||||
altpll_component.port_clk5 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena2 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena3 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena4 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena5 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk0 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk2 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk3 = "PORT_UNUSED",
|
||||
altpll_component.self_reset_on_loss_lock = "ON",
|
||||
altpll_component.width_clock = 5,
|
||||
altpll_component.scan_chain_mif_file = "pll_vidc_36.mif";
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -66,19 +199,10 @@ endmodule
|
||||
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "32.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "128.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "50.099998"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "128.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "72.000000"
|
||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
@@ -99,44 +223,20 @@ endmodule
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
|
||||
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "32.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "128.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "50.10000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "128.00000000"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "72.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "-3700.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
|
||||
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
|
||||
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
@@ -145,8 +245,8 @@ endmodule
|
||||
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clockgen.mif"
|
||||
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_vidc_36.mif"
|
||||
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "1"
|
||||
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
|
||||
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
@@ -155,55 +255,34 @@ endmodule
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3"
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "32"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
|
||||
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "128"
|
||||
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "90"
|
||||
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "167"
|
||||
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "27"
|
||||
// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "128"
|
||||
// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "-3700"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
|
||||
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
@@ -215,17 +294,17 @@ endmodule
|
||||
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
@@ -240,26 +319,40 @@ endmodule
|
||||
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
|
||||
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
// Retrieval info: CONSTANT: scan_chain_mif_file STRING "pll_vidc_36.mif"
|
||||
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
|
||||
// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
|
||||
// Retrieval info: USED_PORT: configupdate 0 0 0 0 INPUT GND "configupdate"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||
// Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk"
|
||||
// Retrieval info: USED_PORT: scanclkena 0 0 0 0 INPUT GND "scanclkena"
|
||||
// Retrieval info: USED_PORT: scandata 0 0 0 0 INPUT GND "scandata"
|
||||
// Retrieval info: USED_PORT: scandataout 0 0 0 0 OUTPUT VCC "scandataout"
|
||||
// Retrieval info: USED_PORT: scandone 0 0 0 0 OUTPUT VCC "scandone"
|
||||
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
|
||||
// Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
|
||||
// Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0
|
||||
// Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
|
||||
// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
|
||||
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL clockgen.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL clockgen.ppf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL clockgen.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL clockgen.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL clockgen.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL clockgen_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL clockgen_bb.v TRUE
|
||||
// Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0
|
||||
// Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_vidc.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_vidc.ppf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_vidc.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_vidc.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_vidc.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_vidc_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_vidc_bb.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_vidc.mif FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL .mif FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_vidc_24.mif TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_vidc_25.mif TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_vidc_36.mif TRUE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
// Retrieval info: CBX_MODULE_PREFIX: ON
|
||||
174
cores/archie/fpga/mist/pll_vidc_24.mif
Normal file
174
cores/archie/fpga/mist/pll_vidc_24.mif
Normal file
@@ -0,0 +1,174 @@
|
||||
-- Copyright (C) 1991-2014 Altera Corporation
|
||||
-- Your use of Altera Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Altera Program License
|
||||
-- Subscription Agreement, Altera MegaCore Function License
|
||||
-- Agreement, or other applicable license agreement, including,
|
||||
-- without limitation, that your use is for the sole purpose of
|
||||
-- programming logic devices manufactured by Altera and sold by
|
||||
-- Altera or its authorized distributors. Please refer to the
|
||||
-- applicable agreement for further details.
|
||||
|
||||
-- MIF file representing initial state of PLL Scan Chain
|
||||
-- Device Family: Cyclone III
|
||||
-- Device Part: -
|
||||
-- Device Speed Grade: 8
|
||||
-- PLL Scan Chain: Fast PLL (144 bits)
|
||||
-- File Name: /home/gyuri/git/mist-board/cores/archie/fpga/mist/pll_vidc_24.mif
|
||||
-- Generated: Fri Feb 22 22:07:56 2019
|
||||
|
||||
WIDTH=1;
|
||||
DEPTH=144;
|
||||
|
||||
ADDRESS_RADIX=UNS;
|
||||
DATA_RADIX=UNS;
|
||||
|
||||
CONTENT BEGIN
|
||||
0 : 0; -- Reserved Bits = 0 (1 bit(s))
|
||||
1 : 0; -- Reserved Bits = 0 (1 bit(s))
|
||||
2 : 0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0)
|
||||
3 : 0;
|
||||
4 : 1; -- Loop Filter Resistance = 27 (5 bit(s)) (Setting 27)
|
||||
5 : 1;
|
||||
6 : 0;
|
||||
7 : 1;
|
||||
8 : 1;
|
||||
9 : 0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2)
|
||||
10 : 0; -- Reserved Bits = 0 (5 bit(s))
|
||||
11 : 0;
|
||||
12 : 0;
|
||||
13 : 0;
|
||||
14 : 0;
|
||||
15 : 0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1)
|
||||
16 : 0;
|
||||
17 : 1;
|
||||
18 : 1; -- N counter: Bypass = 1 (1 bit(s))
|
||||
19 : 0; -- N counter: High Count = 0 (8 bit(s))
|
||||
20 : 0;
|
||||
21 : 0;
|
||||
22 : 0;
|
||||
23 : 0;
|
||||
24 : 0;
|
||||
25 : 0;
|
||||
26 : 0;
|
||||
27 : 0; -- N counter: Odd Division = 0 (1 bit(s))
|
||||
28 : 0; -- N counter: Low Count = 0 (8 bit(s))
|
||||
29 : 0;
|
||||
30 : 0;
|
||||
31 : 0;
|
||||
32 : 0;
|
||||
33 : 0;
|
||||
34 : 0;
|
||||
35 : 0;
|
||||
36 : 0; -- M counter: Bypass = 0 (1 bit(s))
|
||||
37 : 0; -- M counter: High Count = 8 (8 bit(s))
|
||||
38 : 0;
|
||||
39 : 0;
|
||||
40 : 0;
|
||||
41 : 1;
|
||||
42 : 0;
|
||||
43 : 0;
|
||||
44 : 0;
|
||||
45 : 0; -- M counter: Odd Division = 0 (1 bit(s))
|
||||
46 : 0; -- M counter: Low Count = 8 (8 bit(s))
|
||||
47 : 0;
|
||||
48 : 0;
|
||||
49 : 0;
|
||||
50 : 1;
|
||||
51 : 0;
|
||||
52 : 0;
|
||||
53 : 0;
|
||||
54 : 0; -- clk0 counter: Bypass = 0 (1 bit(s))
|
||||
55 : 0; -- clk0 counter: High Count = 5 (8 bit(s))
|
||||
56 : 0;
|
||||
57 : 0;
|
||||
58 : 0;
|
||||
59 : 0;
|
||||
60 : 1;
|
||||
61 : 0;
|
||||
62 : 1;
|
||||
63 : 1; -- clk0 counter: Odd Division = 1 (1 bit(s))
|
||||
64 : 0; -- clk0 counter: Low Count = 4 (8 bit(s))
|
||||
65 : 0;
|
||||
66 : 0;
|
||||
67 : 0;
|
||||
68 : 0;
|
||||
69 : 1;
|
||||
70 : 0;
|
||||
71 : 0;
|
||||
72 : 1; -- clk1 counter: Bypass = 1 (1 bit(s))
|
||||
73 : 0; -- clk1 counter: High Count = 0 (8 bit(s))
|
||||
74 : 0;
|
||||
75 : 0;
|
||||
76 : 0;
|
||||
77 : 0;
|
||||
78 : 0;
|
||||
79 : 0;
|
||||
80 : 0;
|
||||
81 : 0; -- clk1 counter: Odd Division = 0 (1 bit(s))
|
||||
82 : 0; -- clk1 counter: Low Count = 0 (8 bit(s))
|
||||
83 : 0;
|
||||
84 : 0;
|
||||
85 : 0;
|
||||
86 : 0;
|
||||
87 : 0;
|
||||
88 : 0;
|
||||
89 : 0;
|
||||
90 : 1; -- clk2 counter: Bypass = 1 (1 bit(s))
|
||||
91 : 0; -- clk2 counter: High Count = 0 (8 bit(s))
|
||||
92 : 0;
|
||||
93 : 0;
|
||||
94 : 0;
|
||||
95 : 0;
|
||||
96 : 0;
|
||||
97 : 0;
|
||||
98 : 0;
|
||||
99 : 0; -- clk2 counter: Odd Division = 0 (1 bit(s))
|
||||
100 : 0; -- clk2 counter: Low Count = 0 (8 bit(s))
|
||||
101 : 0;
|
||||
102 : 0;
|
||||
103 : 0;
|
||||
104 : 0;
|
||||
105 : 0;
|
||||
106 : 0;
|
||||
107 : 0;
|
||||
108 : 1; -- clk3 counter: Bypass = 1 (1 bit(s))
|
||||
109 : 0; -- clk3 counter: High Count = 0 (8 bit(s))
|
||||
110 : 0;
|
||||
111 : 0;
|
||||
112 : 0;
|
||||
113 : 0;
|
||||
114 : 0;
|
||||
115 : 0;
|
||||
116 : 0;
|
||||
117 : 0; -- clk3 counter: Odd Division = 0 (1 bit(s))
|
||||
118 : 0; -- clk3 counter: Low Count = 0 (8 bit(s))
|
||||
119 : 0;
|
||||
120 : 0;
|
||||
121 : 0;
|
||||
122 : 0;
|
||||
123 : 0;
|
||||
124 : 0;
|
||||
125 : 0;
|
||||
126 : 1; -- clk4 counter: Bypass = 1 (1 bit(s))
|
||||
127 : 0; -- clk4 counter: High Count = 0 (8 bit(s))
|
||||
128 : 0;
|
||||
129 : 0;
|
||||
130 : 0;
|
||||
131 : 0;
|
||||
132 : 0;
|
||||
133 : 0;
|
||||
134 : 0;
|
||||
135 : 0; -- clk4 counter: Odd Division = 0 (1 bit(s))
|
||||
136 : 0; -- clk4 counter: Low Count = 0 (8 bit(s))
|
||||
137 : 0;
|
||||
138 : 0;
|
||||
139 : 0;
|
||||
140 : 0;
|
||||
141 : 0;
|
||||
142 : 0;
|
||||
143 : 0;
|
||||
END;
|
||||
174
cores/archie/fpga/mist/pll_vidc_25.mif
Normal file
174
cores/archie/fpga/mist/pll_vidc_25.mif
Normal file
@@ -0,0 +1,174 @@
|
||||
-- Copyright (C) 1991-2014 Altera Corporation
|
||||
-- Your use of Altera Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Altera Program License
|
||||
-- Subscription Agreement, Altera MegaCore Function License
|
||||
-- Agreement, or other applicable license agreement, including,
|
||||
-- without limitation, that your use is for the sole purpose of
|
||||
-- programming logic devices manufactured by Altera and sold by
|
||||
-- Altera or its authorized distributors. Please refer to the
|
||||
-- applicable agreement for further details.
|
||||
|
||||
-- MIF file representing initial state of PLL Scan Chain
|
||||
-- Device Family: Cyclone III
|
||||
-- Device Part: -
|
||||
-- Device Speed Grade: 8
|
||||
-- PLL Scan Chain: Fast PLL (144 bits)
|
||||
-- File Name: /home/gyuri/git/mist-board/cores/archie/fpga/mist/pll_vidc_25.mif
|
||||
-- Generated: Sat Feb 23 00:00:38 2019
|
||||
|
||||
WIDTH=1;
|
||||
DEPTH=144;
|
||||
|
||||
ADDRESS_RADIX=UNS;
|
||||
DATA_RADIX=UNS;
|
||||
|
||||
CONTENT BEGIN
|
||||
0 : 0; -- Reserved Bits = 0 (1 bit(s))
|
||||
1 : 0; -- Reserved Bits = 0 (1 bit(s))
|
||||
2 : 0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0)
|
||||
3 : 0;
|
||||
4 : 0; -- Loop Filter Resistance = 8 (5 bit(s)) (Setting 8)
|
||||
5 : 1;
|
||||
6 : 0;
|
||||
7 : 0;
|
||||
8 : 0;
|
||||
9 : 0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2)
|
||||
10 : 0; -- Reserved Bits = 0 (5 bit(s))
|
||||
11 : 0;
|
||||
12 : 0;
|
||||
13 : 0;
|
||||
14 : 0;
|
||||
15 : 0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1)
|
||||
16 : 0;
|
||||
17 : 1;
|
||||
18 : 0; -- N counter: Bypass = 0 (1 bit(s))
|
||||
19 : 0; -- N counter: High Count = 3 (8 bit(s))
|
||||
20 : 0;
|
||||
21 : 0;
|
||||
22 : 0;
|
||||
23 : 0;
|
||||
24 : 0;
|
||||
25 : 1;
|
||||
26 : 1;
|
||||
27 : 1; -- N counter: Odd Division = 1 (1 bit(s))
|
||||
28 : 0; -- N counter: Low Count = 2 (8 bit(s))
|
||||
29 : 0;
|
||||
30 : 0;
|
||||
31 : 0;
|
||||
32 : 0;
|
||||
33 : 0;
|
||||
34 : 1;
|
||||
35 : 0;
|
||||
36 : 0; -- M counter: Bypass = 0 (1 bit(s))
|
||||
37 : 0; -- M counter: High Count = 56 (8 bit(s))
|
||||
38 : 0;
|
||||
39 : 1;
|
||||
40 : 1;
|
||||
41 : 1;
|
||||
42 : 0;
|
||||
43 : 0;
|
||||
44 : 0;
|
||||
45 : 0; -- M counter: Odd Division = 0 (1 bit(s))
|
||||
46 : 0; -- M counter: Low Count = 56 (8 bit(s))
|
||||
47 : 0;
|
||||
48 : 1;
|
||||
49 : 1;
|
||||
50 : 1;
|
||||
51 : 0;
|
||||
52 : 0;
|
||||
53 : 0;
|
||||
54 : 0; -- clk0 counter: Bypass = 0 (1 bit(s))
|
||||
55 : 0; -- clk0 counter: High Count = 6 (8 bit(s))
|
||||
56 : 0;
|
||||
57 : 0;
|
||||
58 : 0;
|
||||
59 : 0;
|
||||
60 : 1;
|
||||
61 : 1;
|
||||
62 : 0;
|
||||
63 : 0; -- clk0 counter: Odd Division = 0 (1 bit(s))
|
||||
64 : 0; -- clk0 counter: Low Count = 6 (8 bit(s))
|
||||
65 : 0;
|
||||
66 : 0;
|
||||
67 : 0;
|
||||
68 : 0;
|
||||
69 : 1;
|
||||
70 : 1;
|
||||
71 : 0;
|
||||
72 : 1; -- clk1 counter: Bypass = 1 (1 bit(s))
|
||||
73 : 0; -- clk1 counter: High Count = 0 (8 bit(s))
|
||||
74 : 0;
|
||||
75 : 0;
|
||||
76 : 0;
|
||||
77 : 0;
|
||||
78 : 0;
|
||||
79 : 0;
|
||||
80 : 0;
|
||||
81 : 0; -- clk1 counter: Odd Division = 0 (1 bit(s))
|
||||
82 : 0; -- clk1 counter: Low Count = 0 (8 bit(s))
|
||||
83 : 0;
|
||||
84 : 0;
|
||||
85 : 0;
|
||||
86 : 0;
|
||||
87 : 0;
|
||||
88 : 0;
|
||||
89 : 0;
|
||||
90 : 1; -- clk2 counter: Bypass = 1 (1 bit(s))
|
||||
91 : 0; -- clk2 counter: High Count = 0 (8 bit(s))
|
||||
92 : 0;
|
||||
93 : 0;
|
||||
94 : 0;
|
||||
95 : 0;
|
||||
96 : 0;
|
||||
97 : 0;
|
||||
98 : 0;
|
||||
99 : 0; -- clk2 counter: Odd Division = 0 (1 bit(s))
|
||||
100 : 0; -- clk2 counter: Low Count = 0 (8 bit(s))
|
||||
101 : 0;
|
||||
102 : 0;
|
||||
103 : 0;
|
||||
104 : 0;
|
||||
105 : 0;
|
||||
106 : 0;
|
||||
107 : 0;
|
||||
108 : 1; -- clk3 counter: Bypass = 1 (1 bit(s))
|
||||
109 : 0; -- clk3 counter: High Count = 0 (8 bit(s))
|
||||
110 : 0;
|
||||
111 : 0;
|
||||
112 : 0;
|
||||
113 : 0;
|
||||
114 : 0;
|
||||
115 : 0;
|
||||
116 : 0;
|
||||
117 : 0; -- clk3 counter: Odd Division = 0 (1 bit(s))
|
||||
118 : 0; -- clk3 counter: Low Count = 0 (8 bit(s))
|
||||
119 : 0;
|
||||
120 : 0;
|
||||
121 : 0;
|
||||
122 : 0;
|
||||
123 : 0;
|
||||
124 : 0;
|
||||
125 : 0;
|
||||
126 : 1; -- clk4 counter: Bypass = 1 (1 bit(s))
|
||||
127 : 0; -- clk4 counter: High Count = 0 (8 bit(s))
|
||||
128 : 0;
|
||||
129 : 0;
|
||||
130 : 0;
|
||||
131 : 0;
|
||||
132 : 0;
|
||||
133 : 0;
|
||||
134 : 0;
|
||||
135 : 0; -- clk4 counter: Odd Division = 0 (1 bit(s))
|
||||
136 : 0; -- clk4 counter: Low Count = 0 (8 bit(s))
|
||||
137 : 0;
|
||||
138 : 0;
|
||||
139 : 0;
|
||||
140 : 0;
|
||||
141 : 0;
|
||||
142 : 0;
|
||||
143 : 0;
|
||||
END;
|
||||
174
cores/archie/fpga/mist/pll_vidc_36.mif
Normal file
174
cores/archie/fpga/mist/pll_vidc_36.mif
Normal file
@@ -0,0 +1,174 @@
|
||||
-- Copyright (C) 1991-2014 Altera Corporation
|
||||
-- Your use of Altera Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Altera Program License
|
||||
-- Subscription Agreement, Altera MegaCore Function License
|
||||
-- Agreement, or other applicable license agreement, including,
|
||||
-- without limitation, that your use is for the sole purpose of
|
||||
-- programming logic devices manufactured by Altera and sold by
|
||||
-- Altera or its authorized distributors. Please refer to the
|
||||
-- applicable agreement for further details.
|
||||
|
||||
-- MIF file representing initial state of PLL Scan Chain
|
||||
-- Device Family: Cyclone III
|
||||
-- Device Part: -
|
||||
-- Device Speed Grade: 8
|
||||
-- PLL Scan Chain: Fast PLL (144 bits)
|
||||
-- File Name: /home/gyuri/git/mist-board/cores/archie/fpga/mist/pll_vidc_36.mif
|
||||
-- Generated: Sat Feb 23 00:01:12 2019
|
||||
|
||||
WIDTH=1;
|
||||
DEPTH=144;
|
||||
|
||||
ADDRESS_RADIX=UNS;
|
||||
DATA_RADIX=UNS;
|
||||
|
||||
CONTENT BEGIN
|
||||
0 : 0; -- Reserved Bits = 0 (1 bit(s))
|
||||
1 : 0; -- Reserved Bits = 0 (1 bit(s))
|
||||
2 : 0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0)
|
||||
3 : 0;
|
||||
4 : 0; -- Loop Filter Resistance = 8 (5 bit(s)) (Setting 8)
|
||||
5 : 1;
|
||||
6 : 0;
|
||||
7 : 0;
|
||||
8 : 0;
|
||||
9 : 0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2)
|
||||
10 : 0; -- Reserved Bits = 0 (5 bit(s))
|
||||
11 : 0;
|
||||
12 : 0;
|
||||
13 : 0;
|
||||
14 : 0;
|
||||
15 : 0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1)
|
||||
16 : 0;
|
||||
17 : 1;
|
||||
18 : 0; -- N counter: Bypass = 0 (1 bit(s))
|
||||
19 : 0; -- N counter: High Count = 3 (8 bit(s))
|
||||
20 : 0;
|
||||
21 : 0;
|
||||
22 : 0;
|
||||
23 : 0;
|
||||
24 : 0;
|
||||
25 : 1;
|
||||
26 : 1;
|
||||
27 : 1; -- N counter: Odd Division = 1 (1 bit(s))
|
||||
28 : 0; -- N counter: Low Count = 2 (8 bit(s))
|
||||
29 : 0;
|
||||
30 : 0;
|
||||
31 : 0;
|
||||
32 : 0;
|
||||
33 : 0;
|
||||
34 : 1;
|
||||
35 : 0;
|
||||
36 : 0; -- M counter: Bypass = 0 (1 bit(s))
|
||||
37 : 0; -- M counter: High Count = 60 (8 bit(s))
|
||||
38 : 0;
|
||||
39 : 1;
|
||||
40 : 1;
|
||||
41 : 1;
|
||||
42 : 1;
|
||||
43 : 0;
|
||||
44 : 0;
|
||||
45 : 0; -- M counter: Odd Division = 0 (1 bit(s))
|
||||
46 : 0; -- M counter: Low Count = 60 (8 bit(s))
|
||||
47 : 0;
|
||||
48 : 1;
|
||||
49 : 1;
|
||||
50 : 1;
|
||||
51 : 1;
|
||||
52 : 0;
|
||||
53 : 0;
|
||||
54 : 0; -- clk0 counter: Bypass = 0 (1 bit(s))
|
||||
55 : 0; -- clk0 counter: High Count = 5 (8 bit(s))
|
||||
56 : 0;
|
||||
57 : 0;
|
||||
58 : 0;
|
||||
59 : 0;
|
||||
60 : 1;
|
||||
61 : 0;
|
||||
62 : 1;
|
||||
63 : 1; -- clk0 counter: Odd Division = 1 (1 bit(s))
|
||||
64 : 0; -- clk0 counter: Low Count = 4 (8 bit(s))
|
||||
65 : 0;
|
||||
66 : 0;
|
||||
67 : 0;
|
||||
68 : 0;
|
||||
69 : 1;
|
||||
70 : 0;
|
||||
71 : 0;
|
||||
72 : 1; -- clk1 counter: Bypass = 1 (1 bit(s))
|
||||
73 : 0; -- clk1 counter: High Count = 0 (8 bit(s))
|
||||
74 : 0;
|
||||
75 : 0;
|
||||
76 : 0;
|
||||
77 : 0;
|
||||
78 : 0;
|
||||
79 : 0;
|
||||
80 : 0;
|
||||
81 : 0; -- clk1 counter: Odd Division = 0 (1 bit(s))
|
||||
82 : 0; -- clk1 counter: Low Count = 0 (8 bit(s))
|
||||
83 : 0;
|
||||
84 : 0;
|
||||
85 : 0;
|
||||
86 : 0;
|
||||
87 : 0;
|
||||
88 : 0;
|
||||
89 : 0;
|
||||
90 : 1; -- clk2 counter: Bypass = 1 (1 bit(s))
|
||||
91 : 0; -- clk2 counter: High Count = 0 (8 bit(s))
|
||||
92 : 0;
|
||||
93 : 0;
|
||||
94 : 0;
|
||||
95 : 0;
|
||||
96 : 0;
|
||||
97 : 0;
|
||||
98 : 0;
|
||||
99 : 0; -- clk2 counter: Odd Division = 0 (1 bit(s))
|
||||
100 : 0; -- clk2 counter: Low Count = 0 (8 bit(s))
|
||||
101 : 0;
|
||||
102 : 0;
|
||||
103 : 0;
|
||||
104 : 0;
|
||||
105 : 0;
|
||||
106 : 0;
|
||||
107 : 0;
|
||||
108 : 1; -- clk3 counter: Bypass = 1 (1 bit(s))
|
||||
109 : 0; -- clk3 counter: High Count = 0 (8 bit(s))
|
||||
110 : 0;
|
||||
111 : 0;
|
||||
112 : 0;
|
||||
113 : 0;
|
||||
114 : 0;
|
||||
115 : 0;
|
||||
116 : 0;
|
||||
117 : 0; -- clk3 counter: Odd Division = 0 (1 bit(s))
|
||||
118 : 0; -- clk3 counter: Low Count = 0 (8 bit(s))
|
||||
119 : 0;
|
||||
120 : 0;
|
||||
121 : 0;
|
||||
122 : 0;
|
||||
123 : 0;
|
||||
124 : 0;
|
||||
125 : 0;
|
||||
126 : 1; -- clk4 counter: Bypass = 1 (1 bit(s))
|
||||
127 : 0; -- clk4 counter: High Count = 0 (8 bit(s))
|
||||
128 : 0;
|
||||
129 : 0;
|
||||
130 : 0;
|
||||
131 : 0;
|
||||
132 : 0;
|
||||
133 : 0;
|
||||
134 : 0;
|
||||
135 : 0; -- clk4 counter: Odd Division = 0 (1 bit(s))
|
||||
136 : 0; -- clk4 counter: Low Count = 0 (8 bit(s))
|
||||
137 : 0;
|
||||
138 : 0;
|
||||
139 : 0;
|
||||
140 : 0;
|
||||
141 : 0;
|
||||
142 : 0;
|
||||
143 : 0;
|
||||
END;
|
||||
3
cores/archie/fpga/mist/rom_reconfig_24.qip
Normal file
3
cores/archie/fpga/mist/rom_reconfig_24.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "rom_reconfig_24.v"]
|
||||
164
cores/archie/fpga/mist/rom_reconfig_24.v
Normal file
164
cores/archie/fpga/mist/rom_reconfig_24.v
Normal file
@@ -0,0 +1,164 @@
|
||||
// megafunction wizard: %ROM: 1-PORT%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altsyncram
|
||||
|
||||
// ============================================================
|
||||
// File Name: rom_reconfig_24.v
|
||||
// Megafunction Name(s):
|
||||
// altsyncram
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2014 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module rom_reconfig_24 (
|
||||
address,
|
||||
clock,
|
||||
rden,
|
||||
q);
|
||||
|
||||
input [7:0] address;
|
||||
input clock;
|
||||
input rden;
|
||||
output [0:0] q;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_off
|
||||
`endif
|
||||
tri1 clock;
|
||||
tri1 rden;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_on
|
||||
`endif
|
||||
|
||||
wire [0:0] sub_wire0;
|
||||
wire [0:0] q = sub_wire0[0:0];
|
||||
|
||||
altsyncram altsyncram_component (
|
||||
.address_a (address),
|
||||
.clock0 (clock),
|
||||
.rden_a (rden),
|
||||
.q_a (sub_wire0),
|
||||
.aclr0 (1'b0),
|
||||
.aclr1 (1'b0),
|
||||
.address_b (1'b1),
|
||||
.addressstall_a (1'b0),
|
||||
.addressstall_b (1'b0),
|
||||
.byteena_a (1'b1),
|
||||
.byteena_b (1'b1),
|
||||
.clock1 (1'b1),
|
||||
.clocken0 (1'b1),
|
||||
.clocken1 (1'b1),
|
||||
.clocken2 (1'b1),
|
||||
.clocken3 (1'b1),
|
||||
.data_a (1'b1),
|
||||
.data_b (1'b1),
|
||||
.eccstatus (),
|
||||
.q_b (),
|
||||
.rden_b (1'b1),
|
||||
.wren_a (1'b0),
|
||||
.wren_b (1'b0));
|
||||
defparam
|
||||
altsyncram_component.address_aclr_a = "NONE",
|
||||
altsyncram_component.clock_enable_input_a = "BYPASS",
|
||||
altsyncram_component.clock_enable_output_a = "BYPASS",
|
||||
altsyncram_component.init_file = "../pll_vidc_24.mif",
|
||||
altsyncram_component.intended_device_family = "Cyclone III",
|
||||
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
|
||||
altsyncram_component.lpm_type = "altsyncram",
|
||||
altsyncram_component.numwords_a = 256,
|
||||
altsyncram_component.operation_mode = "ROM",
|
||||
altsyncram_component.outdata_aclr_a = "NONE",
|
||||
altsyncram_component.outdata_reg_a = "CLOCK0",
|
||||
altsyncram_component.widthad_a = 8,
|
||||
altsyncram_component.width_a = 1,
|
||||
altsyncram_component.width_byteena_a = 1;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
|
||||
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Clken NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
|
||||
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
||||
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: MIFfilename STRING "../pll_vidc_24.mif"
|
||||
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
|
||||
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
|
||||
// Retrieval info: PRIVATE: WidthData NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: rden NUMERIC "1"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: INIT_FILE STRING "../pll_vidc_24.mif"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
||||
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
|
||||
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
|
||||
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
|
||||
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
|
||||
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
|
||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
|
||||
// Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL "q[0..0]"
|
||||
// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
|
||||
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
|
||||
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
|
||||
// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
|
||||
// Retrieval info: CONNECT: q 0 0 1 0 @q_a 0 0 1 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_24.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_24.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_24.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_24.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_24_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_24_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
3
cores/archie/fpga/mist/rom_reconfig_25.qip
Normal file
3
cores/archie/fpga/mist/rom_reconfig_25.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "rom_reconfig_25.v"]
|
||||
164
cores/archie/fpga/mist/rom_reconfig_25.v
Normal file
164
cores/archie/fpga/mist/rom_reconfig_25.v
Normal file
@@ -0,0 +1,164 @@
|
||||
// megafunction wizard: %ROM: 1-PORT%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altsyncram
|
||||
|
||||
// ============================================================
|
||||
// File Name: rom_reconfig_25.v
|
||||
// Megafunction Name(s):
|
||||
// altsyncram
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2014 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module rom_reconfig_25 (
|
||||
address,
|
||||
clock,
|
||||
rden,
|
||||
q);
|
||||
|
||||
input [7:0] address;
|
||||
input clock;
|
||||
input rden;
|
||||
output [0:0] q;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_off
|
||||
`endif
|
||||
tri1 clock;
|
||||
tri1 rden;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_on
|
||||
`endif
|
||||
|
||||
wire [0:0] sub_wire0;
|
||||
wire [0:0] q = sub_wire0[0:0];
|
||||
|
||||
altsyncram altsyncram_component (
|
||||
.address_a (address),
|
||||
.clock0 (clock),
|
||||
.rden_a (rden),
|
||||
.q_a (sub_wire0),
|
||||
.aclr0 (1'b0),
|
||||
.aclr1 (1'b0),
|
||||
.address_b (1'b1),
|
||||
.addressstall_a (1'b0),
|
||||
.addressstall_b (1'b0),
|
||||
.byteena_a (1'b1),
|
||||
.byteena_b (1'b1),
|
||||
.clock1 (1'b1),
|
||||
.clocken0 (1'b1),
|
||||
.clocken1 (1'b1),
|
||||
.clocken2 (1'b1),
|
||||
.clocken3 (1'b1),
|
||||
.data_a (1'b1),
|
||||
.data_b (1'b1),
|
||||
.eccstatus (),
|
||||
.q_b (),
|
||||
.rden_b (1'b1),
|
||||
.wren_a (1'b0),
|
||||
.wren_b (1'b0));
|
||||
defparam
|
||||
altsyncram_component.address_aclr_a = "NONE",
|
||||
altsyncram_component.clock_enable_input_a = "BYPASS",
|
||||
altsyncram_component.clock_enable_output_a = "BYPASS",
|
||||
altsyncram_component.init_file = "../pll_vidc_25.mif",
|
||||
altsyncram_component.intended_device_family = "Cyclone III",
|
||||
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
|
||||
altsyncram_component.lpm_type = "altsyncram",
|
||||
altsyncram_component.numwords_a = 256,
|
||||
altsyncram_component.operation_mode = "ROM",
|
||||
altsyncram_component.outdata_aclr_a = "NONE",
|
||||
altsyncram_component.outdata_reg_a = "CLOCK0",
|
||||
altsyncram_component.widthad_a = 8,
|
||||
altsyncram_component.width_a = 1,
|
||||
altsyncram_component.width_byteena_a = 1;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
|
||||
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Clken NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
|
||||
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
||||
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: MIFfilename STRING "../pll_vidc_25.mif"
|
||||
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
|
||||
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
|
||||
// Retrieval info: PRIVATE: WidthData NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: rden NUMERIC "1"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: INIT_FILE STRING "../pll_vidc_25.mif"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
||||
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
|
||||
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
|
||||
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
|
||||
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
|
||||
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
|
||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
|
||||
// Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL "q[0..0]"
|
||||
// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
|
||||
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
|
||||
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
|
||||
// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
|
||||
// Retrieval info: CONNECT: q 0 0 1 0 @q_a 0 0 1 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_25.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_25.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_25.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_25.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_25_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_25_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
3
cores/archie/fpga/mist/rom_reconfig_36.qip
Normal file
3
cores/archie/fpga/mist/rom_reconfig_36.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "rom_reconfig_36.v"]
|
||||
164
cores/archie/fpga/mist/rom_reconfig_36.v
Normal file
164
cores/archie/fpga/mist/rom_reconfig_36.v
Normal file
@@ -0,0 +1,164 @@
|
||||
// megafunction wizard: %ROM: 1-PORT%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altsyncram
|
||||
|
||||
// ============================================================
|
||||
// File Name: rom_reconfig_36.v
|
||||
// Megafunction Name(s):
|
||||
// altsyncram
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2014 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module rom_reconfig_36 (
|
||||
address,
|
||||
clock,
|
||||
rden,
|
||||
q);
|
||||
|
||||
input [7:0] address;
|
||||
input clock;
|
||||
input rden;
|
||||
output [0:0] q;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_off
|
||||
`endif
|
||||
tri1 clock;
|
||||
tri1 rden;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_on
|
||||
`endif
|
||||
|
||||
wire [0:0] sub_wire0;
|
||||
wire [0:0] q = sub_wire0[0:0];
|
||||
|
||||
altsyncram altsyncram_component (
|
||||
.address_a (address),
|
||||
.clock0 (clock),
|
||||
.rden_a (rden),
|
||||
.q_a (sub_wire0),
|
||||
.aclr0 (1'b0),
|
||||
.aclr1 (1'b0),
|
||||
.address_b (1'b1),
|
||||
.addressstall_a (1'b0),
|
||||
.addressstall_b (1'b0),
|
||||
.byteena_a (1'b1),
|
||||
.byteena_b (1'b1),
|
||||
.clock1 (1'b1),
|
||||
.clocken0 (1'b1),
|
||||
.clocken1 (1'b1),
|
||||
.clocken2 (1'b1),
|
||||
.clocken3 (1'b1),
|
||||
.data_a (1'b1),
|
||||
.data_b (1'b1),
|
||||
.eccstatus (),
|
||||
.q_b (),
|
||||
.rden_b (1'b1),
|
||||
.wren_a (1'b0),
|
||||
.wren_b (1'b0));
|
||||
defparam
|
||||
altsyncram_component.address_aclr_a = "NONE",
|
||||
altsyncram_component.clock_enable_input_a = "BYPASS",
|
||||
altsyncram_component.clock_enable_output_a = "BYPASS",
|
||||
altsyncram_component.init_file = "pll_vidc_36.mif",
|
||||
altsyncram_component.intended_device_family = "Cyclone III",
|
||||
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
|
||||
altsyncram_component.lpm_type = "altsyncram",
|
||||
altsyncram_component.numwords_a = 256,
|
||||
altsyncram_component.operation_mode = "ROM",
|
||||
altsyncram_component.outdata_aclr_a = "NONE",
|
||||
altsyncram_component.outdata_reg_a = "CLOCK0",
|
||||
altsyncram_component.widthad_a = 8,
|
||||
altsyncram_component.width_a = 1,
|
||||
altsyncram_component.width_byteena_a = 1;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
|
||||
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Clken NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
|
||||
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
||||
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: MIFfilename STRING "pll_vidc_36.mif"
|
||||
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
|
||||
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
|
||||
// Retrieval info: PRIVATE: WidthData NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: rden NUMERIC "1"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: INIT_FILE STRING "pll_vidc_36.mif"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
||||
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
|
||||
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
|
||||
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
|
||||
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
|
||||
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
|
||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
|
||||
// Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL "q[0..0]"
|
||||
// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
|
||||
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
|
||||
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
|
||||
// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
|
||||
// Retrieval info: CONNECT: q 0 0 1 0 @q_a 0 0 1 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_36.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_36.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_36.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_36.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_36_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_36_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
Reference in New Issue
Block a user