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Reduced 1541 clock slightly to cope with fast loaders

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harbaum
2018-08-30 10:18:40 +02:00
parent 000a28d920
commit 64b44825bf
1 changed files with 1 additions and 1 deletions
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cores/c16/c1541/c1541_logic.vhd
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@@ -123,7 +123,7 @@ begin
clk_1M_pulse <= '1';
end if;
-- if count = "000100000" then -- DAR divide by 33 (otherwise real c64 miss EOI acknowledge)
if count = "000011111" then -- TH divide by 32
if count = "000011110" then -- TH divide by 31
count := (others => '0'); -- DAR
else -- DAR
count := std_logic_vector(unsigned(count) + 1);