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Merge pull request #87 from gyurco/archie

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Archie speedup (CPU + SDRAM)
This commit is contained in:
gyurco
2019-03-08 10:13:13 +01:00
committed by GitHub
parent f141ee22e3 9b19a1f1b8
commit 7563ad2ac6
16 changed files with 185 additions and 147 deletions
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10
cores/archie/bench/sdram/sdram.cpp
View File

@@ -17,7 +17,7 @@ vluint64_t main_time = 0; // Current simulation time
// This is a 64-bit integer to reduce wrap over issues and
// allow modulus. You can also use a double, if you wish.
double sc_time_stamp () { // Called by $time in Verilog
return main_time; // converts to double, to match
return (double)main_time*3.8; // converts to double, to match
// what SystemC does
}
@@ -30,10 +30,10 @@ void tick()
uut->RESET = 0; // Deassert reset
}
uut->DRAM_CLK = uut->DRAM_CLK ? 0 : 1; // Toggle clock
uut->DRAM_CLK = uut->DRAM_CLK ? 0 : 1; // Toggle SDRAM clock
DRAM_CLK.Update(uut->DRAM_CLK);
if ((main_time % 4) == 0)
if ((main_time % 3) == 0)
{
uut->wb_clk = uut->wb_clk ? 0 : 1; // Toggle clock
wb_clk.Update(uut->wb_clk);
@@ -43,7 +43,7 @@ void tick()
if (tfp != NULL)
{
tfp->dump(main_time);
tfp->dump(main_time*3.8);
}
main_time++; // Time passes...

2
cores/archie/bench/sdram/sdram.v
View File

@@ -54,7 +54,7 @@ sdram_top uut(
.wb_clk ( wb_clk ),
.wb_stb ( wb_stb ),
.wb_cyc ( wb_cyc ),
.wb_we ( wb_wr ),
.wb_we ( wb_we ),
.wb_ack ( wb_ack ),
.wb_sel ( wb_sel ),
.wb_adr ( wb_adr ),

20
cores/archie/bench/support/mt48lc16m16a2.v
View File

@@ -159,7 +159,7 @@ module mt48lc16m16a2 (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm);
`define A_REF 5
`define BST 6
`define LMR 7
/*
// Timing Parameters for -7E PC133 CL2
parameter tAC = 5.4;
parameter tHZ = 5.4;
@@ -173,6 +173,20 @@ module mt48lc16m16a2 (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm);
parameter tRRD = 14.0;
parameter tWRa = 7.0; // A2 Version - Auto precharge mode (1 Clk + 7 ns)
parameter tWRm = 14.0; // A2 Version - Manual precharge mode (14 ns)
*/
// Timing Parameters for -75 PC133 CL3
parameter tAC = 5.4;
parameter tHZ = 5.4;
parameter tOH = 3.0;
parameter tMRD = 2.0; // 2 Clk Cycles
parameter tRAS = 37.0;
parameter tRC = 60.0;
parameter tRCD = 20.0;
parameter tRFC = 66.0;
parameter tRP = 20.0;
parameter tRRD = 15.0;
parameter tWRa = 7.5; // A2 Version - Auto precharge mode (1 Clk + 7.5 ns)
parameter tWRm = 15.0; // A2 Version - Manual precharge mode (15 ns)
// Timing Check variable
time MRD_chk;
@@ -425,7 +439,7 @@ end
// Record variables
Act_b0 = 1'b1;
//$display ("%m : Bank 0 activated at time %t", $time);
$display ("%m : Bank 0 activated at time %t", $time);
Pc_b0 = 1'b0;
B0_row_addr = Addr [addr_bits - 1 : 0];
RAS_chk0 = $time;
@@ -655,7 +669,7 @@ end
(Ba == 2'b01) && ($time - RCD_chk1 < tRCD) ||
(Ba == 2'b10) && ($time - RCD_chk2 < tRCD) ||
(Ba == 2'b11) && ($time - RCD_chk3 < tRCD)) begin
$display("%m : at time %t ERROR: tRCD violation during Read", $time);
$display("%m : at time %t ERROR: tRCD violation during Read %t %t %t %t", $time, $time-RCD_chk0, $time-RCD_chk1, $time-RCD_chk2, $time-RCD_chk3 );
end
// CAS Latency pipeline

5
cores/archie/fpga/mist/archimedes_mist_top.qsf
View File

@@ -171,7 +171,7 @@ set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name FITTER_EFFORT "AUTO FIT"
set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[*]
set_global_assignment -name SEED 1
@@ -201,8 +201,6 @@ set_global_assignment -name VERILOG_FILE ../../rtl/ioc_irq.v
set_global_assignment -name VERILOG_FILE ../../rtl/ioc.v
set_global_assignment -name VERILOG_FILE ../../rtl/amber/a23_barrel_shift.v
set_global_assignment -name VERILOG_FILE ../../rtl/memc_translator.v
set_global_assignment -name VERILOG_FILE ../../rtl/gdb/slgdb_debug.v
set_global_assignment -name VERILOG_FILE ../../sw/testdata/screenbox.v
set_global_assignment -name VERILOG_FILE ../../rtl/vidc_fifo.v
set_global_assignment -name VERILOG_FILE ../../rtl/vidc_timing.v
set_global_assignment -name VERILOG_FILE ../../rtl/vidc.v
@@ -228,4 +226,5 @@ set_global_assignment -name QIP_FILE rom_reconfig_36.qip
set_global_assignment -name QIP_FILE pll_vidc.qip
set_global_assignment -name SIGNALTAP_FILE output_files/vidc.stp
set_global_assignment -name SIGNALTAP_FILE output_files/sd.stp
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

4
cores/archie/fpga/mist/archimedes_mist_top.sdc
View File

@@ -100,8 +100,8 @@ set_false_path -to [get_ports {LED}]
# Set Multicycle Path
#**************************************************************
set_multicycle_path -from [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[1]}] -setup 4
set_multicycle_path -from [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[1]}] -hold 3
set_multicycle_path -from [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[1]}] -setup 3
set_multicycle_path -from [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[1]}] -hold 2
set_multicycle_path -to {VGA_*[*]} -setup 4
set_multicycle_path -to {VGA_*[*]} -hold 3

37
cores/archie/fpga/mist/archimedes_mist_top.v
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@@ -67,8 +67,8 @@ wire kbd_in_strobe;
// generated clocks
wire clk_pix;
wire ce_pix;
wire clk_32m /* synthesis keep */ ;
wire clk_128m /* synthesis keep */ ;
wire clk_sys /* synthesis keep */ ;
wire clk_mem /* synthesis keep */ ;
//wire clk_8m /* synthesis keep */ ;
wire pll_ready;
@@ -106,9 +106,8 @@ wire ypbpr;
clockgen CLOCKS(
.inclk0 (CLOCK_27[0]),
.c0 (clk_32m),
.c1 (clk_128m),
// .c2 (clk_50m),
.c0 (clk_sys), // 40 MHz
.c1 (clk_mem), // 120 MHz
.c3 (DRAM_CLK),
.locked (pll_ready) // pll locked output
);
@@ -147,7 +146,7 @@ wire q_reconfig_36;
rom_reconfig_25 rom_reconfig_25
(
.address(pll_rom_address),
.clock(CLOCK_27[0]),
.clock(clk_sys),
.rden(pll_write_rom_ena),
.q(q_reconfig_25)
);
@@ -155,7 +154,7 @@ rom_reconfig_25 rom_reconfig_25
rom_reconfig_24 rom_reconfig_24
(
.address(pll_rom_address),
.clock(CLOCK_27[0]),
.clock(clk_sys),
.rden(pll_write_rom_ena),
.q(q_reconfig_24)
);
@@ -163,7 +162,7 @@ rom_reconfig_24 rom_reconfig_24
rom_reconfig_36 rom_reconfig_36
(
.address(pll_rom_address),
.clock(CLOCK_27[0]),
.clock(clk_sys),
.rden(pll_write_rom_ena),
.q(q_reconfig_36)
);
@@ -174,7 +173,7 @@ assign pll_rom_q = pixbaseclk_select == 2'b01 ? q_reconfig_25 :
pll_reconfig pll_reconfig_inst
(
.busy(pll_reconfig_busy),
.clock(CLOCK_27[0]),
.clock(clk_sys),
.counter_param(0),
.counter_type(0),
.data_in(0),
@@ -197,7 +196,7 @@ pll_reconfig pll_reconfig_inst
.write_rom_ena(pll_write_rom_ena)
);
always @(posedge CLOCK_27[0]) begin
always @(posedge clk_sys) begin
reg [1:0] pixbaseclk_select_d;
reg [1:0] pll_reconfig_state = 0;
reg [9:0] pll_reconfig_timeout;
@@ -237,7 +236,7 @@ end
wire [5:0] osd_r_o, osd_g_o, osd_b_o;
osd #(0,0,4) OSD (
osd #(10'd0,10'd0,4) OSD (
.clk_sys ( clk_pix ),
// spi for OSD
@@ -296,7 +295,7 @@ assign SPI_DO = (CONF_DATA0==0)?user_io_sdo:1'bZ;
wire user_io_sdo;
user_io user_io(
// the spi interface
.clk_sys ( clk_32m ),
.clk_sys ( clk_sys ),
.SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ),
.SPI_MISO (user_io_sdo ), // tristate handling inside user_io
@@ -331,7 +330,7 @@ user_io user_io(
.img_size ( img_size )
);
data_io # ( .START_ADDR(26'h40_0000) )
data_io # ( .START_ADDR(24'h40_0000) )
DATA_IO (
.sck ( SPI_SCK ),
.ss ( SPI_SS2 ),
@@ -342,7 +341,7 @@ DATA_IO (
.index ( dio_index ),
// ram interface
.clk ( clk_32m ),
.clk ( clk_sys ),
.wr ( loader_we ),
.a ( loader_addr ),
.sel ( loader_sel ),
@@ -366,7 +365,7 @@ wire i2c_din, i2c_dout, i2c_clock;
archimedes_top ARCHIMEDES(
.CLKCPU_I ( clk_32m ),
.CLKCPU_I ( clk_sys ),
.CLKPIX_I ( clk_pix ), // pixel clock for OSD
.CEPIX_O ( ce_pix ),
@@ -432,7 +431,7 @@ wire [25:0] ram_address/* synthesis keep */ ;
sdram_top SDRAM(
// wishbone interface
.wb_clk ( clk_32m ),
.wb_clk ( clk_sys ),
.wb_stb ( ram_stb ),
.wb_cyc ( ram_cyc ),
.wb_we ( ram_we ),
@@ -445,7 +444,7 @@ sdram_top SDRAM(
.wb_cti ( core_cti_o ),
// SDRAM Interface
.sd_clk ( clk_128m ),
.sd_clk ( clk_mem ),
.sd_rst ( ~pll_ready ),
.sd_cke ( DRAM_CKE ),
@@ -461,7 +460,7 @@ sdram_top SDRAM(
);
i2cSlaveTop CMOS (
.clk ( clk_32m ),
.clk ( clk_sys ),
.rst ( ~pll_ready ),
.sdaIn ( i2c_din ),
.sdaOut ( i2c_dout ),
@@ -480,7 +479,7 @@ audio AUDIO (
.audio_r ( AUDIO_R )
);
always @(posedge clk_32m) begin
always @(posedge clk_sys) begin
reg loader_active_old;
loader_active_old <= loader_active;

38
cores/archie/fpga/mist/clockgen.v
View File

@@ -111,17 +111,17 @@ module clockgen (
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 27,
altpll_component.clk0_divide_by = 9,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 32,
altpll_component.clk0_multiply_by = 14,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 27,
altpll_component.clk1_divide_by = 3,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 128,
altpll_component.clk1_multiply_by = 14,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk3_divide_by = 27,
altpll_component.clk3_divide_by = 3,
altpll_component.clk3_duty_cycle = 50,
altpll_component.clk3_multiply_by = 128,
altpll_component.clk3_multiply_by = 14,
altpll_component.clk3_phase_shift = "-1845",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
@@ -202,9 +202,9 @@ endmodule
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "32.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "128.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "128.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "42.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "126.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "126.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -235,9 +235,9 @@ endmodule
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "32.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "128.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "128.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "42.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "126.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "126.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
@@ -263,6 +263,7 @@ endmodule
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clockgen.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
@@ -289,17 +290,17 @@ endmodule
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "32"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "14"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "128"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "14"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "27"
// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "3"
// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "128"
// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "14"
// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "-1845"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
@@ -371,6 +372,5 @@ endmodule
// Retrieval info: GEN_FILE: TYPE_NORMAL clockgen.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clockgen_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clockgen_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clockgen.mif FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

2
cores/archie/fpga/mist/data_io.v
View File

@@ -126,7 +126,7 @@ always @(posedge clk) begin
end else if (spi_receiver_strobeD ^ spi_receiver_strobe) begin
if(~&abyte_cnt)
abyte_cnt <= abyte_cnt + 8'd1;
abyte_cnt <= abyte_cnt + 1'd1;
if(!abyte_cnt) begin
acmd <= spi_byte_in;

4
cores/archie/fpga/mist/user_io.v
View File

@@ -227,7 +227,7 @@ always @(posedge clk_sys) begin
reg spi_transfer_end;
reg spi_receiver_strobeD;
reg spi_transfer_endD;
reg sd_wrD;
reg [1:0] sd_wrD;
reg [7:0] acmd;
reg [7:0] abyte_cnt; // counts bytes
@@ -245,7 +245,7 @@ always @(posedge clk_sys) begin
sd_din_strobe<= 0;
sd_wrD <= sd_wr;
// fetch the first byte immediately after the write command seen
if (~sd_wrD & sd_wr) begin
if ((~sd_wrD[0] & sd_wr[0]) || (~sd_wrD[1] & sd_wr[1])) begin
sd_buff_addr <= 0;
sd_din_strobe <= 1;
end

22
cores/archie/rtl/fdc1772.v
View File

@@ -62,7 +62,7 @@ module fdc1772 (
input sd_din_strobe
);
localparam CLK = 32000000;
localparam CLK = 42000000;
localparam CLK_EN = 8000000;
// -------------------------------------------------------------------------
@@ -75,10 +75,10 @@ reg [1:0] floppy_ready = 0;
reg [1:0] floppy_wp = 1;
wire floppy_present = (floppy_drive == 4'b1110)?floppy_ready[0]:
(floppy_drive == 4'b1101)?floppy_ready[1]:0;
(floppy_drive == 4'b1101)?floppy_ready[1]:1'b0;
wire floppy_write_protected = (floppy_drive == 4'b1110)?floppy_wp[0]:
(floppy_drive == 4'b1101)?floppy_wp[1]:1;
(floppy_drive == 4'b1101)?floppy_wp[1]:1'b1;
always @(posedge clkcpu) begin
reg [1:0] img_mountedD;
@@ -319,7 +319,7 @@ wire fd_track0 = (fd_track == 0);
// reached full speed for 5 rotations (800ms spin-up time + 5*200ms =
// 1.8sec) If the floppy is idle for 10 rotations (2 sec) then the
// motor is switched off again
localparam MOTOR_IDLE_COUNTER = 10;
localparam MOTOR_IDLE_COUNTER = 4'd10;
reg [3:0] motor_timeout_index;
reg indexD;
reg busy;
@@ -406,7 +406,7 @@ always @(posedge clkcpu) begin
// all type 1 commands are step commands and step_to has been set
if(fd_track == step_to) begin
busy <= 1'b0; // done if reached track 0
motor_timeout_index <= MOTOR_IDLE_COUNTER - 1;
motor_timeout_index <= MOTOR_IDLE_COUNTER - 1'd1;
irq_set <= 1'b1; // emit irq when command done
end else begin
// do the step
@@ -430,7 +430,7 @@ always @(posedge clkcpu) begin
if(!floppy_present) begin
// no image selected -> send irq immediately
busy <= 1'b0;
motor_timeout_index <= MOTOR_IDLE_COUNTER - 1;
motor_timeout_index <= MOTOR_IDLE_COUNTER - 1'd1;
irq_set <= 1'b1; // emit irq when command done
end else begin
// read sector
@@ -447,7 +447,7 @@ always @(posedge clkcpu) begin
if(data_transfer_done) begin
busy <= 1'b0;
motor_timeout_index <= MOTOR_IDLE_COUNTER - 1;
motor_timeout_index <= MOTOR_IDLE_COUNTER - 1'd1;
irq_set <= 1'b1; // emit irq when command done
end
end
@@ -458,7 +458,7 @@ always @(posedge clkcpu) begin
if (data_transfer_done) sd_card_write <= 1;
if (sd_card_done) begin
busy <= 1'b0;
motor_timeout_index <= MOTOR_IDLE_COUNTER - 1;
motor_timeout_index <= MOTOR_IDLE_COUNTER - 1'd1;
irq_set <= 1'b1; // emit irq when command done
end
end
@@ -470,7 +470,7 @@ always @(posedge clkcpu) begin
if(!floppy_present) begin
// no image selected -> send irq immediately
busy <= 1'b0;
motor_timeout_index <= MOTOR_IDLE_COUNTER - 1;
motor_timeout_index <= MOTOR_IDLE_COUNTER - 1'd1;
irq_set <= 1'b1; // emit irq when command done
end else begin
// read address
@@ -481,7 +481,7 @@ always @(posedge clkcpu) begin
if(data_transfer_done) begin
busy <= 1'b0;
motor_timeout_index <= MOTOR_IDLE_COUNTER - 1;
motor_timeout_index <= MOTOR_IDLE_COUNTER - 1'd1;
irq_set <= 1'b1; // emit irq when command done
end
end
@@ -692,7 +692,7 @@ localparam FDC_REG_SECTOR = 2;
localparam FDC_REG_DATA = 3;
// CPU register read
always @(wb_stb, wb_cyc, wb_adr, wb_we) begin
always @(*) begin
wb_dat_o = 8'h00;
if(wb_stb && wb_cyc && !wb_we) begin

36
cores/archie/rtl/floppy.v
View File

@@ -43,19 +43,19 @@ assign sector_hdr = (sec_state == SECTOR_STATE_HDR);
assign sector_data = (sec_state == SECTOR_STATE_DATA);
// a standard DD floppy has a data rate of 250kBit/s and rotates at 300RPM
localparam RATE = 250000;
localparam RPM = 300;
localparam STEPBUSY = 18; // 18ms after step data can be read
localparam SPINUP = 500; // drive spins up in up to 800ms
localparam SPINDOWN = 300; // GUESSED: drive spins down in 300ms
localparam INDEX_PULSE_LEN = 5; // fd1036 data sheet says 1~8ms
localparam SECTOR_HDR_LEN = 6; // GUESSED: Sector header is 6 bytes
localparam TRACKS = 85; // max allowed track
localparam RATE = 20'd250000;
localparam RPM = 10'd300;
localparam STEPBUSY = 8'd18; // 18ms after step data can be read
localparam SPINUP = 10'd500; // drive spins up in up to 800ms
localparam SPINDOWN = 10'd300; // GUESSED: drive spins down in 300ms
localparam INDEX_PULSE_LEN = 4'd5; // fd1036 data sheet says 1~8ms
localparam SECTOR_HDR_LEN = 4'd6; // GUESSED: Sector header is 6 bytes
localparam TRACKS = 8'd85; // max allowed track
// Archimedes specific values
localparam SECTOR_LEN = 1024; // Default sector size is 1k on Archie ...
localparam SPT = 5; // ... with 5 sectors per track
localparam SECTOR_BASE = 0; // number of first sector on track (archie 0, dos 1)
localparam SECTOR_LEN = 11'd1024; // Default sector size is 1k on Archie ...
localparam SPT = 4'd5; // ... with 5 sectors per track
localparam SECTOR_BASE = 4'd0; // number of first sector on track (archie 0, dos 1)
// number of physical bytes per track
localparam BPT = RATE*60/(8*RPM);
@@ -85,7 +85,7 @@ end
// ======================= track handling =========================
// ================================================================
localparam STEP_BUSY_CLKS = (SYS_CLK/1000)*STEPBUSY; // steprate is in ms
localparam[19:0] STEP_BUSY_CLKS = (SYS_CLK/1000)*STEPBUSY; // steprate is in ms
assign track = current_track;
reg [6:0] current_track = 7'd0;
@@ -139,7 +139,7 @@ reg [3:0] current_sector = SECTOR_BASE;
always @(posedge clk) begin
if (byte_clk_en) begin
if(index_pulse_start) begin
sec_byte_cnt <= SECTOR_GAP_LEN-1;
sec_byte_cnt <= SECTOR_GAP_LEN-1'd1;
sec_state <= SECTOR_STATE_GAP; // track starts with gap
current_sector <= start_sector; // track starts with sector 1
end else begin
@@ -147,17 +147,17 @@ always @(posedge clk) begin
case(sec_state)
SECTOR_STATE_GAP: begin
sec_state <= SECTOR_STATE_HDR;
sec_byte_cnt <= SECTOR_HDR_LEN-1;
sec_byte_cnt <= SECTOR_HDR_LEN-1'd1;
end
SECTOR_STATE_HDR: begin
sec_state <= SECTOR_STATE_DATA;
sec_byte_cnt <= SECTOR_LEN-1;
sec_byte_cnt <= SECTOR_LEN-1'd1;
end
SECTOR_STATE_DATA: begin
sec_state <= SECTOR_STATE_GAP;
sec_byte_cnt <= SECTOR_GAP_LEN-1;
sec_byte_cnt <= SECTOR_GAP_LEN-1'd1;
if(current_sector == SECTOR_BASE+SPT-1)
current_sector <= SECTOR_BASE;
else
@@ -191,7 +191,7 @@ always @(posedge clk) begin
byte_cnt <= 0;
index_pulse_start <= 1'b1;
end else
byte_cnt <= byte_cnt + 1;
byte_cnt <= byte_cnt + 1'd1;
end
end
@@ -203,7 +203,7 @@ reg [2:0] clk_cnt2;
always @(posedge clk) begin
byte_clk_en <= 0;
if (data_clk_en) begin
clk_cnt2 <= clk_cnt2 + 1;
clk_cnt2 <= clk_cnt2 + 1'd1;
if (clk_cnt2 == 3'b011) byte_clk_en <= 1;
end
end

19
cores/archie/rtl/ioc.v
View File

@@ -69,8 +69,7 @@ module ioc(
input kbd_in_strobe
);
reg [3:0] clk2m_count;
reg [1:0] clk8m_count;
reg [4:0] clken_counter;
wire [7:0] irqa_dout, irqb_dout, firq_dout;
wire irqa_req, irqb_req, firq_req;
@@ -229,9 +228,6 @@ initial begin
ctrl_state = 6'h3F;
clk8m_count = 'd0;
clk2m_count = 'd0;
ir_r = 1'b1;
end
@@ -253,10 +249,10 @@ always @(posedge clkcpu) begin
end
// increment the clock counters.
clk2m_count <= clk2m_count + 'd1;
clk8m_count <= clk8m_count + 'd1;
// increment the clock counter. 42 MHz clkcpu assumed.
clken_counter <= clken_counter + 1'd1;
if (clken_counter == 20) clken_counter <= 0;
if (write_request & ctrl_selected) begin
ctrl_state <= wb_dat_i[5:0];
@@ -288,9 +284,8 @@ assign ctrl_dout = { ir, 1'b1, c_in & c_out };
assign ir_edge = ~ir_r & ir;
// pulse the 2mhz & 8mhz clock enable line high when all the bits are set.
assign clk2m_en = &clk2m_count;
assign clk8m_en = &clk8m_count;
assign clk2m_en = !clken_counter;
assign clk8m_en = clken_counter == 0 || clken_counter == 5 || clken_counter == 10 || clken_counter == 15;
assign wb_dat_o = read_request ?
(ctrl_selected ? ctrl_dout :

2
cores/archie/rtl/latches.v
View File

@@ -99,7 +99,7 @@ assign floppy_density = ext_latch_b[1];
assign floppy_reset = ext_latch_b[3];
assign wb_dat_o = wb_adr == 14'h001e ? {3'b011, joy0} :
wb_adr == 14'h001f ? {3'b011, joy1} : 32'hFFFFFFFF;
wb_adr == 14'h001f ? {3'b011, joy1} : 8'hFF;
assign baseclk = ext_latch_c[1:0];
assign syncpol = ext_latch_c[3:2];

12
cores/archie/rtl/memc.v
View File

@@ -127,6 +127,12 @@ localparam REG_SendN = 3'b101;
localparam REG_Sptr = 3'b110;
localparam REG_Ctrl = 3'b111;
wire table_valid;
wire err;
wire memw;
wire logcs;
wire vidc_cs;
wire mem_virtual;
wire[25:0] phys_address;
memc_translator PAGETABLES(
@@ -332,12 +338,12 @@ always @(posedge clkcpu) begin
if ((vidak & vid_load) == 1'b1) begin
// advance the pointer to the next location.
vid_address <= vid_address + 4;
vid_address <= vid_address + 4'd4;
end else if ((vidak & cur_load) == 1'b1) begin
// advance the cursor pointer to the next location.
cur_address <= cur_address + 4;
cur_address <= cur_address + 4'd4;
end
@@ -358,7 +364,7 @@ always @(posedge clkcpu) begin
if ((sndak & snd_load) == 1'b1) begin
// advance the pointer to the next location.
snd_sptr <= snd_sptr + 4;
snd_sptr <= snd_sptr + 4'd4;
end
end else begin

117
cores/archie/rtl/sdram/sdram_top.v
View File

@@ -78,9 +78,11 @@ reg [3:0] sd_cmd = 4'd0; // current command sent to sd ram
reg [9:0] sd_refresh = 10'd0;
reg sd_auto_refresh = 1'b0;
wire sd_reading;
wire sd_writing;
wire sd_req = wb_stb & wb_cyc & ~wb_ack;
reg [11:0] sd_active_row[3:0];
reg [3:0] sd_bank_active;
wire [1:0] sd_bank = wb_adr[22:21];
wire [11:0] sd_row = wb_adr[20:9];
initial begin
t = 4'd0;
@@ -89,9 +91,10 @@ initial begin
sd_cmd = CMD_INHIBIT;
end
localparam CYCLE_RAS_START = 4'd1;
localparam CYCLE_PRECHARGE = 4'd0;
localparam CYCLE_RAS_START = 4'd3;
localparam CYCLE_RFSH_START = CYCLE_RAS_START;
localparam CYCLE_CAS0 = CYCLE_RFSH_START + RASCAS_DELAY;
localparam CYCLE_CAS0 = CYCLE_RAS_START + RASCAS_DELAY;
localparam CYCLE_CAS1 = CYCLE_CAS0 + 4'd1;
localparam CYCLE_CAS2 = CYCLE_CAS1 + 4'd1;
localparam CYCLE_CAS3 = CYCLE_CAS2 + 4'd1;
@@ -99,22 +102,30 @@ localparam CYCLE_READ0 = CYCLE_CAS0 + CAS_LATENCY + 4'd1;
localparam CYCLE_READ1 = CYCLE_READ0+ 1'd1;
localparam CYCLE_READ2 = CYCLE_READ1+ 1'd1;
localparam CYCLE_READ3 = CYCLE_READ2+ 1'd1;
localparam CYCLE_END = 4'hF;
localparam CYCLE_WR_END = CYCLE_CAS1 + 4'd4;
localparam CYCLE_END = CYCLE_READ3+ 1'd1;
localparam CYCLE_RFSH_END = CYCLE_RFSH_START + RFC_DELAY;
localparam RAM_CLK = 128000000;
localparam REFRESH_PERIOD = (RAM_CLK / (16 * 8192)) - CYCLE_END;
`ifdef VERILATOR
reg [15:0] sd_q;
assign sd_dq = (sd_writing && (sd_cycle == CYCLE_CAS1 || sd_cycle == CYCLE_CAS2)) ? sd_q : 16'bZZZZZZZZZZZZZZZZ;
`endif
always @(posedge sd_clk) begin
`ifndef VERILATOR
sd_dq <= 16'bZZZZZZZZZZZZZZZZ;
`endif
sd_cmd <= CMD_NOP;
if (sd_rst) begin
t <= 4'd0;
reset <= 5'h1f;
sd_addr <= 13'd0;
sd_ready <= 0;
end else begin
sd_dq <= 16'bZZZZZZZZZZZZZZZZ;
if (!sd_ready) begin
t <= t + 4'd1;
@@ -148,8 +159,7 @@ always @(posedge sd_clk) begin
// bring the wishbone bus signal into the ram clock domain.
sd_we <= wb_we;
sd_cmd <= CMD_INHIBIT;
if (wb_stb & wb_cyc & ~wb_ack) begin
if (sd_req) begin
sd_stb <= wb_stb;
sd_cyc <= wb_cyc;
end
@@ -163,31 +173,46 @@ always @(posedge sd_clk) begin
if ((sd_refresh > REFRESH_PERIOD) && (sd_cycle == 4'd0)) begin
sd_auto_refresh <= 1'b1;
sd_refresh <= 10'd0;
sd_cmd <= CMD_PRECHARGE;
sd_addr[10] <= 1;
sd_bank_active <= 0;
end else if (sd_auto_refresh) begin
// while the cycle is active count.
sd_cycle <= sd_cycle + 3'd1;
case (sd_cycle)
CYCLE_RFSH_START: begin
sd_cmd <= CMD_AUTO_REFRESH;
CYCLE_RFSH_START: begin
sd_cmd <= CMD_AUTO_REFRESH;
end
CYCLE_RFSH_END: begin
CYCLE_RFSH_END: begin
// reset the count.
sd_auto_refresh <= 1'b0;
sd_cycle <= 4'd0;
end
endcase
end else if (sd_cyc | (sd_cycle != 0)) begin
end else if (sd_cyc | (sd_cycle != 0) | (sd_cycle == 0 && sd_req)) begin
// while the cycle is active count.
sd_cycle <= sd_cycle + 3'd1;
//sd_cmd <= CMD_NOP;
case (sd_cycle)
CYCLE_PRECHARGE: begin
if (~sd_bank_active[sd_bank])
sd_cycle <= CYCLE_RAS_START;
else if (sd_active_row[sd_bank] == sd_row)
sd_cycle <= CYCLE_CAS0 - 1'd1; // FIXME: Why doesn't work without -1?
else begin
sd_cmd <= CMD_PRECHARGE;
sd_addr[10] <= 0;
sd_ba <= sd_bank;
end
end
CYCLE_RAS_START: begin
sd_cmd <= CMD_ACTIVE;
sd_addr <= { 1'b0, wb_adr[20:9] };
sd_ba <= wb_adr[22:21];
sd_addr <= { 1'b0, sd_row };
sd_ba <= sd_bank;
sd_active_row[sd_bank] <= sd_row;
sd_bank_active[sd_bank] <= 1;
if(sd_reading) begin
sd_dqm <= 2'b00;
@@ -200,30 +225,38 @@ always @(posedge sd_clk) begin
CYCLE_CAS0: begin
// always, always read on a 32bit boundary and completely ignore the lsb of wb_adr.
sd_addr <= { 4'b0000, wb_adr[23], wb_adr[8:2], 1'b0 }; // no auto precharge
sd_dqm <= ~wb_sel[1:0];
sd_dqm <= ~wb_sel[1:0];
sd_ba <= sd_bank;
if (sd_reading) begin
sd_cmd <= CMD_READ;
end else if (sd_writing) begin
sd_cmd <= CMD_WRITE;
sd_dq <= wb_dat_i[15:0];
`ifdef VERILATOR
sd_q <= wb_dat_i[15:0];
`else
sd_dq <= wb_dat_i[15:0];
`endif
end
end
CYCLE_CAS1: begin
// now we access the second part of the 32 bit location.
sd_addr <= { 4'b0010, wb_adr[23], wb_adr[8:2], 1'b1 }; // auto precharge
sd_addr <= { 4'b0000, wb_adr[23], wb_adr[8:2], 1'b1 }; // no auto precharge
sd_dqm <= ~wb_sel[3:2];
if (sd_reading) begin
sd_cmd <= CMD_READ;
if (burst_mode & can_burst) begin
sd_addr[10] <= 1'b0;
sd_burst <= 1'b1;
end
end else if (sd_writing) begin
end else if (sd_writing) begin
sd_cmd <= CMD_WRITE;
sd_done <= ~sd_done;
`ifdef VERILATOR
sd_q <= wb_dat_i[31:16];
`else
sd_dq <= wb_dat_i[31:16];
sd_done <= 1'b1;
`endif
end
end
@@ -241,32 +274,26 @@ always @(posedge sd_clk) begin
CYCLE_CAS3: begin
if (sd_burst) begin
// always, always read on a 32bit boundary and completely ignore the lsb of wb_adr.
sd_addr <= { 4'b0010, wb_adr[23], wb_adr[8:3], 2'b11 }; // no auto precharge
sd_addr <= { 4'b0000, wb_adr[23], wb_adr[8:3], 2'b11 }; // no auto precharge
sd_dqm <= ~wb_sel[3:2];
if (sd_reading) begin
sd_cmd <= CMD_READ;
end
end
end
end
CYCLE_READ0: begin
if (sd_writing) begin
// if we are writing then the sd_done signal has been high for
// enough clock cycles. we can end the cycle here.
sd_done <= 1'b0;
sd_cycle <= 4'd0;
sd_cyc <= 1'b0;
sd_stb <= 1'b0;
end
if (sd_reading) begin
sd_dat[15:0] <= sd_dq;
end
end else begin
if (sd_writing) sd_cycle <= CYCLE_END;
end
end
CYCLE_READ1: begin
if (sd_reading) begin
sd_dat[31:16] <= sd_dq;
sd_done <= 1'b1;
sd_done <= ~sd_done;
end
end
@@ -284,13 +311,11 @@ always @(posedge sd_clk) begin
CYCLE_END: begin
sd_burst <= 1'b0;
sd_done <= 1'b0;
sd_cyc <= 1'b0;
sd_stb <= 1'b0;
end
endcase
end else begin
sd_done <= 1'd0;
sd_cycle <= 4'd0;
sd_burst <= 1'b0;
end
@@ -301,12 +326,14 @@ end
reg wb_burst;
always @(posedge wb_clk) begin
reg sd_doneD;
wb_ack <= sd_done & ~wb_ack;
sd_doneD <= sd_done;
wb_ack <= (sd_done ^ sd_doneD) & ~wb_ack;
if (wb_stb & wb_cyc) begin
if (sd_done & ~wb_ack) begin
if ((sd_done ^ sd_doneD) & ~wb_ack) begin
wb_dat_o <= sd_dat;
wb_burst <= burst_mode;
@@ -331,10 +358,10 @@ always @(posedge wb_clk) begin
end
assign burst_mode = wb_cti == 3'b010;
assign can_burst = wb_adr[2] === 1'b0;
assign sd_reading = sd_stb & sd_cyc & ~sd_we;
assign sd_writing = sd_stb & sd_cyc & sd_we;
wire burst_mode = wb_cti == 3'b010;
wire can_burst = wb_adr[2] === 1'b0;
wire sd_reading = sd_stb & sd_cyc & ~sd_we;
wire sd_writing = sd_stb & sd_cyc & sd_we;
// drive control signals according to current command
assign sd_cs_n = sd_cmd[3];

2
cores/archie/rtl/vidc_timing.v
View File

@@ -86,7 +86,6 @@ reg [9:0] vidc_hber; // horizontal border end
// cursor registers
reg [10:0] vidc_hcsr; // horizontal cursor start
reg [10:0] vidc_hcer; // horizontal cursor start
reg [9:0] vidc_vcsr; // vertical cursor start
reg [9:0] vidc_vcer; // vertical cursor end
@@ -113,7 +112,6 @@ initial begin
vidc_hber = 10'd0; // horizontal border end
vidc_hcsr = 11'd0; // horizontal cursor start
vidc_hcer = 11'd0; // horizontal cursor end
vidc_vcsr = 10'd0; // vertical cursor start
vidc_vcer = 10'd0; // vertical cursor end