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Merge pull request #86 from gyurco/archie

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Archie fixes
This commit is contained in:
gyurco
2019-03-03 17:54:42 +01:00
committed by GitHub
parent f8f31ea5ce ca812da031
commit f141ee22e3
8 changed files with 83 additions and 256 deletions
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11
cores/archie/fpga/mist/archimedes_mist_top.qsf
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@@ -136,7 +136,7 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_*
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/vidc.stp
set_global_assignment -name USE_SIGNALTAP_FILE output_files/sd.stp
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
@@ -161,7 +161,7 @@ set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
set_location_assignment PIN_7 -to LED
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
@@ -174,8 +174,9 @@ set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[*]
set_global_assignment -name SEED 2
set_global_assignment -name SEED 1
set_global_assignment -name ENABLE_DRC_SETTINGS OFF
set_location_assignment PLL_1 -to CLOCKS|altpll_component|auto_generated|pll1
set_global_assignment -name VERILOG_FILE archimedes_mist_top.v
set_global_assignment -name SYSTEMVERILOG_FILE rgb2ypbpr.sv
set_global_assignment -name VERILOG_FILE sigma_delta_dac.v
@@ -187,7 +188,6 @@ set_global_assignment -name VERILOG_FILE sram_line_en.v
set_global_assignment -name VERILOG_FILE sram_byte_en.v
set_global_assignment -name QIP_FILE clockgen.qip
set_global_assignment -name VERILOG_FILE ../../rtl/fdc1772.v
set_global_assignment -name VERILOG_FILE ../../rtl/vidc_divider.v
set_global_assignment -name VERILOG_FILE ../../rtl/latches.v
set_global_assignment -name VERILOG_FILE ../../rtl/floppy.v
set_global_assignment -name VERILOG_FILE ../../rtl/podules.v
@@ -221,12 +221,11 @@ set_global_assignment -name VERILOG_FILE ../../rtl/amber/a23_cache.v
set_global_assignment -name VERILOG_FILE ../../rtl/amber/a23_alu.v
set_global_assignment -name VERILOG_FILE ../../rtl/archimedes_top.v
set_global_assignment -name VERILOG_FILE ../../rtl/sdram/sdram_top.v
set_global_assignment -name VERILOG_FILE ../../rtl/sdram/sdram_init.v
set_global_assignment -name QIP_FILE rom_reconfig_24.qip
set_global_assignment -name QIP_FILE rom_reconfig_25.qip
set_global_assignment -name QIP_FILE pll_reconfig.qip
set_location_assignment PLL_1 -to CLOCKS|altpll_component|auto_generated|pll1
set_global_assignment -name QIP_FILE rom_reconfig_36.qip
set_global_assignment -name QIP_FILE pll_vidc.qip
set_global_assignment -name SIGNALTAP_FILE output_files/vidc.stp
set_global_assignment -name SIGNALTAP_FILE output_files/sd.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

15
cores/archie/fpga/mist/archimedes_mist_top.v
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@@ -83,8 +83,10 @@ wire core_hs, core_vs;
wire [15:0] coreaud_l, coreaud_r;
// data loading
wire loader_active /* synthesis keep */ ;
wire loader_we /* synthesis keep */ ;
wire downloading;
wire loader_active = downloading && (dio_index == 1 || dio_index == 2);
wire [7:0] dio_index;
wire loader_we /* synthesis keep */ ;
reg loader_stb = 1'b0 /* synthesis keep */ ;
reg rom_ready = 0;
(*KEEP="TRUE"*)wire [3:0] loader_sel /* synthesis keep */ ;
@@ -289,7 +291,6 @@ wire [8:0] sd_buff_addr;
wire [1:0] img_mounted;
wire [31:0] img_size;
// de-multiplex spi outputs from user_io and data_io
assign SPI_DO = (CONF_DATA0==0)?user_io_sdo:1'bZ;
wire user_io_sdo;
@@ -336,8 +337,9 @@ DATA_IO (
.ss ( SPI_SS2 ),
.sdi ( SPI_DI ),
.downloading ( loader_active ),
.downloading ( downloading ),
.size ( ),
.index ( dio_index ),
// ram interface
.clk ( clk_32m ),
@@ -463,7 +465,10 @@ i2cSlaveTop CMOS (
.rst ( ~pll_ready ),
.sdaIn ( i2c_din ),
.sdaOut ( i2c_dout ),
.scl ( i2c_clock )
.scl ( i2c_clock ),
.we ( downloading && dio_index == 3 && loader_we ),
.addr ( loader_addr[7:0] ),
.data ( loader_data[7:0] )
);
audio AUDIO (

11
cores/archie/fpga/mist/data_io.v
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@@ -31,6 +31,7 @@ module data_io #(parameter ADDR_WIDTH=24, START_ADDR = 0) (
output reg downloading, // signal indicating an active download
output [ADDR_WIDTH-1:0] size, // number of bytes in input buffer
output reg [7:0] index, // menu index
// external ram interface
input clk,
@@ -54,7 +55,6 @@ assign size = addr - START_ADDR;
// this core supports only the display related OSD commands
// of the minimig
reg [6:0] sbuf;
reg [7:0] cmd;
reg [7:0] data;
reg [2:0] bit_cnt;
reg [2:0] byte_cnt;
@@ -63,7 +63,7 @@ reg [ADDR_WIDTH-1:0] addr;
localparam UIO_FILE_TX = 8'h53;
localparam UIO_FILE_TX_DAT = 8'h54;
localparam UIO_FILE_INDEX = 8'h55;
// data_io has its own SPI interface to the io controller
// SPI bit and byte counters
@@ -71,11 +71,9 @@ always@(posedge sck or posedge ss) begin
if(ss == 1) begin
bit_cnt <= 0;
byte_cnt <= 0;
cmd <= 0;
end else begin
if((&bit_cnt)&&(~&byte_cnt)) begin
byte_cnt <= byte_cnt + 1'd1;
if (!byte_cnt) cmd <= {sbuf, sdi};
end
bit_cnt <= bit_cnt + 1'd1;
end
@@ -124,7 +122,7 @@ always @(posedge clk) begin
// strobe is set whenever a valid byte has been received
if (~spi_transfer_endD & spi_transfer_end) begin
abyte_cnt <= 8'd0;
abyte_cnt <= 0;
end else if (spi_receiver_strobeD ^ spi_receiver_strobe) begin
if(~&abyte_cnt)
@@ -154,6 +152,9 @@ always @(posedge clk) begin
data <= spi_byte_in;
wr <= 1;
end
// index
UIO_FILE_INDEX: index <= spi_byte_in;
endcase;
end
end

55
cores/archie/rtl/fdc1772.v
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@@ -109,8 +109,13 @@ always @(posedge clkcpu)
wire irq_clr = !floppy_reset || cpu_read_status;
always @(posedge clkcpu or posedge irq_clr) begin
if(irq_clr) irq <= 1'b0;
else if(irq_set) irq <= 1'b1;
reg irq_setD;
if(irq_clr) irq <= 1'b0;
else begin
irq_setD <= irq_set;
if(~irq_setD & irq_set) irq <= 1'b1;
end
end
assign floppy_firq = irq;
@@ -345,18 +350,21 @@ wire step_busy = (step_rate_cnt != 0);
reg [7:0] step_to;
always @(posedge clkcpu) begin
reg data_transfer_can_start;
irq_set <= 0;
sd_card_read <= 0;
sd_card_write <= 0;
if(!floppy_reset) begin
motor_on <= 1'b0;
busy <= 1'b0;
step_in <= 1'b0;
step_out <= 1'b0;
irq_set <= 1'b0;
sd_card_read <= 0;
sd_card_write <= 0;
data_transfer_start <= 1'b0;
data_transfer_can_start <= 0;
end else if (clk8m_en) begin
sd_card_read <= 0;
sd_card_write <= 0;
irq_set <= 1'b0;
data_transfer_start <= 1'b0;
@@ -427,14 +435,15 @@ always @(posedge clkcpu) begin
end else begin
// read sector
if(cmd[7:5] == 3'b100) begin
if (sd_state == SD_IDLE && fifo_cpuptr == 0) sd_card_read <= 1;
if (fifo_cpuptr == 0) sd_card_read <= 1;
// we are busy until the right sector header passes under
// the head and the arm7 has delivered at least one byte
// (one byte is sufficient as the arm7 is much faster and
// all further bytes will arrive in time)
if(fd_ready && fd_sector_hdr &&
(fd_sector == sector) && (sd_buff_addr != 0))
data_transfer_start <= 1'b1;
// the head and the sd-card controller indicates the sector
// is in the fifo
if(sd_card_done) data_transfer_can_start <= 1;
if(fd_ready && fd_sector_hdr && (fd_sector == sector) && data_transfer_can_start) begin
data_transfer_can_start <= 0;
data_transfer_start <= 1;
end
if(data_transfer_done) begin
busy <= 1'b0;
@@ -447,7 +456,7 @@ always @(posedge clkcpu) begin
if(cmd[7:5] == 3'b101) begin
if (fifo_cpuptr == 0) data_transfer_start <= 1'b1;
if (data_transfer_done) sd_card_write <= 1;
if (sd_card_write_done) begin
if (sd_card_done) begin
busy <= 1'b0;
motor_timeout_index <= MOTOR_IDLE_COUNTER - 1;
irq_set <= 1'b1; // emit irq when command done
@@ -533,24 +542,28 @@ localparam SD_WRITE = 2;
reg [1:0] sd_state;
reg sd_card_write;
reg sd_card_read;
reg sd_card_write_done;
reg sd_card_done;
always @(posedge clkcpu) begin
reg sd_ackD;
reg sd_card_readD;
reg sd_card_writeD;
sd_card_readD <= sd_card_read;
sd_card_writeD <= sd_card_write;
sd_ackD <= sd_ack;
if (sd_ack) {sd_rd, sd_wr} <= 0;
if (clk8m_en) sd_card_write_done <= 0;
if (clk8m_en) sd_card_done <= 0;
case (sd_state)
SD_IDLE:
begin
s_odd <= 0;
if (sd_card_read) begin
if (~sd_card_readD & sd_card_read) begin
sd_rd <= ~{ floppy_drive[1], floppy_drive[0] };
sd_state <= SD_READ;
end
else if (sd_card_write) begin
else if (~sd_card_writeD & sd_card_write) begin
sd_wr <= ~{ floppy_drive[1], floppy_drive[0] };
sd_state <= SD_WRITE;
end
@@ -559,8 +572,10 @@ always @(posedge clkcpu) begin
SD_READ:
begin
if (sd_ackD & ~sd_ack) begin
if (s_odd) sd_state <= SD_IDLE;
else begin
if (s_odd) begin
sd_state <= SD_IDLE;
sd_card_done <= 1; // to be on the safe side now, can be issued earlier
end else begin
s_odd <= 1;
sd_rd <= ~{ floppy_drive[1], floppy_drive[0] };
end
@@ -572,7 +587,7 @@ always @(posedge clkcpu) begin
if (sd_ackD & ~sd_ack) begin
if (s_odd) begin
sd_state <= SD_IDLE;
sd_card_write_done <= 1;
sd_card_done <= 1;
end else begin
s_odd <= 1;
sd_wr <= ~{ floppy_drive[1], floppy_drive[0] };

28
cores/archie/rtl/i2cslave/i2cSlave.v
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@@ -44,21 +44,19 @@
//
`include "i2cSlave_define.v"
module i2cSlave (
clk,
rst,
sdaIn,
sdaOut,
scl
input clk,
input rst,
input sdaIn,
output sdaOut,
input scl,
// parallel write
input we,
input [7:0] addr,
input [7:0] data
);
input clk;
input rst;
input sdaIn;
output sdaOut;
input scl;
// local wires and regs
reg sdaDeb;
reg sclDeb;
@@ -154,9 +152,9 @@ end
registerInterface u_registerInterface(
.clk(clk),
.addr(regAddr),
.dataIn(dataToRegIF),
.writeEn(writeEn),
.addr(we ? addr : regAddr),
.dataIn(we ? data : dataToRegIF),
.writeEn(writeEn | we),
.dataOut(dataFromRegIF)
);

30
cores/archie/rtl/i2cslave/i2cSlaveTop.v
View File

@@ -46,29 +46,27 @@
module i2cSlaveTop (
clk,
rst,
sdaIn,
sdaOut,
scl
input clk,
input rst,
input sdaIn,
output sdaOut,
input scl,
// parallel write
input we,
input [7:0] addr,
input [7:0] data
);
input clk;
input rst;
input sdaIn;
output sdaOut;
input scl;
i2cSlave u_i2cSlave(
.clk(clk),
.rst(rst),
.sdaIn(sdaIn),
.sdaOut(sdaOut),
.scl(scl)
.scl(scl),
.we(we),
.addr(addr),
.data(data)
);
endmodule

101
cores/archie/rtl/sdram/sdram_init.v
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@@ -1,101 +0,0 @@
/* sdram_init.v
Copyright (c) 2013-2014, Stephen J. Leary
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of the Stephen J. Leary nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL STEPHEN J. LEARY BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module sdram_init(
input sd_clk,
input sd_rst,
output reg [3:0] sd_cmd,
output reg [12:0] sd_a, // 13 bit multiplexed address bus
output reg sd_rdy
);
`include "sdram_defines.v"
parameter MODE = 0;
reg [3:0] t;
reg [4:0] reset;
initial begin
t = 4'd0;
reset = 5'h1f;
sd_a = 13'd0;
sd_cmd = CMD_INHIBIT;
sd_rdy = 0;
end
always @(posedge sd_clk) begin
sd_cmd <= CMD_INHIBIT; // default: idle
if (sd_rst) begin
t <= 4'd0;
reset <= 5'h1f;
sd_a <= 13'd0;
sd_rdy <= 0;
end else begin
if (!sd_rdy) t <= t + 4'd1;
if (t ==4'hF) begin
reset <= reset - 5'd1;
end
if (t == 4'h0) begin
if(reset == 13) begin
$display("precharging all banks");
sd_cmd <= CMD_PRECHARGE;
sd_a[10] <= 1'b1; // precharge all banks
end
if(reset == 2) begin
sd_cmd <= CMD_LOAD_MODE;
sd_a <= MODE;
end
if(reset == 1) begin
$display("loading mode");
sd_cmd <= CMD_LOAD_MODE;
sd_a <= MODE;
end
if(reset == 0) sd_rdy <= 1;
end
end
end
endmodule

88
cores/archie/rtl/vidc_divider.v
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@@ -1,88 +0,0 @@
`timescale 1ns / 1ps
/* vidc_divider.v
Copyright (c) 2015, Stephen J. Leary
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the <organization> nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module vidc_divider(
input clkpix2x,
input [1:0] clk_select,
output clkpix
);
reg clk24_m;
reg clk12_m;
wire clk16_m;
reg clk8_m;
reg [1:0] pos_cnt;
reg [1:0] neg_cnt;
initial begin
clk24_m = 1'b0;
clk12_m = 1'b0;
clk8_m = 1'b0;
pos_cnt = 'd0;
neg_cnt = 'd0;
end
always @(posedge clkpix2x) begin
clk24_m <= ~clk24_m;
pos_cnt <= (pos_cnt == 2) ? 0 : pos_cnt + 1;
end
always @(negedge clkpix2x) begin
neg_cnt <= (neg_cnt == 2) ? 0 : neg_cnt + 1;
end
always @(posedge clk24_m) begin
clk12_m <= ~clk12_m;
end
always @(posedge clk16_m) begin
clk8_m <= ~clk8_m;
end
// this is a divide by 3.
assign clk16_m = ((pos_cnt != 2) && (neg_cnt != 2));
assign clkpix = clk_select == 2'b00 ? clk8_m :
clk_select == 2'b01 ? clk12_m :
clk_select == 2'b10 ? clk16_m : clk24_m;
endmodule