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Merge pull request #78 from gyurco/c64

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C16 + C64 + Archie updates
This commit is contained in:
gyurco
2019-02-14 21:01:04 +01:00
committed by GitHub
parent 0aa67161e1 df03af7003
commit 8f52db93d3
42 changed files with 6648 additions and 507 deletions
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3
cores/archie/fpga/mist/archimedes_mist_top.qsf
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@@ -134,7 +134,6 @@ set_location_assignment PIN_80 -to AUDIO_R
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DRAM_*
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_*
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_*
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE signal_tap.stp
@@ -219,4 +218,6 @@ set_global_assignment -name VERILOG_FILE ../../rtl/amber/a23_alu.v
set_global_assignment -name VERILOG_FILE ../../rtl/archimedes_top.v
set_global_assignment -name VERILOG_FILE ../../rtl/sdram/sdram_top.v
set_global_assignment -name VERILOG_FILE ../../rtl/sdram/sdram_init.v
set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[*]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

4
cores/archie/fpga/mist/archimedes_mist_top.sdc
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@@ -70,8 +70,8 @@ set_input_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|
# Set Output Delay
#**************************************************************
set_output_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[1]}] -max 1.5 [get_ports {DRAM_D* DRAM_A* DRAM_BA* DRAM_n* DRAM_CKE}]
set_output_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[1]}] -min -0.8 [get_ports {DRAM_D* DRAM_A* DRAM_BA* DRAM_n* DRAM_CKE}]
set_output_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[1]}] -max 1.5 [get_ports {DRAM_A* DRAM_BA* DRAM_CAS_N DRAM_CKE DRAM_CS_N DRAM_D* DRAM_RAS_N DRAM_WE_N}]
set_output_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[1]}] -min -0.8 [get_ports {DRAM_A* DRAM_BA* DRAM_CAS_N DRAM_CKE DRAM_CS_N DRAM_D* DRAM_RAS_N DRAM_WE_N}]
set_output_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[3]}] -max 1.5 [get_ports DRAM_CLK]
set_output_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[3]}] -min -0.8 [get_ports DRAM_CLK]

290
cores/archie/rtl/sdram/sdram_top.v
View File

@@ -32,15 +32,15 @@ module sdram_top (
input sd_clk, // sdram is accessed at 128MHz
input sd_rst, // reset the sdram controller.
output sd_cke, // clock enable.
inout [15:0] sd_dq, // 16 bit bidirectional data bus
output [12:0] sd_addr, // 13 bit multiplexed address bus
inout reg[15:0]sd_dq, // 16 bit bidirectional data bus
output reg[12:0]sd_addr, // 13 bit multiplexed address bus
output reg[1:0] sd_dqm = 2'b00, // two byte masks
output reg[1:0] sd_ba = 2'b00, // two banks
output sd_cs_n, // a single chip select
output sd_we_n, // write enable
output sd_ras_n, // row address select
output sd_cas_n, // columns address select
output sd_ready, // sd ready.
output reg sd_ready = 0, // sd ready.
// cpu/chipset interface
@@ -60,13 +60,14 @@ module sdram_top (
localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
reg [3:0] t;
reg [4:0] reset;
reg[31:0] sd_dat = 0; // data output to chipset/cpu
reg[31:0] sd_dat_nxt = 0; // data output to chipset/cpu
reg sd_stb = 1'b0; // copy of the wishbone bus signal.
reg sd_we = 1'b0; // copy of the wishbone bus signal.
reg sd_wr = 1'b0;
reg sd_cyc = 1'b0; // copy of the wishbone bus signal.
reg sd_burst = 1'b0;
@@ -74,37 +75,20 @@ reg [3:0] sd_cycle= 4'd0;
reg sd_done = 1'b0;
reg [3:0] sd_cmd = 4'd0; // current command sent to sd ram
reg [12:0] sd_a = 13'd0;
reg [15:0] sd_q = 16'd0; // data to output during write phase.
reg [9:0] sd_refresh = 10'd0;
reg sd_auto_refresh = 1'b0;
wire [3:0] sd_init_cmd;
wire [12:0] sd_init_a;
wire sd_reading;
wire sd_writing;
sdram_init #
(
.MODE(MODE)
)
INIT (
.sd_clk ( sd_clk ),
.sd_rst ( sd_rst ),
.sd_cmd ( sd_init_cmd ),
.sd_a ( sd_init_a ),
.sd_rdy ( sd_ready )
initial begin
t = 4'd0;
reset = 5'h1f;
sd_addr = 13'd0;
sd_cmd = CMD_INHIBIT;
end
);
// output data during the write phase.
assign sd_dq = (sd_wr === 1'b1) ? sd_q : 16'bZZZZZZZZZZZZZZZZ;
localparam CYCLE_RAS_START = 4'd1;
localparam CYCLE_RFSH_START = CYCLE_RAS_START;
localparam CYCLE_CAS0 = CYCLE_RFSH_START + RASCAS_DELAY;
@@ -123,163 +107,149 @@ localparam RAM_CLK = 128000000;
localparam REFRESH_PERIOD = (RAM_CLK / (16 * 8192)) - CYCLE_END;
always @(posedge sd_clk) begin
if (sd_rst) begin
t <= 4'd0;
reset <= 5'h1f;
sd_addr <= 13'd0;
sd_ready <= 0;
end else begin
sd_dq <= 16'bZZZZZZZZZZZZZZZZ;
if (!sd_ready) begin
t <= t + 4'd1;
if (t ==4'hF) begin
reset <= reset - 5'd1;
end
if (t == 4'h0) begin
if(reset == 13) begin
$display("precharging all banks");
sd_cmd <= CMD_PRECHARGE;
sd_addr[10] <= 1'b1; // precharge all banks
end
if(reset == 2) begin
sd_cmd <= CMD_LOAD_MODE;
sd_addr <= MODE;
end
if(reset == 1) begin
$display("loading mode");
sd_cmd <= CMD_LOAD_MODE;
sd_addr <= MODE;
end
if(reset == 0) sd_ready <= 1;
end
end else begin
// bring the wishbone bus signal into the ram clock domain.
sd_wr <= 1'b0; // default to not writing.
sd_we <= wb_we;
sd_cmd <= CMD_INHIBIT;
if (wb_stb & wb_cyc & ~wb_ack) begin
sd_stb <= wb_stb;
sd_cyc <= wb_cyc;
end
sd_refresh <= sd_refresh + 9'd1;
// this is the auto refresh code.
// it kicks in so that 8192 auto refreshes are
// issued in a 64ms period. Other bus operations
// are stalled during this period.
if ((sd_refresh > REFRESH_PERIOD) && (sd_cycle == 4'd0)) begin
sd_auto_refresh <= 1'b1;
sd_refresh <= 10'd0;
end else if (sd_auto_refresh) begin
// while the cycle is active count.
sd_cycle <= sd_cycle + 3'd1;
case (sd_cycle)
// bring the wishbone bus signal into the ram clock domain.
sd_we <= wb_we;
sd_cmd <= CMD_INHIBIT;
if (wb_stb & wb_cyc & ~wb_ack) begin
sd_stb <= wb_stb;
sd_cyc <= wb_cyc;
end
sd_refresh <= sd_refresh + 9'd1;
// this is the auto refresh code.
// it kicks in so that 8192 auto refreshes are
// issued in a 64ms period. Other bus operations
// are stalled during this period.
if ((sd_refresh > REFRESH_PERIOD) && (sd_cycle == 4'd0)) begin
sd_auto_refresh <= 1'b1;
sd_refresh <= 10'd0;
end else if (sd_auto_refresh) begin
// while the cycle is active count.
sd_cycle <= sd_cycle + 3'd1;
case (sd_cycle)
CYCLE_RFSH_START: begin
sd_cmd <= CMD_AUTO_REFRESH;
end
CYCLE_RFSH_END: begin
// reset the count.
sd_auto_refresh <= 1'b0;
sd_cycle <= 4'd0;
sd_cycle <= 4'd0;
end
endcase
end else if (sd_cyc | (sd_cycle != 0)) begin
// while the cycle is active count.
sd_cycle <= sd_cycle + 3'd1;
//sd_cmd <= CMD_NOP;
case (sd_cycle)
endcase
end else if (sd_cyc | (sd_cycle != 0)) begin
// while the cycle is active count.
sd_cycle <= sd_cycle + 3'd1;
//sd_cmd <= CMD_NOP;
case (sd_cycle)
CYCLE_RAS_START: begin
sd_cmd <= CMD_ACTIVE;
sd_a <= { 1'b0, wb_adr[20:9] };
sd_addr <= { 1'b0, wb_adr[20:9] };
sd_ba <= wb_adr[22:21];
if(sd_reading) begin
sd_dqm <= 2'b00;
end else begin
sd_dqm <= 2'b11;
end
end
// this is the first CAS cycle
CYCLE_CAS0: begin
// always, always read on a 32bit boundary and completely ignore the lsb of wb_adr.
sd_a <= { 4'b0000, wb_adr[23], wb_adr[8:2], 1'b0 }; // no auto precharge
sd_addr <= { 4'b0000, wb_adr[23], wb_adr[8:2], 1'b0 }; // no auto precharge
sd_dqm <= ~wb_sel[1:0];
if (sd_reading) begin
sd_cmd <= CMD_READ;
end else if (sd_writing) begin
sd_cmd <= CMD_WRITE;
sd_q <= wb_dat_i[15:0];
sd_wr <= 1'b1;
end
end
CYCLE_CAS1: begin
// now we access the second part of the 32 bit location.
sd_a <= { 4'b0010, wb_adr[23], wb_adr[8:2], 1'b1 }; // auto precharge
sd_dqm <= ~wb_sel[3:2];
if (sd_reading) begin
sd_cmd <= CMD_READ;
if (burst_mode & can_burst) begin
sd_a[10] <= 1'b0;
sd_burst <= 1'b1;
end
end else if (sd_writing) begin
sd_cmd <= CMD_WRITE;
sd_q <= wb_dat_i[31:16];
sd_dq <= wb_dat_i[15:0];
end
end
CYCLE_CAS1: begin
// now we access the second part of the 32 bit location.
sd_addr <= { 4'b0010, wb_adr[23], wb_adr[8:2], 1'b1 }; // auto precharge
sd_dqm <= ~wb_sel[3:2];
if (sd_reading) begin
sd_cmd <= CMD_READ;
if (burst_mode & can_burst) begin
sd_addr[10] <= 1'b0;
sd_burst <= 1'b1;
end
end else if (sd_writing) begin
sd_cmd <= CMD_WRITE;
sd_dq <= wb_dat_i[31:16];
sd_done <= 1'b1;
sd_wr <= 1'b1;
end
end
CYCLE_CAS2: begin
if (sd_burst) begin
// always, always read on a 32bit boundary and completely ignore the lsb of wb_adr.
sd_a <= { 4'b0000, wb_adr[23], wb_adr[8:3], 2'b10 }; // no auto precharge
sd_addr <= { 4'b0000, wb_adr[23], wb_adr[8:3], 2'b10 }; // no auto precharge
sd_dqm <= ~wb_sel[1:0];
if (sd_reading) begin
sd_cmd <= CMD_READ;
end
end
end
CYCLE_CAS3: begin
if (sd_burst) begin
// always, always read on a 32bit boundary and completely ignore the lsb of wb_adr.
sd_a <= { 4'b0010, wb_adr[23], wb_adr[8:3], 2'b11 }; // no auto precharge
sd_addr <= { 4'b0010, wb_adr[23], wb_adr[8:3], 2'b11 }; // no auto precharge
sd_dqm <= ~wb_sel[3:2];
if (sd_reading) begin
sd_cmd <= CMD_READ;
end
end
end
CYCLE_READ0: begin
if (sd_writing) begin
// if we are writing then the sd_done signal has been high for
// enough clock cycles. we can end the cycle here.
@@ -287,66 +257,45 @@ always @(posedge sd_clk) begin
sd_cycle <= 4'd0;
sd_cyc <= 1'b0;
sd_stb <= 1'b0;
end
if (sd_reading) begin
sd_dat[15:0] <= sd_dq;
end
end
CYCLE_READ1: begin
CYCLE_READ1: begin
if (sd_reading) begin
sd_dat[31:16] <= sd_dq;
sd_done <= 1'b1;
end
end
CYCLE_READ2: begin
if (sd_reading) begin
sd_dat_nxt[15:0] <= sd_dq;
end
end
CYCLE_READ3: begin
CYCLE_READ3: begin
if (sd_reading) begin
sd_dat_nxt[31:16] <= sd_dq;
end
end
CYCLE_END: begin
sd_burst <= 1'b0;
sd_done <= 1'b0;
sd_cyc <= 1'b0;
sd_stb <= 1'b0;
end
endcase
end else begin
sd_done <= 1'd0;
sd_cycle <= 4'd0;
sd_burst <= 1'b0;
endcase
end else begin
sd_done <= 1'd0;
sd_cycle <= 4'd0;
sd_burst <= 1'b0;
end
end
end
end
reg wb_burst;
@@ -388,11 +337,10 @@ assign sd_reading = sd_stb & sd_cyc & ~sd_we;
assign sd_writing = sd_stb & sd_cyc & sd_we;
// drive control signals according to current command
assign sd_cs_n = sd_ready ? sd_cmd[3] : sd_init_cmd[3];
assign sd_ras_n = sd_ready ? sd_cmd[2] : sd_init_cmd[2];
assign sd_cas_n = sd_ready ? sd_cmd[1] : sd_init_cmd[1];
assign sd_we_n = sd_ready ? sd_cmd[0] : sd_init_cmd[0];
assign sd_addr = sd_ready ? sd_a : sd_init_a;
assign sd_cs_n = sd_cmd[3];
assign sd_ras_n = sd_cmd[2];
assign sd_cas_n = sd_cmd[1];
assign sd_we_n = sd_cmd[0];
assign sd_cke = 1'b1;
endmodule

31
cores/c16/c1541/c1541_sd.vhd
View File

@@ -8,13 +8,11 @@
--
-- c1541_logic from : Mark McDougall
-- spi_controller from : Michel Stempin, Stephen A. Edwards
-- via6522 from : Arnim Laeuger, Mark McDougall, MikeJ
-- via6522 from : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
-- T65 from : Daniel Wallner, MikeJ, ehenciak
--
-- c1541_logic modified for : slow down CPU (EOI ack missed by real c64)
-- : remove iec internal OR wired
-- : synched atn_in (sometime no IRQ with real c64)
-- spi_controller modified for : sector start and size adapted + busy signal
-- c1541_logic modified for : remove iec internal OR wired
-- spi_controller replaced with mist_sd_card
-- via6522 modified for : no modification
--
--
@@ -35,6 +33,7 @@ port(
disk_num : in std_logic_vector(9 downto 0);
disk_change : in std_logic;
disk_readonly : in std_logic;
iec_atn_i : in std_logic;
iec_data_i : in std_logic;
@@ -111,6 +110,9 @@ signal track_modified : std_logic;
signal sector_offset : std_logic;
signal save_track_stage : std_logic_vector(3 downto 0);
signal wps_flag : std_logic;
signal change_timer : integer;
signal dbg_sector : std_logic_vector(4 downto 0);
signal dbg_adr_fetch : std_logic_vector(15 downto 0);
@@ -173,7 +175,7 @@ begin
freq => freq, -- motor frequency
sync_n => sync_n, -- reading SYNC bytes
byte_n => byte_n, -- byte ready
wps_n => '1', -- write-protect sense (0 = protected)
wps_n => not wps_flag, -- write-protect sense (0 = protected)
tr00_sense_n => '1', -- track 0 sense (unused?)
act => act, -- activity LED
@@ -267,7 +269,22 @@ port map
--
-- dbg_state => dbg_sd_state
--);
wps_flag <= disk_readonly when change_timer = 0 else not disk_readonly;
process (clk32,reset)
begin
if reset = '1' then
change_timer <= 0;
elsif rising_edge(clk32) then
if disk_change = '1' then
change_timer <= 1000000;
elsif change_timer /= 0 then
change_timer <= change_timer - 1;
end if;
end if;
end process;
process (clk32)
begin
if rising_edge(clk32) then

12
cores/c16/c16_mist.qsf
View File

@@ -127,7 +127,7 @@ set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name TOP_LEVEL_ENTITY c16_mist
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
@@ -144,7 +144,7 @@ set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
@@ -324,8 +324,6 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to CONF_DATA0
set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name VHDL_FILE gen_ram.vhd
set_global_assignment -name QIP_FILE pll_ntsc.qip
set_global_assignment -name QIP_FILE pll_pal.qip
set_global_assignment -name VERILOG_FILE data_io.v
set_global_assignment -name VERILOG_FILE sdram.v
set_global_assignment -name VERILOG_FILE osd.v
@@ -353,4 +351,10 @@ set_global_assignment -name VHDL_FILE t65/T65_ALU.vhd
set_global_assignment -name VHDL_FILE t65/T65.vhd
set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
set_global_assignment -name SYSTEMVERILOG_FILE rgb2ypbpr.sv
set_global_assignment -name QIP_FILE pll_c1541.qip
set_global_assignment -name QIP_FILE pll_c16.qip
set_global_assignment -name QIP_FILE rom_reconfig_pal.qip
set_global_assignment -name QIP_FILE rom_reconfig_ntsc.qip
set_global_assignment -name QIP_FILE pll_reconfig.qip
set_global_assignment -name ENABLE_DRC_SETTINGS ON
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

21
cores/c16/c16_mist.sdc
View File

@@ -33,21 +33,22 @@ derive_pll_clocks -create_base_clocks
derive_clock_uncertainty
# Clock groups
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[*]}]
set_clock_groups -asynchronous -group [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[1]}] -group [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[0]}]
set_clock_groups -asynchronous -group [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[1]}] -group [get_clocks {pll_ntsc|altpll_component|auto_generated|pll1|clk[0]}]
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll_c1541|altpll_component|auto_generated|pll1|clk[*]}]
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[*]}]
set_clock_groups -asynchronous -group [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[*]}] -group [get_clocks {pll_c1541|altpll_component|auto_generated|pll1|clk[*]}]
# Some relaxed constrain to the VGA pins. The signals should arrive together, the delay is not really important.
set_output_delay -clock [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[0]}] -max 0 [get_ports {VGA_*}]
set_output_delay -clock [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[0]}] -min -5 [get_ports {VGA_*}]
set_output_delay -clock [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[0]}] -max 0 [get_ports {VGA_*}]
set_output_delay -clock [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[0]}] -min -5 [get_ports {VGA_*}]
# SDRAM delays
set_input_delay -clock [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[0]}] -max 6.4 [get_ports SDRAM_DQ[*]]
set_input_delay -clock [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[0]}] -min 3.2 [get_ports SDRAM_DQ[*]]
set_input_delay -clock [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[0]}] -max 6.4 [get_ports SDRAM_DQ[*]]
set_input_delay -clock [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[0]}] -min 3.2 [get_ports SDRAM_DQ[*]]
set_output_delay -clock [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[0]}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_output_delay -clock [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[0]}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_output_delay -clock [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[0]}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_output_delay -clock [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[0]}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_output_delay -clock [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[0]}] -max 1.5 [get_ports {SDRAM_CLK}]
set_output_delay -clock [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[0]}] -min -0.8 [get_ports {SDRAM_CLK}]
set_false_path -to [get_ports {AUDIO_L}]
set_false_path -to [get_ports {AUDIO_R}]

147
cores/c16/c16_mist.v
View File

@@ -57,7 +57,6 @@ module c16_mist (
output [5:0] VGA_B
);
parameter MODE_PAL = 1'b1;
// -------------------------------------------------------------------------
// ------------------------------ user_io ----------------------------------
// -------------------------------------------------------------------------
@@ -72,13 +71,14 @@ parameter MODE_PAL = 1'b1;
parameter CONF_STR = {
"C16;PRG;",
"S,D64,Mount Disk;",
"F,ROM,Load Kernal;",
"O2,Scanlines,Off,On;",
"O3,Joysticks,Normal,Swapped;",
"O4,Memory,64k,16k;",
"T5,Reset;"
};
parameter CONF_STR_LEN = 8+17+20+28+18+9;
parameter CONF_STR_LEN = 8+17+18+20+28+18+9;
// the status register is controlled by the on screen display (OSD)
wire [7:0] status;
@@ -277,7 +277,7 @@ wire [7:0] ioctl_data;
wire [4:0] ioctl_index;
wire ioctl_downloading;
wire rom_download = ioctl_downloading && (ioctl_index == 5'd0);
wire rom_download = ioctl_downloading && ((ioctl_index == 5'd0) || (ioctl_index == 5'd3));
wire prg_download = ioctl_downloading && (ioctl_index == 5'd1);
// halt cpu when it's done with the current cycle
@@ -511,15 +511,15 @@ always @(negedge clk28) begin
if(ioctl_rom_wr && !last_ioctl_rom_wr) begin
rom_dl_data <= ioctl_data;
rom_dl_addr <= ioctl_addr[13:0];
c1541_dl_wr <= !ioctl_addr[15:14];
kernal_dl_wr <= ioctl_addr[15:14] == 2'd1;
basic_dl_wr <= ioctl_addr[15:14] == 2'd2;
c1541_dl_wr <= !ioctl_addr[15:14] && ioctl_index == 5'd0;
kernal_dl_wr <= ioctl_addr[15:14] == 2'd1 || ioctl_index == 5'd3;
basic_dl_wr <= ioctl_addr[15:14] == 2'd2 && ioctl_index == 5'd0;
end else
{ kernal_dl_wr, basic_dl_wr, c1541_dl_wr } <= 0;
end
// include the c16 itself
C16 #(.MODE_PAL(MODE_PAL)) c16 (
C16 c16 (
.CLK28 ( clk28 ),
.RESET ( reset ),
.WAIT ( c16_wait ),
@@ -571,8 +571,8 @@ C16 #(.MODE_PAL(MODE_PAL)) c16 (
// the FPGATED uses two different clocks for NTSC and PAL mode.
// Switching the clocks may crash the system. We might need to force a reset it.
wire clk28 = MODE_PAL?clk28_pal:clk28_ntsc;
wire pll_locked = pll_pal_locked && pll_ntsc_locked;
wire pll_locked = pll_c1541_locked && pll_c16_locked;
wire ntsc = ~c16_pal;
// tv15hkz has quarter the pixel rate, so we need a 7mhz clock for the OSD
reg clk7;
@@ -588,22 +588,127 @@ always @(posedge clk28) begin
end
// A PLL to derive the system clock from the MiSTs 27MHz
wire clk32;
wire pll_pal_locked, clk28_pal;
pll_pal pll_pal (
.inclk0( CLOCK_27 ),
.c0( clk28_pal ),
.c1( clk32 ),
.locked( pll_pal_locked )
wire pll_c1541_locked, clk32;
pll_c1541 pll_c1541 (
.inclk0 ( CLOCK_27 ),
.c0 ( clk32 ),
.locked ( pll_c1541_locked )
);
wire pll_ntsc_locked, clk28_ntsc;
pll_ntsc pll_ntsc (
.inclk0( CLOCK_27 ),
.c0( clk28_ntsc ),
.locked( pll_ntsc_locked )
wire pll_c16_locked, clk28;
pll_c16 pll_c16 (
.inclk0(CLOCK_27),
.c0(clk28),
.areset(pll_areset),
.scanclk(pll_scanclk),
.scandata(pll_scandata),
.scanclkena(pll_scanclkena),
.configupdate(pll_configupdate),
.scandataout(pll_scandataout),
.scandone(pll_scandone),
.locked(pll_c16_locked)
);
wire pll_reconfig_busy;
wire pll_areset;
wire pll_configupdate;
wire pll_scanclk;
wire pll_scanclkena;
wire pll_scandata;
wire pll_scandataout;
wire pll_scandone;
reg pll_reconfig_reset;
wire [7:0] pll_rom_address;
wire pll_rom_q;
reg pll_write_from_rom;
wire pll_write_rom_ena;
reg pll_reconfig;
wire q_reconfig_ntsc;
wire q_reconfig_pal;
rom_reconfig_pal rom_reconfig_pal
(
.address(pll_rom_address),
.clock(clk32),
.rden(pll_write_rom_ena),
.q(q_reconfig_pal)
);
rom_reconfig_ntsc rom_reconfig_ntsc
(
.address(pll_rom_address),
.clock(clk32),
.rden(pll_write_rom_ena),
.q(q_reconfig_ntsc)
);
assign pll_rom_q = ntsc ? q_reconfig_ntsc : q_reconfig_pal;
pll_reconfig pll_reconfig_inst
(
.busy(pll_reconfig_busy),
.clock(clk32),
.counter_param(0),
.counter_type(0),
.data_in(0),
.pll_areset(pll_areset),
.pll_areset_in(0),
.pll_configupdate(pll_configupdate),
.pll_scanclk(pll_scanclk),
.pll_scanclkena(pll_scanclkena),
.pll_scandata(pll_scandata),
.pll_scandataout(pll_scandataout),
.pll_scandone(pll_scandone),
.read_param(0),
.reconfig(pll_reconfig),
.reset(pll_reconfig_reset),
.reset_rom_address(0),
.rom_address_out(pll_rom_address),
.rom_data_in(pll_rom_q),
.write_from_rom(pll_write_from_rom),
.write_param(0),
.write_rom_ena(pll_write_rom_ena)
);
always @(posedge clk32) begin
reg ntsc_d, ntsc_d2, ntsc_d3;
reg [1:0] pll_reconfig_state = 0;
reg [9:0] pll_reconfig_timeout;
ntsc_d <= ntsc;
ntsc_d2 <= ntsc_d;
pll_write_from_rom <= 0;
pll_reconfig <= 0;
pll_reconfig_reset <= 0;
case (pll_reconfig_state)
2'b00:
begin
ntsc_d3 <= ntsc_d2;
if (ntsc_d2 ^ ntsc_d3) begin
pll_write_from_rom <= 1;
pll_reconfig_state <= 2'b01;
end
end
2'b01: pll_reconfig_state <= 2'b10;
2'b10:
if (~pll_reconfig_busy) begin
pll_reconfig <= 1;
pll_reconfig_state <= 2'b11;
pll_reconfig_timeout <= 10'd1000;
end
2'b11:
begin
pll_reconfig_timeout <= pll_reconfig_timeout - 1'd1;
if (pll_reconfig_timeout == 10'd1) begin
// pll_reconfig stuck in busy state
pll_reconfig_reset <= 1;
pll_reconfig_state <= 2'b00;
end
if (~pll_reconfig & ~pll_reconfig_busy) pll_reconfig_state <= 2'b00;
end
default: ;
endcase
end
// ---------------------------------------------------------------------------------
// ----------------------------------- floppy 1541 ---------------------------------
// ---------------------------------------------------------------------------------

19
cores/c16/osd.v
View File

@@ -141,8 +141,9 @@ end
reg [9:0] v_cnt;
reg [9:0] vs_low, vs_high;
wire vs_pol = vs_high < vs_low;
wire [9:0] v_dsp_width = vs_pol?vs_low:vs_high;
wire [9:0] v_dsp_ctr = { 1'b0, v_dsp_width[9:1] };
wire [9:0] v_dsp_height = vs_pol?vs_low:vs_high;
wire [9:0] v_dsp_ctr = { 1'b0, v_dsp_height[9:1] };
wire doublescan = (v_dsp_height>350);
always @(posedge clk_sys) begin
reg hsD, vsD;
@@ -172,8 +173,8 @@ end
// area in which OSD is being displayed
wire [9:0] h_osd_start = h_dsp_ctr + OSD_X_OFFSET - (OSD_WIDTH >> 1);
wire [9:0] h_osd_end = h_dsp_ctr + OSD_X_OFFSET + (OSD_WIDTH >> 1) - 1;
wire [9:0] v_osd_start = v_dsp_ctr + OSD_Y_OFFSET - (OSD_HEIGHT >> 1);
wire [9:0] v_osd_end = v_dsp_ctr + OSD_Y_OFFSET + (OSD_HEIGHT >> 1) - 1;
wire [9:0] v_osd_start = v_dsp_ctr + OSD_Y_OFFSET - (doublescan ? OSD_HEIGHT : OSD_HEIGHT >> 1);
wire [9:0] v_osd_end = v_dsp_ctr + OSD_Y_OFFSET + (doublescan ? OSD_HEIGHT : OSD_HEIGHT >> 1) - 1;
reg h_osd_active, v_osd_active;
always @(posedge clk_sys) begin
@@ -189,14 +190,12 @@ end
wire osd_de = osd_enable && h_osd_active && v_osd_active;
wire [7:0] osd_hcnt = h_cnt - h_osd_start + 7'd1; // one pixel offset for osd_byte register
wire [6:0] osd_vcnt = v_cnt - v_osd_start;
wire osd_pixel = osd_byte[osd_vcnt[3:1]];
wire [9:0] osd_hcnt = h_cnt - h_osd_start + 7'd1; // one pixel offset for osd_byte register
wire [9:0] osd_vcnt = v_cnt - v_osd_start;
reg [7:0] osd_byte;
always @(posedge clk_sys)
if (ce_pix) osd_byte <= osd_buffer[{osd_vcnt[6:4], osd_hcnt}];
always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}];
wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
wire [2:0] osd_color = OSD_COLOR;
assign red_out = !osd_de?red_in: {osd_pixel, osd_pixel, osd_color[2], red_in[5:3] };

10
cores/c16/pll_c1541.ppf Normal file
View File

@@ -0,0 +1,10 @@
<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone III" variation_name="pll_c1541" megafunction_name="ALTPLL" specifies="all_ports">
<global>
<pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="c0" direction="output" scope="external" source="clock" />
<pin name="locked" direction="output" scope="external" />
</global>
</pinplan>

4
cores/c16/pll_ntsc.qip → cores/c16/pll_c1541.qip
View File

@@ -1,4 +1,4 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_ntsc.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_ntsc.ppf"]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_c1541.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_c1541.ppf"]

40
cores/c16/pll_ntsc.v → cores/c16/pll_c1541.v
View File

@@ -4,7 +4,7 @@
// MODULE: altpll
// ============================================================
// File Name: pll_ntsc.v
// File Name: pll_c1541.v
// Megafunction Name(s):
// altpll
//
@@ -36,7 +36,7 @@
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll_ntsc (
module pll_c1541 (
inclk0,
c0,
locked);
@@ -94,14 +94,14 @@ module pll_ntsc (
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 270000,
altpll_component.clk0_divide_by = 27,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 286363,
altpll_component.clk0_multiply_by = 32,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_ntsc",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_c1541",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
@@ -171,9 +171,9 @@ endmodule
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "183"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "28.636299"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "32.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -196,9 +196,9 @@ endmodule
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "191"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.63630000"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "32.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
@@ -216,7 +216,7 @@ endmodule
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_ntsc.mif"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_c1541.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
@@ -224,7 +224,7 @@ endmodule
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.000"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
@@ -237,9 +237,9 @@ endmodule
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "270000"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "286363"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "32"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
@@ -298,12 +298,12 @@ endmodule
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c1541.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c1541.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c1541.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c1541.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c1541.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c1541_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c1541_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

17
cores/c16/pll_c16.ppf Normal file
View File

@@ -0,0 +1,17 @@
<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone III" variation_name="pll_c16" megafunction_name="ALTPLL" specifies="all_ports">
<global>
<pin name="areset" direction="input" scope="external" />
<pin name="configupdate" direction="input" scope="external" />
<pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="scanclk" direction="input" scope="external" source="clock" />
<pin name="scanclkena" direction="input" scope="external" />
<pin name="scandata" direction="input" scope="external" />
<pin name="c0" direction="output" scope="external" source="clock" />
<pin name="locked" direction="output" scope="external" />
<pin name="scandataout" direction="output" scope="external" />
<pin name="scandone" direction="output" scope="external" />
</global>
</pinplan>

4
cores/c16/pll_pal.qip → cores/c16/pll_c16.qip
View File

@@ -1,4 +1,4 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_pal.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_pal.ppf"]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_c16.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_c16.ppf"]

187
cores/c16/pll_pal.v → cores/c16/pll_c16.v
View File

@@ -4,7 +4,7 @@
// MODULE: altpll
// ============================================================
// File Name: pll_pal.v
// File Name: pll_c16.v
// Megafunction Name(s):
// altpll
//
@@ -36,39 +36,68 @@
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll_pal (
module pll_c16 (
areset,
configupdate,
inclk0,
scanclk,
scanclkena,
scandata,
c0,
c1,
locked);
locked,
scandataout,
scandone);
input areset;
input configupdate;
input inclk0;
input scanclk;
input scanclkena;
input scandata;
output c0;
output c1;
output locked;
output scandataout;
output scandone;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 configupdate;
tri0 scanclkena;
tri0 scandata;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire6 = 1'h0;
wire [0:0] sub_wire3 = sub_wire0[0:0];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire locked = sub_wire2;
wire c0 = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
wire sub_wire3;
wire sub_wire4;
wire [0:0] sub_wire7 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire scandataout = sub_wire2;
wire scandone = sub_wire3;
wire locked = sub_wire4;
wire sub_wire5 = inclk0;
wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
altpll altpll_component (
.inclk (sub_wire5),
.areset (areset),
.configupdate (configupdate),
.inclk (sub_wire6),
.scanclk (scanclk),
.scanclkena (scanclkena),
.scandata (scandata),
.clk (sub_wire0),
.locked (sub_wire2),
.scandataout (sub_wire2),
.scandone (sub_wire3),
.locked (sub_wire4),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
@@ -85,11 +114,6 @@ module pll_pal (
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
@@ -98,28 +122,24 @@ module pll_pal (
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 39,
altpll_component.clk0_divide_by = 27000000,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 41,
altpll_component.clk0_multiply_by = 28375151,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 27,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 32,
altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_pal",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_c16",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_USED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
@@ -131,15 +151,15 @@ module pll_pal (
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_USED",
altpll_component.port_scanclkena = "PORT_USED",
altpll_component.port_scandata = "PORT_USED",
altpll_component.port_scandataout = "PORT_USED",
altpll_component.port_scandone = "PORT_USED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
@@ -155,7 +175,8 @@ module pll_pal (
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
altpll_component.width_clock = 5,
altpll_component.scan_chain_mif_file = "pll_c16_pal.mif";
endmodule
@@ -179,12 +200,9 @@ endmodule
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "39"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "28.384615"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "32.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "28.375153"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -205,28 +223,20 @@ endmodule
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "41"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.37500000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "32.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.37515200"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
@@ -235,38 +245,31 @@ endmodule
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_pal.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_c16_pal.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "1"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.000"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "39"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27000000"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "41"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "28375151"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "32"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
@@ -274,12 +277,12 @@ endmodule
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
@@ -291,15 +294,15 @@ endmodule
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
@@ -316,22 +319,38 @@ endmodule
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: CONSTANT: scan_chain_mif_file STRING "pll_c16_pal.mif"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: configupdate 0 0 0 0 INPUT GND "configupdate"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk"
// Retrieval info: USED_PORT: scanclkena 0 0 0 0 INPUT GND "scanclkena"
// Retrieval info: USED_PORT: scandata 0 0 0 0 INPUT GND "scandata"
// Retrieval info: USED_PORT: scandataout 0 0 0 0 OUTPUT VCC "scandataout"
// Retrieval info: USED_PORT: scandone 0 0 0 0 OUTPUT VCC "scandone"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
// Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0
// Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal_bb.v FALSE
// Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0
// Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16.mif FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16_ntsc.mif TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16_pal.mif TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

174
cores/c16/pll_c16_ntsc.mif Normal file
View File

@@ -0,0 +1,174 @@
-- Copyright (C) 1991-2014 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- MIF file representing initial state of PLL Scan Chain
-- Device Family: Cyclone III
-- Device Part: -
-- Device Speed Grade: 8
-- PLL Scan Chain: Fast PLL (144 bits)
-- File Name: /home/gyurco/git/mist-board/cores/c16/pll_c16_ntsc.mif
-- Generated: Thu Feb 14 11:24:12 2019
WIDTH=1;
DEPTH=144;
ADDRESS_RADIX=UNS;
DATA_RADIX=UNS;
CONTENT BEGIN
0 : 0; -- Reserved Bits = 0 (1 bit(s))
1 : 0; -- Reserved Bits = 0 (1 bit(s))
2 : 0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0)
3 : 0;
4 : 1; -- Loop Filter Resistance = 16 (5 bit(s)) (Setting 16)
5 : 0;
6 : 0;
7 : 0;
8 : 0;
9 : 0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2)
10 : 0; -- Reserved Bits = 0 (5 bit(s))
11 : 0;
12 : 0;
13 : 0;
14 : 0;
15 : 0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1)
16 : 0;
17 : 1;
18 : 0; -- N counter: Bypass = 0 (1 bit(s))
19 : 0; -- N counter: High Count = 2 (8 bit(s))
20 : 0;
21 : 0;
22 : 0;
23 : 0;
24 : 0;
25 : 1;
26 : 0;
27 : 1; -- N counter: Odd Division = 1 (1 bit(s))
28 : 0; -- N counter: Low Count = 1 (8 bit(s))
29 : 0;
30 : 0;
31 : 0;
32 : 0;
33 : 0;
34 : 0;
35 : 1;
36 : 0; -- M counter: Bypass = 0 (1 bit(s))
37 : 0; -- M counter: High Count = 35 (8 bit(s))
38 : 0;
39 : 1;
40 : 0;
41 : 0;
42 : 0;
43 : 1;
44 : 1;
45 : 0; -- M counter: Odd Division = 0 (1 bit(s))
46 : 0; -- M counter: Low Count = 35 (8 bit(s))
47 : 0;
48 : 1;
49 : 0;
50 : 0;
51 : 0;
52 : 1;
53 : 1;
54 : 0; -- clk0 counter: Bypass = 0 (1 bit(s))
55 : 0; -- clk0 counter: High Count = 11 (8 bit(s))
56 : 0;
57 : 0;
58 : 0;
59 : 1;
60 : 0;
61 : 1;
62 : 1;
63 : 0; -- clk0 counter: Odd Division = 0 (1 bit(s))
64 : 0; -- clk0 counter: Low Count = 11 (8 bit(s))
65 : 0;
66 : 0;
67 : 0;
68 : 1;
69 : 0;
70 : 1;
71 : 1;
72 : 1; -- clk1 counter: Bypass = 1 (1 bit(s))
73 : 0; -- clk1 counter: High Count = 0 (8 bit(s))
74 : 0;
75 : 0;
76 : 0;
77 : 0;
78 : 0;
79 : 0;
80 : 0;
81 : 0; -- clk1 counter: Odd Division = 0 (1 bit(s))
82 : 0; -- clk1 counter: Low Count = 0 (8 bit(s))
83 : 0;
84 : 0;
85 : 0;
86 : 0;
87 : 0;
88 : 0;
89 : 0;
90 : 1; -- clk2 counter: Bypass = 1 (1 bit(s))
91 : 0; -- clk2 counter: High Count = 0 (8 bit(s))
92 : 0;
93 : 0;
94 : 0;
95 : 0;
96 : 0;
97 : 0;
98 : 0;
99 : 0; -- clk2 counter: Odd Division = 0 (1 bit(s))
100 : 0; -- clk2 counter: Low Count = 0 (8 bit(s))
101 : 0;
102 : 0;
103 : 0;
104 : 0;
105 : 0;
106 : 0;
107 : 0;
108 : 1; -- clk3 counter: Bypass = 1 (1 bit(s))
109 : 0; -- clk3 counter: High Count = 0 (8 bit(s))
110 : 0;
111 : 0;
112 : 0;
113 : 0;
114 : 0;
115 : 0;
116 : 0;
117 : 0; -- clk3 counter: Odd Division = 0 (1 bit(s))
118 : 0; -- clk3 counter: Low Count = 0 (8 bit(s))
119 : 0;
120 : 0;
121 : 0;
122 : 0;
123 : 0;
124 : 0;
125 : 0;
126 : 1; -- clk4 counter: Bypass = 1 (1 bit(s))
127 : 0; -- clk4 counter: High Count = 0 (8 bit(s))
128 : 0;
129 : 0;
130 : 0;
131 : 0;
132 : 0;
133 : 0;
134 : 0;
135 : 0; -- clk4 counter: Odd Division = 0 (1 bit(s))
136 : 0; -- clk4 counter: Low Count = 0 (8 bit(s))
137 : 0;
138 : 0;
139 : 0;
140 : 0;
141 : 0;
142 : 0;
143 : 0;
END;

174
cores/c16/pll_c16_pal.mif Normal file
View File

@@ -0,0 +1,174 @@
-- Copyright (C) 1991-2014 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- MIF file representing initial state of PLL Scan Chain
-- Device Family: Cyclone III
-- Device Part: -
-- Device Speed Grade: 8
-- PLL Scan Chain: Fast PLL (144 bits)
-- File Name: /home/gyurco/git/mist-board/cores/c16/pll_c16_pal.mif
-- Generated: Thu Feb 14 11:25:48 2019
WIDTH=1;
DEPTH=144;
ADDRESS_RADIX=UNS;
DATA_RADIX=UNS;
CONTENT BEGIN
0 : 0; -- Reserved Bits = 0 (1 bit(s))
1 : 0; -- Reserved Bits = 0 (1 bit(s))
2 : 0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0)
3 : 0;
4 : 1; -- Loop Filter Resistance = 20 (5 bit(s)) (Setting 20)
5 : 0;
6 : 1;
7 : 0;
8 : 0;
9 : 0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2)
10 : 0; -- Reserved Bits = 0 (5 bit(s))
11 : 0;
12 : 0;
13 : 0;
14 : 0;
15 : 0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1)
16 : 0;
17 : 1;
18 : 0; -- N counter: Bypass = 0 (1 bit(s))
19 : 0; -- N counter: High Count = 2 (8 bit(s))
20 : 0;
21 : 0;
22 : 0;
23 : 0;
24 : 0;
25 : 1;
26 : 0;
27 : 1; -- N counter: Odd Division = 1 (1 bit(s))
28 : 0; -- N counter: Low Count = 1 (8 bit(s))
29 : 0;
30 : 0;
31 : 0;
32 : 0;
33 : 0;
34 : 0;
35 : 1;
36 : 0; -- M counter: Bypass = 0 (1 bit(s))
37 : 0; -- M counter: High Count = 21 (8 bit(s))
38 : 0;
39 : 0;
40 : 1;
41 : 0;
42 : 1;
43 : 0;
44 : 1;
45 : 1; -- M counter: Odd Division = 1 (1 bit(s))
46 : 0; -- M counter: Low Count = 20 (8 bit(s))
47 : 0;
48 : 0;
49 : 1;
50 : 0;
51 : 1;
52 : 0;
53 : 0;
54 : 0; -- clk0 counter: Bypass = 0 (1 bit(s))
55 : 0; -- clk0 counter: High Count = 7 (8 bit(s))
56 : 0;
57 : 0;
58 : 0;
59 : 0;
60 : 1;
61 : 1;
62 : 1;
63 : 1; -- clk0 counter: Odd Division = 1 (1 bit(s))
64 : 0; -- clk0 counter: Low Count = 6 (8 bit(s))
65 : 0;
66 : 0;
67 : 0;
68 : 0;
69 : 1;
70 : 1;
71 : 0;
72 : 1; -- clk1 counter: Bypass = 1 (1 bit(s))
73 : 0; -- clk1 counter: High Count = 0 (8 bit(s))
74 : 0;
75 : 0;
76 : 0;
77 : 0;
78 : 0;
79 : 0;
80 : 0;
81 : 0; -- clk1 counter: Odd Division = 0 (1 bit(s))
82 : 0; -- clk1 counter: Low Count = 0 (8 bit(s))
83 : 0;
84 : 0;
85 : 0;
86 : 0;
87 : 0;
88 : 0;
89 : 0;
90 : 1; -- clk2 counter: Bypass = 1 (1 bit(s))
91 : 0; -- clk2 counter: High Count = 0 (8 bit(s))
92 : 0;
93 : 0;
94 : 0;
95 : 0;
96 : 0;
97 : 0;
98 : 0;
99 : 0; -- clk2 counter: Odd Division = 0 (1 bit(s))
100 : 0; -- clk2 counter: Low Count = 0 (8 bit(s))
101 : 0;
102 : 0;
103 : 0;
104 : 0;
105 : 0;
106 : 0;
107 : 0;
108 : 1; -- clk3 counter: Bypass = 1 (1 bit(s))
109 : 0; -- clk3 counter: High Count = 0 (8 bit(s))
110 : 0;
111 : 0;
112 : 0;
113 : 0;
114 : 0;
115 : 0;
116 : 0;
117 : 0; -- clk3 counter: Odd Division = 0 (1 bit(s))
118 : 0; -- clk3 counter: Low Count = 0 (8 bit(s))
119 : 0;
120 : 0;
121 : 0;
122 : 0;
123 : 0;
124 : 0;
125 : 0;
126 : 1; -- clk4 counter: Bypass = 1 (1 bit(s))
127 : 0; -- clk4 counter: High Count = 0 (8 bit(s))
128 : 0;
129 : 0;
130 : 0;
131 : 0;
132 : 0;
133 : 0;
134 : 0;
135 : 0; -- clk4 counter: Odd Division = 0 (1 bit(s))
136 : 0; -- clk4 counter: Low Count = 0 (8 bit(s))
137 : 0;
138 : 0;
139 : 0;
140 : 0;
141 : 0;
142 : 0;
143 : 0;
END;

3
cores/c16/pll_reconfig.qip Normal file
View File

@@ -0,0 +1,3 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL_RECONFIG"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_reconfig.v"]

1624
cores/c16/pll_reconfig.v Normal file
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File diff suppressed because it is too large Load Diff

3
cores/c16/rom_reconfig_ntsc.qip Normal file
View File

@@ -0,0 +1,3 @@
set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "rom_reconfig_ntsc.v"]

164
cores/c16/rom_reconfig_ntsc.v Normal file
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@@ -0,0 +1,164 @@
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: rom_reconfig_ntsc.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module rom_reconfig_ntsc (
address,
clock,
rden,
q);
input [7:0] address;
input clock;
input rden;
output [0:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri1 rden;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire0;
wire [0:0] q = sub_wire0[0:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.rden_a (rden),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "pll_c16_ntsc.mif",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 8,
altsyncram_component.width_a = 1,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "pll_c16_ntsc.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
// Retrieval info: PRIVATE: WidthData NUMERIC "1"
// Retrieval info: PRIVATE: rden NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "pll_c16_ntsc.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL "q[0..0]"
// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
// Retrieval info: CONNECT: q 0 0 1 0 @q_a 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_ntsc.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_ntsc.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_ntsc.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_ntsc.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_ntsc_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_ntsc_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf

3
cores/c16/rom_reconfig_pal.qip Normal file
View File

@@ -0,0 +1,3 @@
set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "rom_reconfig_pal.v"]

164
cores/c16/rom_reconfig_pal.v Normal file
View File

@@ -0,0 +1,164 @@
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: rom_reconfig_pal.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module rom_reconfig_pal (
address,
clock,
rden,
q);
input [7:0] address;
input clock;
input rden;
output [0:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri1 rden;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire0;
wire [0:0] q = sub_wire0[0:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.rden_a (rden),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "pll_c16_pal.mif",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 8,
altsyncram_component.width_a = 1,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "pll_c16_pal.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
// Retrieval info: PRIVATE: WidthData NUMERIC "1"
// Retrieval info: PRIVATE: rden NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "pll_c16_pal.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL "q[0..0]"
// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
// Retrieval info: CONNECT: q 0 0 1 0 @q_a 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_pal.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_pal.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_pal.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_pal.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_pal_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_pal_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf

12
cores/c64/C64_mist.qsf
View File

@@ -166,7 +166,7 @@ set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/sid.stp
set_global_assignment -name USE_SIGNALTAP_FILE output_files/pll.stp
# Power Estimation Assignments
# ============================
@@ -320,6 +320,7 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to CONF_DATA0
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF
set_global_assignment -name VERILOG_FILE rtl/sid8580/sid_voice.v
set_global_assignment -name VERILOG_FILE rtl/sid8580/sid_filters.v
set_global_assignment -name VERILOG_FILE rtl/sid8580/sid_envelope.v
@@ -375,6 +376,13 @@ set_global_assignment -name VHDL_FILE rtl/t65/T65_Pack.vhd
set_global_assignment -name VHDL_FILE rtl/t65/T65_MCode.vhd
set_global_assignment -name VHDL_FILE rtl/t65/T65_ALU.vhd
set_global_assignment -name VHDL_FILE rtl/t65/T65.vhd
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF
set_global_assignment -name SIGNALTAP_FILE output_files/sid.stp
set_global_assignment -name QIP_FILE rtl/mist/pll.qip
set_global_assignment -name QIP_FILE rtl/mist/pll_c64.qip
set_global_assignment -name QIP_FILE rtl/mist/pll_c64_reconfig.qip
set_global_assignment -name QIP_FILE rtl/mist/rom_reconfig_pal.qip
set_global_assignment -name QIP_FILE rtl/mist/rom_reconfig_ntsc.qip
set_global_assignment -name SIGNALTAP_FILE output_files/pll.stp
set_location_assignment PIN_46 -to UART_TX
set_location_assignment PIN_31 -to UART_RX
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

12
cores/c64/C64_mist.sdc
View File

@@ -34,6 +34,8 @@ derive_clock_uncertainty
# Clock groups
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll_2|altpll_component|auto_generated|pll1|clk[*]}]
set_clock_groups -asynchronous -group [get_clocks {pll_2|altpll_component|auto_generated|pll1|clk[0]}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
# Some relaxed constrain to the VGA pins. The signals should arrive together, the delay is not really important.
@@ -41,11 +43,11 @@ set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|cl
set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -min -5 [get_ports {VGA_*}]
# SDRAM delays
set_input_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -max 6.4 [get_ports SDRAM_DQ[*]]
set_input_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -min 3.2 [get_ports SDRAM_DQ[*]]
set_input_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -max 6.4 [get_ports SDRAM_DQ[*]]
set_input_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -min 3.2 [get_ports SDRAM_DQ[*]]
set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_multicycle_path -from {video_mixer:vmixer|scandoubler:scandoubler|Hq2x:Hq2x|*} -to {VGA_*[*]} -setup 4
set_multicycle_path -from {video_mixer:vmixer|scandoubler:scandoubler|Hq2x:Hq2x|*} -to {VGA_*[*]} -hold 3
@@ -53,6 +55,8 @@ set_multicycle_path -from {video_mixer:vmixer|scandoubler:scandoubler|Hq2x:Hq2x|
set_multicycle_path -to {VGA_*[*]} -setup 4
set_multicycle_path -to {VGA_*[*]} -hold 3
set_false_path -from [get_ports {UART_RX}]
set_false_path -to [get_ports {UART_TX}]
set_false_path -to [get_ports {AUDIO_L}]
set_false_path -to [get_ports {AUDIO_R}]
set_false_path -to [get_ports {LED}]

5
cores/c64/PLLJ_PLLSPE_INFO.txt
View File

@@ -1,5 +0,0 @@
PLL_Name pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll1
PLLJITTER 25
PLLSPEmax 84
PLLSPEmin -53

77
cores/c64/rtl/fpga64_sid_iec.vhd
View File

@@ -86,9 +86,6 @@ entity fpga64_sid_iec is
-- joystick interface
joyA : in unsigned(6 downto 0);
joyB : in unsigned(6 downto 0);
-- 4 player interface
joyC : in unsigned(6 downto 0);
joyD : in unsigned(6 downto 0);
-- serial port, for connection to pheripherals
serioclk : out std_logic;
@@ -110,6 +107,22 @@ entity fpga64_sid_iec is
iec_atn_o : out std_logic;
-- iec_atn_i : in std_logic;
-- user port
cnt1_in : in std_logic := '1';
cnt1_out : out std_logic;
cnt2_in : in std_logic := '1';
cnt2_out : out std_logic;
sp1_in : in std_logic := '1';
sp1_out : out std_logic;
sp2_in : in std_logic := '1';
sp2_out : out std_logic;
flag2_n : in std_logic := '1';
pc2_n : out std_logic;
pa2_in : in std_logic;
pa2_out : out std_logic;
pb_in : in std_logic_vector(7 downto 0);
pb_out : out std_logic_vector(7 downto 0);
-- CIA
cia_mode : in std_logic;
@@ -204,18 +217,14 @@ architecture rtl of fpga64_sid_iec is
signal theScanCode: unsigned(7 downto 0);
-- I/O
signal cia1_pai: unsigned(7 downto 0);
signal cia1_pao: unsigned(7 downto 0);
signal cia1_pad: unsigned(7 downto 0);
signal cia1_pbi: unsigned(7 downto 0);
signal cia1_pbo: unsigned(7 downto 0);
signal cia1_pbd: unsigned(7 downto 0);
signal cia2_pai: unsigned(7 downto 0);
signal cia2_pao: unsigned(7 downto 0);
signal cia2_pad: unsigned(7 downto 0);
signal cia2_pbi: unsigned(7 downto 0);
signal cia2_pbo: unsigned(7 downto 0);
signal cia2_pbd: unsigned(7 downto 0);
signal cia1_pai: std_logic_vector(7 downto 0);
signal cia1_pao: std_logic_vector(7 downto 0);
signal cia1_pbi: std_logic_vector(7 downto 0);
signal cia1_pbo: std_logic_vector(7 downto 0);
signal cia2_pai: std_logic_vector(7 downto 0);
signal cia2_pao: std_logic_vector(7 downto 0);
signal cia2_pbi: std_logic_vector(7 downto 0);
signal cia2_pbo: std_logic_vector(7 downto 0);
signal debugWE: std_logic := '0';
signal debugData: unsigned(7 downto 0) := (others => '0');
@@ -677,9 +686,11 @@ div1m: process(clk32) -- this process devides 32 MHz to 1MHz (for the SID)
pb_in => std_logic_vector(cia1_pbi),
unsigned(pb_out) => cia1_pbo,
flag_n => '1',
sp_in => '1',
cnt_in => '1',
flag_n => flag2_n,
sp_in => sp1_in,
sp_out => sp1_out,
cnt_in => cnt1_in,
cnt_out => cnt1_out,
pc_n => open,
tod => vicVSync,
@@ -705,11 +716,13 @@ div1m: process(clk32) -- this process devides 32 MHz to 1MHz (for the SID)
pb_in => std_logic_vector(cia2_pbi),
unsigned(pb_out) => cia2_pbo,
flag_n => '1',
sp_in => '1',
cnt_in => '1',
flag_n => flag2_n,
sp_in => sp2_in,
sp_out => sp2_out,
cnt_in => cnt2_in,
cnt_out => cnt2_out,
pc_n => open,
pc_n => pc2_n,
tod => vicVSync,
irq_n => irq_cia2
);
@@ -757,11 +770,11 @@ div1m: process(clk32) -- this process devides 32 MHz to 1MHz (for the SID)
joyA => (not joyA(4 downto 0)),
joyB => (not joyB(4 downto 0)),
pai => cia1_pao,
pbi => cia1_pbo,
pao => cia1_pai,
pbo => cia1_pbi,
pai => unsigned(cia1_pao),
pbi => unsigned(cia1_pbo),
std_logic_vector(pao) => cia1_pai,
std_logic_vector(pbo) => cia1_pbi,
videoKey => videoKey,
traceKey => open,
trace2Key => trace2Key,
@@ -808,7 +821,7 @@ div1m: process(clk32) -- this process devides 32 MHz to 1MHz (for the SID)
iec_data_o <= cia2_pao(5);
iec_clk_o <= cia2_pao(4);
iec_atn_o <= cia2_pao(3);
ramDataOut <= "00" & cia2_pao(5 downto 3) & "000" when sysCycle >= CYCLE_IEC0 and sysCycle <= CYCLE_IEC3 else cpuDo;
ramDataOut <= "00" & unsigned(cia2_pao)(5 downto 3) & "000" when sysCycle >= CYCLE_IEC0 and sysCycle <= CYCLE_IEC3 else cpuDo;
ramAddr <= systemAddr when (phi0_cpu = '1') or (phi0_vic = '1') else (others => '0');
ramWe <= '0' when sysCycle = CYCLE_IEC2 or sysCycle = CYCLE_IEC3 else not systemWe;
ramCE <= '0' when sysCycle /= CYCLE_IDLE0 and sysCycle /= CYCLE_IDLE1 and sysCycle /= CYCLE_IDLE2 and
@@ -884,10 +897,10 @@ div1m: process(clk32) -- this process devides 32 MHz to 1MHz (for the SID)
end process;
cia2_pai(5 downto 0) <= cia2_pao(5 downto 0);
cia2_pbi(7 downto 6) <= cia2_pbo(7 downto 6);
-- Protovision 4 player interface
cia2_pbi(5 downto 0) <= not joyC(5 downto 0) when cia2_pbo(7) = '1' else not joyD(5 downto 0);
cia2_pai(2) <= pa2_in;
pa2_out <= cia2_pao(2);
cia2_pbi <= pb_in;
pb_out <= cia2_pbo;
-- -----------------------------------------------------------------------
-- VIC bank to address lines

240
cores/c64/rtl/mist/c64_mist.vhd
View File

@@ -68,7 +68,10 @@ entity c64_mist is port
SPI_DI : in std_logic;
SPI_SS2 : in std_logic;
SPI_SS3 : in std_logic;
CONF_DATA0 : in std_logic
CONF_DATA0 : in std_logic;
UART_RX : in std_logic;
UART_TX : out std_logic
);
end c64_mist;
@@ -126,14 +129,16 @@ constant CONF_STR : string :=
"S,D64,Mount Disk;"&
"F,PRG,Load File;"&
"F,CRT,Load Cartridge;" &--3
-- "F,TAP,Load File;"&--4
-- "F,T64,Load File;"&--5
"F,ROM,Load Kernal;"&
-- "F,TAP,Load File;"&--5
-- "F,T64,Load File;"&--6
"OG,Disk Write,Enable,Disable;"&
"O2,Video standard,PAL,NTSC;"&
"O8A,Scandoubler Fx,None,HQ2x-320,HQ2x-160,CRT 25%,CRT 50%;"&
"ODF,SID,6581 Mono,6581 Stereo,8580 Mono,8580 Stereo,Pseudo Stereo;"&
"O3,Joysticks,normal,swapped;"&
"O6,Audio filter,On,Off;"&
"O3,Joysticks,normal,swapped;"&
"O7,Userport,4-player IF,UART;"&
"O4,CIA Model,6256,8521;"&
-- "OB,BIOS,C64,C64GS;" &
"T5,Reset & Detach Cartridge;";
@@ -255,9 +260,9 @@ component cartridge port
IOE : in std_logic; -- IOE signal &DE00
IOF : in std_logic; -- IOF signal &DF00
clk32 : in std_logic; -- 32mhz clock source
reset : in std_logic; -- reset signal
reset_out : out std_logic; -- reset signal
clk32 : in std_logic; -- 32mhz clock source
reset : in std_logic; -- reset signal
reset_out : out std_logic; -- reset signal
cart_id : in std_logic_vector(15 downto 0); -- cart ID or cart type
cart_exrom : in std_logic_vector(7 downto 0); -- CRT file EXROM status
@@ -289,8 +294,27 @@ component cartridge port
end component cartridge;
signal pll_locked_in: std_logic_vector(1 downto 0);
signal pll_locked: std_logic;
signal pll_locked_in : std_logic_vector(1 downto 0);
signal pll_locked : std_logic;
signal pll_areset : std_logic;
signal pll_scanclk : std_logic;
signal pll_scandata : std_logic;
signal pll_scanclkena : std_logic;
signal pll_configupdate : std_logic;
signal pll_scandataout : std_logic;
signal pll_scandone : std_logic;
signal pll_rom_address : std_logic_vector(7 downto 0);
signal pll_write_rom_ena : std_logic;
signal pll_write_from_rom : std_logic;
signal pll_reconfig : std_logic;
signal pll_reconfig_busy : std_logic;
signal pll_reconfig_reset : std_logic;
signal pll_reconfig_state : std_logic_vector(1 downto 0) := "00";
signal pll_reconfig_timeout : integer;
signal q_reconfig_pal : std_logic_vector(0 downto 0);
signal q_reconfig_ntsc : std_logic_vector(0 downto 0);
signal pll_rom_q : std_logic;
signal c1541_reset: std_logic;
signal idle: std_logic;
signal ces: std_logic_vector(3 downto 0);
@@ -349,6 +373,7 @@ end component cartridge;
signal c1541rom_wr : std_logic;
signal c64rom_wr : std_logic;
signal c64rom_addr : std_logic_vector(13 downto 0);
signal joyA : std_logic_vector(31 downto 0);
signal joyB : std_logic_vector(31 downto 0);
@@ -405,18 +430,27 @@ end component cartridge;
signal c1541_iec_data_i : std_logic;
signal c1541_iec_clk_i : std_logic;
signal pa2_in : std_logic;
signal pa2_out : std_logic;
signal pb_in : std_logic_vector(7 downto 0);
signal pb_out : std_logic_vector(7 downto 0);
signal flag2_n : std_logic;
signal tv15Khz_mode : std_logic;
signal ypbpr : std_logic;
signal ntsc_init_mode : std_logic;
signal ntsc_init_mode : std_logic := '0';
signal ntsc_init_mode_d: std_logic;
signal ntsc_init_mode_d2: std_logic;
signal ntsc_init_mode_d3: std_logic;
alias c64_addr_int : unsigned is unsigned(c64_addr);
alias c64_data_in_int : unsigned is unsigned(c64_data_in);
signal c64_data_in16: std_logic_vector(15 downto 0);
alias c64_data_out_int : unsigned is unsigned(c64_data_out);
signal clk_ram : std_logic;
signal clk32 : std_logic;
signal clk16 : std_logic;
signal c64_clk : std_logic; -- 31.527mhz (PAL), 32.727mhz(NTSC) clock source
signal clk_ram : std_logic; -- 2 x c64_clk
signal clk32 : std_logic; -- 32mhz
signal ce_8 : std_logic;
signal ce_4 : std_logic;
signal hq2x160 : std_logic;
@@ -465,7 +499,7 @@ begin
user_io_d : user_io
generic map (STRLEN => CONF_STR'length)
port map (
clk_sys => clk32,
clk_sys => c64_clk,
clk_sd => clk32,
SPI_CLK => SPI_SCK,
@@ -503,7 +537,7 @@ begin
data_io_d: data_io
port map (
clk_sys => clk32,
clk_sys => c64_clk,
SPI_SCK => SPI_SCK,
SPI_SS2 => SPI_SS2,
SPI_DI => SPI_DI,
@@ -530,7 +564,7 @@ begin
mem_ce => not ram_ce,
mem_ce_out => mem_ce,
clk32 => clk32,
clk32 => c64_clk,
reset => reset_n,
reset_out => reset_crt,
@@ -579,9 +613,9 @@ begin
sdram_ce <= mem_ce when iec_cycle='0' else ioctl_iec_cycle_used;
sdram_we <= not ram_we when iec_cycle='0' else ioctl_iec_cycle_used;
process(clk32)
process(c64_clk)
begin
if falling_edge(clk32) then
if falling_edge(c64_clk) then
old_download <= ioctl_download;
iec_cycleD <= iec_cycle;
@@ -655,7 +689,7 @@ begin
end if;
end if;
if ioctl_index = 4 then
if ioctl_index = 5 then
if ioctl_addr = 0 then
ioctl_load_addr <= '0' & X"200000";
ioctl_ram_data <= ioctl_data;
@@ -694,13 +728,13 @@ begin
end if;
end process;
c64rom_wr <= ioctl_wr when (ioctl_index = 0) and (ioctl_addr(14) = '0') and (ioctl_download = '1') else '0';
c64rom_wr <= ioctl_wr when (((ioctl_index = 0) and (ioctl_addr(14) = '0')) or (ioctl_index = 4)) and (ioctl_download = '1') else '0';
c64rom_addr <= ioctl_addr(13 downto 0) when ioctl_index = 0 else '1' & ioctl_addr(12 downto 0);
c1541rom_wr <= ioctl_wr when (ioctl_index = 0) and (ioctl_addr(14) = '1') and (ioctl_download = '1') else '0';
process(clk32)
process(c64_clk)
begin
if rising_edge(clk32) then
clk16 <= not clk16;
if rising_edge(c64_clk) then
clkdiv <= std_logic_vector(unsigned(clkdiv)+1);
if(clkdiv(1 downto 0) = "00") then
ce_8 <= '1';
@@ -717,25 +751,121 @@ begin
ntsc_init_mode <= status(2);
-- second to generate 64mhz clock and phase shifted ram clock
pll : entity work.pll
pll_rom_pal : entity work.rom_reconfig_pal
port map(
inclk0 => CLOCK_27,
c0 => clk_ram,
c1 => SDRAM_CLK,
c2 => clk32,
locked => pll_locked
address => pll_rom_address,
clock => clk32,
rden => pll_write_rom_ena,
q => q_reconfig_pal
);
pll_rom_ntsc : entity work.rom_reconfig_ntsc
port map(
address => pll_rom_address,
clock => clk32,
rden => pll_write_rom_ena,
q => q_reconfig_ntsc
);
pll_rom_q <= q_reconfig_pal(0) when ntsc_init_mode_d2 = '0' else q_reconfig_ntsc(0);
pll_c64_reconfig : entity work.pll_c64_reconfig
port map (
busy => pll_reconfig_busy,
clock => clk32,
counter_param => (others => '0'),
counter_type => (others => '0'),
data_in => (others => '0'),
pll_areset => pll_areset,
pll_areset_in => '0',
pll_configupdate => pll_configupdate,
pll_scanclk => pll_scanclk,
pll_scanclkena => pll_scanclkena,
pll_scandata => pll_scandata,
pll_scandataout => pll_scandataout,
pll_scandone => pll_scandone,
read_param => '0',
reconfig => pll_reconfig,
reset => pll_reconfig_reset,
reset_rom_address => '0',
rom_address_out => pll_rom_address,
rom_data_in => pll_rom_q,
write_from_rom => pll_write_from_rom,
write_param => '0',
write_rom_ena => pll_write_rom_ena
);
process(clk32)
begin
if rising_edge(clk32) then
ntsc_init_mode_d <= ntsc_init_mode;
ntsc_init_mode_d2 <= ntsc_init_mode_d;
pll_write_from_rom <= '0';
pll_reconfig <= '0';
pll_reconfig_reset <= '0';
case pll_reconfig_state is
when "00" =>
ntsc_init_mode_d3 <= ntsc_init_mode_d2;
if ntsc_init_mode_d3 /= ntsc_init_mode_d2 then
pll_write_from_rom <= '1';
pll_reconfig_state <= "01";
end if;
when "01" =>
pll_reconfig_state <= "10";
when "10" =>
if pll_reconfig_busy = '0' then
pll_reconfig <= '1';
pll_reconfig_state <= "11";
pll_reconfig_timeout <= 1000;
end if;
when "11" =>
pll_reconfig_timeout <= pll_reconfig_timeout - 1;
if pll_reconfig_timeout = 1 then
pll_reconfig_reset <= '1'; -- sometimes pll reconfig stuck in busy state
pll_reconfig_state <= "00";
end if;
if pll_reconfig = '0' and pll_reconfig_busy = '0' then
pll_reconfig_state <= "00";
end if;
when others => null;
end case;
end if;
end process;
-- clock for C64 and SDRAM
pll : entity work.pll_c64
port map(
inclk0 => CLOCK_27,
c0 => c64_clk,
c1 => clk_ram,
areset => pll_areset,
scanclk => pll_scanclk,
scandata => pll_scandata,
scanclkena => pll_scanclkena,
configupdate => pll_configupdate,
scandataout => pll_scandataout,
scandone => pll_scandone
);
SDRAM_CLK <= not clk_ram;
-- clock for 1541
pll_2 : entity work.pll
port map(
inclk0 => CLOCK_27,
c0 => clk32,
locked => pll_locked
);
process(c64_clk)
begin
if rising_edge(c64_clk) then
-- Reset by:
-- Button at device, IO controller reboot, OSD or FPGA startup
if status(0)='1' or pll_locked = '0' then
reset_counter <= 1000000;
reset_n <= '0';
elsif buttons(1)='1' or status(5)='1' or reset_key = '1' or reset_crt='1' or (ioctl_download='1' and ioctl_index = 3) then
elsif buttons(1)='1' or status(5)='1' or reset_key = '1' or reset_crt='1' or
(ioctl_download='1' and (ioctl_index = 3 or ioctl_index = 4)) then
reset_counter <= 255;
reset_n <= '0';
elsif ioctl_download ='1' then
@@ -783,7 +913,7 @@ begin
dac : sigma_delta_dac
port map (
clk => clk32,
clk => c64_clk,
ldatasum => audio_data_l(17 downto 3),
rdatasum => audio_data_r(17 downto 3),
aleft => AUDIO_L,
@@ -793,7 +923,7 @@ begin
fpga64 : entity work.fpga64_sid_iec
port map(
clk32 => clk32,
clk32 => c64_clk,
reset_n => reset_n,
c64gs => status(11),-- not enough BRAM
kbd_clk => not ps2_clk,
@@ -828,8 +958,6 @@ begin
ba => open,
joyA => unsigned(joyA_c64),
joyB => unsigned(joyB_c64),
joyC => unsigned(joyC_c64),
joyD => unsigned(joyD_c64),
serioclk => open,
ces => ces,
SIDclk => open,
@@ -845,15 +973,43 @@ begin
iec_data_i => c64_iec_data_i,
iec_clk_i => c64_iec_clk_i,
-- iec_atn_i => not c64_iec_atn_i,
pa2_in => pa2_in,
pa2_out => pa2_out,
pb_in => pb_in,
pb_out => pb_out,
flag2_n => flag2_n,
cia_mode => status(4),
disk_num => open,
c64rom_addr => ioctl_addr(13 downto 0),
c64rom_addr => c64rom_addr,
c64rom_data => ioctl_data,
c64rom_wr => c64rom_wr,
-- cart_detach_key => cart_detach_key,
reset_key => reset_key
);
-- connect user port
process (pa2_out, pb_out, joyC_c64, joyD_c64, UART_RX, status)
begin
pa2_in <= pa2_out;
if status(7) = '0' then
-- Protovision 4 player interface
flag2_n <= '1';
UART_TX <= '0';
pb_in(7 downto 6) <= pb_out(7 downto 6);
if pb_out(7) = '1' then
pb_in(5 downto 0) <= not joyC_c64(5 downto 0);
else
pb_in(5 downto 0) <= not joyD_c64(5 downto 0);
end if;
else
-- UART
pb_in(7 downto 1) <= pb_out(7 downto 1);
flag2_n <= UART_RX;
pb_in(0) <= UART_RX;
UART_TX <= pa2_out;
end if;
end process;
disk_readonly <= status(16);
c64_iec_data_i <= c1541_iec_data_o;
@@ -863,12 +1019,12 @@ begin
c1541_iec_data_i <= c64_iec_data_o;
c1541_iec_clk_i <= c64_iec_clk_o;
process(clk32, reset_n)
process(c64_clk, reset_n)
variable reset_cnt : integer range 0 to 32000000;
begin
if reset_n = '0' then
reset_cnt := 100000;
elsif rising_edge(clk32) then
elsif rising_edge(c64_clk) then
if reset_cnt /= 0 then
reset_cnt := reset_cnt - 1;
end if;
@@ -887,7 +1043,7 @@ begin
clk32 => clk32,
reset => c1541_reset,
c1541rom_clk => clk32,
c1541rom_clk => c64_clk,
c1541rom_addr => ioctl_addr(13 downto 0),
c1541rom_data => ioctl_data,
c1541rom_wr => c1541rom_wr,
@@ -918,7 +1074,7 @@ begin
comp_sync : entity work.composite_sync
port map(
clk32 => clk32,
clk32 => c64_clk,
hsync => hsync,
vsync => vsync,
ntsc => ntsc_init_mode,
@@ -935,9 +1091,9 @@ begin
hq2x <= status(9) xor status(8);
ce_pix_actual <= ce_4 when hq2x160='1' else ce_8;
process(clk32)
process(c64_clk)
begin
if rising_edge(clk32) then
if rising_edge(c64_clk) then
if((old_vsync = '0') and (vsync_out = '1')) then
if(status(10 downto 8)="010") then
hq2x160 <= '1';

10
cores/c64/rtl/mist/pll.ppf Normal file
View File

@@ -0,0 +1,10 @@
<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone III" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
<global>
<pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="c0" direction="output" scope="external" source="clock" />
<pin name="locked" direction="output" scope="external" />
</global>
</pinplan>

4
cores/c64/rtl/mist/pll.qip Normal file
View File

@@ -0,0 +1,4 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]

102
cores/c64/rtl/mist/pll.vhd
View File

@@ -14,7 +14,7 @@
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.4 Build 182 03/12/2014 SJ Full Version
-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
-- ************************************************************
@@ -44,8 +44,6 @@ ENTITY pll IS
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll;
@@ -57,11 +55,9 @@ ARCHITECTURE SYN OF pll IS
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
@@ -72,14 +68,6 @@ ARCHITECTURE SYN OF pll IS
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
@@ -138,33 +126,21 @@ ARCHITECTURE SYN OF pll IS
END COMPONENT;
BEGIN
sub_wire7_bv(0 DOWNTO 0) <= "0";
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
sub_wire4 <= sub_wire0(2);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
c2 <= sub_wire4;
sub_wire5 <= inclk0;
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 27,
clk0_duty_cycle => 50,
clk0_multiply_by => 64,
clk0_multiply_by => 32,
clk0_phase_shift => "0",
clk1_divide_by => 27,
clk1_duty_cycle => 50,
clk1_multiply_by => 64,
clk1_phase_shift => "-2604",
clk2_divide_by => 27,
clk2_duty_cycle => 50,
clk2_multiply_by => 32,
clk2_phase_shift => "0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=pll",
@@ -197,8 +173,8 @@ BEGIN
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
@@ -216,7 +192,7 @@ BEGIN
width_clock => 5
)
PORT MAP (
inclk => sub_wire6,
inclk => sub_wire4,
clk => sub_wire0,
locked => sub_wire2
);
@@ -245,14 +221,8 @@ END SYN;
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "64.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "64.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "32.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "32.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -273,34 +243,18 @@ END SYN;
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "48"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "7"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "64.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "64.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "32.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "32.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-60.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -323,33 +277,19 @@ END SYN;
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "64"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "32"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "64"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-2604"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "27"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "32"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
@@ -381,8 +321,8 @@ END SYN;
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
@@ -401,15 +341,11 @@ END SYN;
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE

18
cores/c64/rtl/mist/pll_c64.ppf Normal file
View File

@@ -0,0 +1,18 @@
<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone III" variation_name="pll_c64" megafunction_name="ALTPLL" specifies="all_ports">
<global>
<pin name="areset" direction="input" scope="external" />
<pin name="configupdate" direction="input" scope="external" />
<pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="scanclk" direction="input" scope="external" source="clock" />
<pin name="scanclkena" direction="input" scope="external" />
<pin name="scandata" direction="input" scope="external" />
<pin name="c0" direction="output" scope="external" source="clock" />
<pin name="c1" direction="output" scope="external" source="clock" />
<pin name="locked" direction="output" scope="external" />
<pin name="scandataout" direction="output" scope="external" />
<pin name="scandone" direction="output" scope="external" />
</global>
</pinplan>

4
cores/c64/rtl/mist/pll_c64.qip Normal file
View File

@@ -0,0 +1,4 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_c64.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_c64.ppf"]

436
cores/c64/rtl/mist/pll_c64.vhd Normal file
View File

@@ -0,0 +1,436 @@
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll_c64.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll_c64 IS
PORT
(
areset : IN STD_LOGIC := '0';
configupdate : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
scanclk : IN STD_LOGIC := '1';
scanclkena : IN STD_LOGIC := '0';
scandata : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC ;
scandataout : OUT STD_LOGIC ;
scandone : OUT STD_LOGIC
);
END pll_c64;
ARCHITECTURE SYN OF pll_c64 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL;
scan_chain_mif_file : STRING
);
PORT (
areset : IN STD_LOGIC ;
configupdate : IN STD_LOGIC ;
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
scanclk : IN STD_LOGIC ;
scanclkena : IN STD_LOGIC ;
scandata : IN STD_LOGIC ;
scandataout : OUT STD_LOGIC ;
scandone : OUT STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire8_bv(0 DOWNTO 0) <= "0";
sub_wire8 <= To_stdlogicvector(sub_wire8_bv);
sub_wire2 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
c0 <= sub_wire2;
scandataout <= sub_wire3;
scandone <= sub_wire4;
locked <= sub_wire5;
sub_wire6 <= inclk0;
sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 6,
clk0_duty_cycle => 50,
clk0_multiply_by => 7,
clk0_phase_shift => "0",
clk1_divide_by => 3,
clk1_duty_cycle => 50,
clk1_multiply_by => 7,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=pll_c64",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_USED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_USED",
port_scanclkena => "PORT_USED",
port_scandata => "PORT_USED",
port_scandataout => "PORT_USED",
port_scandone => "PORT_USED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "ON",
width_clock => 5,
scan_chain_mif_file => "pll_c64_pal.mif"
)
PORT MAP (
areset => areset,
configupdate => configupdate,
inclk => sub_wire7,
scanclk => scanclk,
scanclkena => scanclkena,
scandata => scandata,
clk => sub_wire0,
scandataout => sub_wire3,
scandone => sub_wire4,
locked => sub_wire5
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "6"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "31.500000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "63.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "7"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "7"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "31.52000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "63.04000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_c64_pal.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "1"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "6"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "7"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "7"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: CONSTANT: scan_chain_mif_file STRING "pll_c64_pal.mif"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: configupdate 0 0 0 0 INPUT GND "configupdate"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk"
-- Retrieval info: USED_PORT: scanclkena 0 0 0 0 INPUT GND "scanclkena"
-- Retrieval info: USED_PORT: scandata 0 0 0 0 INPUT GND "scandata"
-- Retrieval info: USED_PORT: scandataout 0 0 0 0 OUTPUT VCC "scandataout"
-- Retrieval info: USED_PORT: scandone 0 0 0 0 OUTPUT VCC "scandone"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
-- Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0
-- Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0
-- Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_c64.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_c64.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_c64.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_c64.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_c64.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_c64_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_c64_pal.mif TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_c64_ntsc.mif TRUE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON

174
cores/c64/rtl/mist/pll_c64_ntsc.mif Normal file
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-- Copyright (C) 1991-2014 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- MIF file representing initial state of PLL Scan Chain
-- Device Family: Cyclone III
-- Device Part: -
-- Device Speed Grade: 8
-- PLL Scan Chain: Fast PLL (144 bits)
-- File Name: /home/gyuri/git/mist-board/cores/c64/rtl/mist/pll_c64_ntsc.mif
-- Generated: Sun Feb 10 18:12:08 2019
WIDTH=1;
DEPTH=144;
ADDRESS_RADIX=UNS;
DATA_RADIX=UNS;
CONTENT BEGIN
0 : 0; -- Reserved Bits = 0 (1 bit(s))
1 : 0; -- Reserved Bits = 0 (1 bit(s))
2 : 0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0)
3 : 0;
4 : 0; -- Loop Filter Resistance = 8 (5 bit(s)) (Setting 8)
5 : 1;
6 : 0;
7 : 0;
8 : 0;
9 : 0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2)
10 : 0; -- Reserved Bits = 0 (5 bit(s))
11 : 0;
12 : 0;
13 : 0;
14 : 0;
15 : 0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1)
16 : 0;
17 : 1;
18 : 0; -- N counter: Bypass = 0 (1 bit(s))
19 : 0; -- N counter: High Count = 3 (8 bit(s))
20 : 0;
21 : 0;
22 : 0;
23 : 0;
24 : 0;
25 : 1;
26 : 1;
27 : 1; -- N counter: Odd Division = 1 (1 bit(s))
28 : 0; -- N counter: Low Count = 2 (8 bit(s))
29 : 0;
30 : 0;
31 : 0;
32 : 0;
33 : 0;
34 : 1;
35 : 0;
36 : 0; -- M counter: Bypass = 0 (1 bit(s))
37 : 0; -- M counter: High Count = 49 (8 bit(s))
38 : 0;
39 : 1;
40 : 1;
41 : 0;
42 : 0;
43 : 0;
44 : 1;
45 : 1; -- M counter: Odd Division = 1 (1 bit(s))
46 : 0; -- M counter: Low Count = 48 (8 bit(s))
47 : 0;
48 : 1;
49 : 1;
50 : 0;
51 : 0;
52 : 0;
53 : 0;
54 : 0; -- clk0 counter: Bypass = 0 (1 bit(s))
55 : 0; -- clk0 counter: High Count = 8 (8 bit(s))
56 : 0;
57 : 0;
58 : 0;
59 : 1;
60 : 0;
61 : 0;
62 : 0;
63 : 0; -- clk0 counter: Odd Division = 0 (1 bit(s))
64 : 0; -- clk0 counter: Low Count = 8 (8 bit(s))
65 : 0;
66 : 0;
67 : 0;
68 : 1;
69 : 0;
70 : 0;
71 : 0;
72 : 0; -- clk1 counter: Bypass = 0 (1 bit(s))
73 : 0; -- clk1 counter: High Count = 4 (8 bit(s))
74 : 0;
75 : 0;
76 : 0;
77 : 0;
78 : 1;
79 : 0;
80 : 0;
81 : 0; -- clk1 counter: Odd Division = 0 (1 bit(s))
82 : 0; -- clk1 counter: Low Count = 4 (8 bit(s))
83 : 0;
84 : 0;
85 : 0;
86 : 0;
87 : 1;
88 : 0;
89 : 0;
90 : 1; -- clk2 counter: Bypass = 1 (1 bit(s))
91 : 0; -- clk2 counter: High Count = 0 (8 bit(s))
92 : 0;
93 : 0;
94 : 0;
95 : 0;
96 : 0;
97 : 0;
98 : 0;
99 : 0; -- clk2 counter: Odd Division = 0 (1 bit(s))
100 : 0; -- clk2 counter: Low Count = 0 (8 bit(s))
101 : 0;
102 : 0;
103 : 0;
104 : 0;
105 : 0;
106 : 0;
107 : 0;
108 : 1; -- clk3 counter: Bypass = 1 (1 bit(s))
109 : 0; -- clk3 counter: High Count = 0 (8 bit(s))
110 : 0;
111 : 0;
112 : 0;
113 : 0;
114 : 0;
115 : 0;
116 : 0;
117 : 0; -- clk3 counter: Odd Division = 0 (1 bit(s))
118 : 0; -- clk3 counter: Low Count = 0 (8 bit(s))
119 : 0;
120 : 0;
121 : 0;
122 : 0;
123 : 0;
124 : 0;
125 : 0;
126 : 1; -- clk4 counter: Bypass = 1 (1 bit(s))
127 : 0; -- clk4 counter: High Count = 0 (8 bit(s))
128 : 0;
129 : 0;
130 : 0;
131 : 0;
132 : 0;
133 : 0;
134 : 0;
135 : 0; -- clk4 counter: Odd Division = 0 (1 bit(s))
136 : 0; -- clk4 counter: Low Count = 0 (8 bit(s))
137 : 0;
138 : 0;
139 : 0;
140 : 0;
141 : 0;
142 : 0;
143 : 0;
END;

174
cores/c64/rtl/mist/pll_c64_pal.mif Normal file
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@@ -0,0 +1,174 @@
-- Copyright (C) 1991-2014 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- MIF file representing initial state of PLL Scan Chain
-- Device Family: Cyclone III
-- Device Part: -
-- Device Speed Grade: 8
-- PLL Scan Chain: Fast PLL (144 bits)
-- File Name: /home/gyuri/git/mist-board/cores/c64/rtl/mist/pll_c64_pal.mif
-- Generated: Sun Feb 10 22:52:34 2019
WIDTH=1;
DEPTH=144;
ADDRESS_RADIX=UNS;
DATA_RADIX=UNS;
CONTENT BEGIN
0 : 0; -- Reserved Bits = 0 (1 bit(s))
1 : 0; -- Reserved Bits = 0 (1 bit(s))
2 : 0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0)
3 : 0;
4 : 1; -- Loop Filter Resistance = 24 (5 bit(s)) (Setting 24)
5 : 1;
6 : 0;
7 : 0;
8 : 0;
9 : 0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2)
10 : 0; -- Reserved Bits = 0 (5 bit(s))
11 : 0;
12 : 0;
13 : 0;
14 : 0;
15 : 0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1)
16 : 0;
17 : 1;
18 : 1; -- N counter: Bypass = 1 (1 bit(s))
19 : 0; -- N counter: High Count = 0 (8 bit(s))
20 : 0;
21 : 0;
22 : 0;
23 : 0;
24 : 0;
25 : 0;
26 : 0;
27 : 0; -- N counter: Odd Division = 0 (1 bit(s))
28 : 0; -- N counter: Low Count = 0 (8 bit(s))
29 : 0;
30 : 0;
31 : 0;
32 : 0;
33 : 0;
34 : 0;
35 : 0;
36 : 0; -- M counter: Bypass = 0 (1 bit(s))
37 : 0; -- M counter: High Count = 11 (8 bit(s))
38 : 0;
39 : 0;
40 : 0;
41 : 1;
42 : 0;
43 : 1;
44 : 1;
45 : 1; -- M counter: Odd Division = 1 (1 bit(s))
46 : 0; -- M counter: Low Count = 10 (8 bit(s))
47 : 0;
48 : 0;
49 : 0;
50 : 1;
51 : 0;
52 : 1;
53 : 0;
54 : 0; -- clk0 counter: Bypass = 0 (1 bit(s))
55 : 0; -- clk0 counter: High Count = 9 (8 bit(s))
56 : 0;
57 : 0;
58 : 0;
59 : 1;
60 : 0;
61 : 0;
62 : 1;
63 : 0; -- clk0 counter: Odd Division = 0 (1 bit(s))
64 : 0; -- clk0 counter: Low Count = 9 (8 bit(s))
65 : 0;
66 : 0;
67 : 0;
68 : 1;
69 : 0;
70 : 0;
71 : 1;
72 : 0; -- clk1 counter: Bypass = 0 (1 bit(s))
73 : 0; -- clk1 counter: High Count = 5 (8 bit(s))
74 : 0;
75 : 0;
76 : 0;
77 : 0;
78 : 1;
79 : 0;
80 : 1;
81 : 1; -- clk1 counter: Odd Division = 1 (1 bit(s))
82 : 0; -- clk1 counter: Low Count = 4 (8 bit(s))
83 : 0;
84 : 0;
85 : 0;
86 : 0;
87 : 1;
88 : 0;
89 : 0;
90 : 1; -- clk2 counter: Bypass = 1 (1 bit(s))
91 : 0; -- clk2 counter: High Count = 0 (8 bit(s))
92 : 0;
93 : 0;
94 : 0;
95 : 0;
96 : 0;
97 : 0;
98 : 0;
99 : 0; -- clk2 counter: Odd Division = 0 (1 bit(s))
100 : 0; -- clk2 counter: Low Count = 0 (8 bit(s))
101 : 0;
102 : 0;
103 : 0;
104 : 0;
105 : 0;
106 : 0;
107 : 0;
108 : 1; -- clk3 counter: Bypass = 1 (1 bit(s))
109 : 0; -- clk3 counter: High Count = 0 (8 bit(s))
110 : 0;
111 : 0;
112 : 0;
113 : 0;
114 : 0;
115 : 0;
116 : 0;
117 : 0; -- clk3 counter: Odd Division = 0 (1 bit(s))
118 : 0; -- clk3 counter: Low Count = 0 (8 bit(s))
119 : 0;
120 : 0;
121 : 0;
122 : 0;
123 : 0;
124 : 0;
125 : 0;
126 : 1; -- clk4 counter: Bypass = 1 (1 bit(s))
127 : 0; -- clk4 counter: High Count = 0 (8 bit(s))
128 : 0;
129 : 0;
130 : 0;
131 : 0;
132 : 0;
133 : 0;
134 : 0;
135 : 0; -- clk4 counter: Odd Division = 0 (1 bit(s))
136 : 0; -- clk4 counter: Low Count = 0 (8 bit(s))
137 : 0;
138 : 0;
139 : 0;
140 : 0;
141 : 0;
142 : 0;
143 : 0;
END;

3
cores/c64/rtl/mist/pll_c64_reconfig.qip Normal file
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@@ -0,0 +1,3 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL_RECONFIG"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_c64_reconfig.vhd"]

2472
cores/c64/rtl/mist/pll_c64_reconfig.vhd Normal file
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File diff suppressed because it is too large Load Diff

3
cores/c64/rtl/mist/rom_reconfig_ntsc.qip Normal file
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@@ -0,0 +1,3 @@
set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "rom_reconfig_ntsc.vhd"]

147
cores/c64/rtl/mist/rom_reconfig_ntsc.vhd Normal file
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-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: rom_reconfig_ntsc.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY rom_reconfig_ntsc IS
PORT
(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC := '1';
rden : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END rom_reconfig_ntsc;
ARCHITECTURE SYN OF rom_reconfig_ntsc IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
q <= sub_wire0(0 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "pll_c64_ntsc.mif",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 256,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
widthad_a => 8,
width_a => 1,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
rden_a => rden,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "pll_c64_ntsc.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
-- Retrieval info: PRIVATE: WidthData NUMERIC "1"
-- Retrieval info: PRIVATE: rden NUMERIC "1"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "pll_c64_ntsc.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL "q[0..0]"
-- Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 1 0 @q_a 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_ntsc.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_ntsc.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_ntsc.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_ntsc.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_ntsc_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf

3
cores/c64/rtl/mist/rom_reconfig_pal.qip Normal file
View File

@@ -0,0 +1,3 @@
set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "rom_reconfig_pal.vhd"]

147
cores/c64/rtl/mist/rom_reconfig_pal.vhd Normal file
View File

@@ -0,0 +1,147 @@
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: rom_reconfig_pal.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY rom_reconfig_pal IS
PORT
(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC := '1';
rden : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END rom_reconfig_pal;
ARCHITECTURE SYN OF rom_reconfig_pal IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
q <= sub_wire0(0 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "pll_c64_pal.mif",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 256,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
widthad_a => 8,
width_a => 1,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
rden_a => rden,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "pll_c64_pal.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
-- Retrieval info: PRIVATE: WidthData NUMERIC "1"
-- Retrieval info: PRIVATE: rden NUMERIC "1"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "pll_c64_pal.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL "q[0..0]"
-- Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 1 0 @q_a 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_pal.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_pal.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_pal.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_pal.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_pal_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf

14
cores/c64/rtl/mos6526.v
View File

@@ -1,8 +1,7 @@
// MOS6526
// by Rayne
// Timers & Interrupts are rewritten by slingshot
// Passes all CIA Timer tests
// TODO: check if Flag and Serial port interrupts are still working
// Passes all Lorenz CIA Timer tests
module mos6526 (
input wire mode, // 0 - 6526 "old", 1 - 8521 "new"
@@ -153,9 +152,14 @@ end
// FLAG Input
always @(posedge clk) begin
if (!res_n || int_reset) icr[4] <= 1'b0;
else if (!flag_n && flag_n_prev) icr[4] <= 1'b1;
if (phi2_p) flag_n_prev <= flag_n;
if (!res_n) icr[4] <= 1'b0;
else begin
if (!flag_n && flag_n_prev) icr[4] <= 1'b1;
if (phi2_p) begin
flag_n_prev <= flag_n;
if (int_reset) icr[4] <= 1'b0;
end
end
end
// Port Control Output