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Merge pull request #128 from gyurco/archie

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Archie IDE support
This commit is contained in:
gyurco
2019-11-02 19:46:52 +01:00
committed by GitHub
parent e74aa72ffa 42a828913f
commit a4e82ddd83
8 changed files with 1275 additions and 56 deletions
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17
cores/archie/fpga/mist/archimedes_mist_top.qsf
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@@ -47,8 +47,8 @@ set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
@@ -136,7 +136,7 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_*
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/vidc.stp
set_global_assignment -name USE_SIGNALTAP_FILE output_files/ide.stp
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
@@ -177,8 +177,9 @@ set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[*]
set_global_assignment -name SEED 1
set_global_assignment -name ENABLE_DRC_SETTINGS OFF
set_location_assignment PLL_1 -to CLOCKS|altpll_component|auto_generated|pll1
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
set_global_assignment -name VERILOG_FILE archimedes_mist_top.v
set_global_assignment -name SYSTEMVERILOG_FILE rgb2ypbpr.sv
set_global_assignment -name VERILOG_FILE scandoubler.v
@@ -190,9 +191,10 @@ set_global_assignment -name VERILOG_FILE osd.v
set_global_assignment -name VERILOG_FILE sram_line_en.v
set_global_assignment -name VERILOG_FILE sram_byte_en.v
set_global_assignment -name QIP_FILE clockgen.qip
set_global_assignment -name VERILOG_FILE ../../rtl/fdc1772.v
set_global_assignment -name VERILOG_FILE ../../rtl/latches.v
set_global_assignment -name VERILOG_FILE ../../rtl/fdc1772.v
set_global_assignment -name VERILOG_FILE ../../rtl/floppy.v
set_global_assignment -name SYSTEMVERILOG_FILE ../../rtl/ide.sv
set_global_assignment -name VERILOG_FILE ../../rtl/podules.v
set_global_assignment -name VERILOG_FILE ../../rtl/i2cslave/serialInterface.v
set_global_assignment -name VERILOG_FILE ../../rtl/i2cslave/registerInterface.v
@@ -228,4 +230,5 @@ set_global_assignment -name QIP_FILE pll_reconfig.qip
set_global_assignment -name QIP_FILE rom_reconfig_36.qip
set_global_assignment -name QIP_FILE pll_vidc.qip
set_global_assignment -name SIGNALTAP_FILE output_files/vidc.stp
set_global_assignment -name SIGNALTAP_FILE output_files/sd.stp
set_global_assignment -name SIGNALTAP_FILE output_files/sd.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

65
cores/archie/fpga/mist/archimedes_mist_top.v
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@@ -56,6 +56,7 @@ module archimedes_mist_top(
input SPI_SCK,
input SPI_SS2, // data_io
input SPI_SS3, // OSD
input SPI_SS4, // Direct SD
input CONF_DATA0 // SPI_SS for user_io
);
@@ -340,7 +341,8 @@ wire [8:0] sd_buff_addr;
wire [1:0] img_mounted;
wire [31:0] img_size;
assign SPI_DO = (CONF_DATA0==0)?user_io_sdo:1'bZ;
// de-multiplex spi outputs from user_io and data_io
assign SPI_DO = (CONF_DATA0==0)?user_io_sdo:(SPI_SS2==0)?data_io_sdo:1'bZ;
wire user_io_sdo;
user_io user_io(
@@ -380,14 +382,34 @@ user_io user_io(
.img_size ( img_size )
);
wire spi_din = SPI_SS4 ? SPI_DI : SPI_DO;
wire data_io_sdo;
data_io # ( .START_ADDR(24'h40_0000) )
DATA_IO (
.sck ( SPI_SCK ),
.ss ( SPI_SS2 ),
.sdi ( SPI_DI ),
.sck ( SPI_SCK ),
.ss ( SPI_SS2 ),
.ss_sd ( SPI_SS4 ),
.sdi ( spi_din ),
.sdo ( data_io_sdo ),
.reset ( reset ),
.ide_req ( ide_req ),
.ide_ack ( ide_ack ),
.ide_err ( ide_err ),
.ide_reg_o_adr ( ide_reg_i_adr ),
.ide_reg_o ( ide_reg_i ),
.ide_reg_we ( ide_reg_we ),
.ide_reg_i_adr ( ide_reg_o_adr ),
.ide_reg_i ( ide_reg_o ),
.ide_data_addr ( ide_data_addr ),
.ide_data_o ( ide_data_i ),
.ide_data_i ( ide_data_o ),
.ide_data_rd ( ide_data_rd ),
.ide_data_we ( ide_data_we ),
.downloading ( downloading ),
.size ( ),
.size ( ),
.index ( dio_index ),
// ram interface
@@ -413,13 +435,29 @@ wire [1:0] pixbaseclk_select;
wire i2c_din, i2c_dout, i2c_clock;
wire ide_req;
wire ide_ack;
wire ide_err;
wire [2:0] ide_reg_o_adr;
wire [7:0] ide_reg_o;
wire ide_reg_we;
wire [2:0] ide_reg_i_adr;
wire [7:0] ide_reg_i;
wire [8:0] ide_data_addr;
wire [7:0] ide_data_o;
wire [7:0] ide_data_i;
wire ide_data_rd;
wire ide_data_we;
wire reset = ~ram_ready | ~rom_ready;
archimedes_top ARCHIMEDES(
.CLKCPU_I ( clk_sys ),
.CLKPIX_I ( clk_pix ), // pixel clock for OSD
.CEPIX_O ( ce_pix ),
.RESET_I (~ram_ready | ~rom_ready),
.RESET_I ( reset ),
.MEM_ACK_I ( core_ack_in ),
.MEM_DAT_I ( core_data_in ),
@@ -460,6 +498,21 @@ archimedes_top ARCHIMEDES(
.sd_dout_strobe ( sd_dout_strobe ),
.sd_din_strobe ( sd_din_strobe ),
// IDE controller
.ide_req ( ide_req ),
.ide_ack ( ide_ack ),
.ide_err ( ide_err ),
.ide_reg_o_adr ( ide_reg_o_adr ),
.ide_reg_o ( ide_reg_o ),
.ide_reg_we ( ide_reg_we ),
.ide_reg_i_adr ( ide_reg_i_adr ),
.ide_reg_i ( ide_reg_i ),
.ide_data_addr ( ide_data_addr ),
.ide_data_o ( ide_data_o ),
.ide_data_i ( ide_data_i ),
.ide_data_rd ( ide_data_rd ),
.ide_data_we ( ide_data_we ),
.KBD_OUT_DATA ( kbd_out_data ),
.KBD_OUT_STROBE ( kbd_out_strobe ),
.KBD_IN_DATA ( kbd_in_data ),

198
cores/archie/fpga/mist/data_io.v
View File

@@ -2,7 +2,7 @@
// data_io.v
//
// Data interface for the archimedes core on the MiST board.
// Providing ROM and floppy data up- and download via the MISTs
// Providing ROM and IDE data up- and download via the MISTs
// own arm7 cpu.
//
// http://code.google.com/p/mist-board/
@@ -25,9 +25,27 @@
module data_io #(parameter ADDR_WIDTH=24, START_ADDR = 0) (
// io controller spi interface
input sck,
input ss,
input sdi,
input sck,
input ss,
input ss_sd,
input sdi,
output reg sdo,
input reset,
input ide_req,
output reg ide_ack,
output reg ide_err,
output reg [2:0] ide_reg_i_adr,
input [7:0] ide_reg_i,
output reg ide_reg_we,
output reg [2:0] ide_reg_o_adr,
output reg [7:0] ide_reg_o,
output reg [8:0] ide_data_addr,
output reg [7:0] ide_data_o,
input [7:0] ide_data_i,
output reg ide_data_rd,
output reg ide_data_we,
output reg downloading, // signal indicating an active download
output [ADDR_WIDTH-1:0] size, // number of bytes in input buffer
@@ -52,19 +70,28 @@ assign size = addr - START_ADDR;
// spi client
// *********************************************************************************
// this core supports only the display related OSD commands
// of the minimig
reg [6:0] sbuf;
reg [7:0] cmd;
reg [7:0] data;
reg [2:0] bit_cnt;
reg [2:0] byte_cnt;
reg [4:0] byte_cnt;
reg [6:0] sbuf_sd;
reg [2:0] bit_cnt_sd;
reg [ADDR_WIDTH-1:0] addr;
localparam UIO_FILE_TX = 8'h53;
localparam UIO_FILE_TX_DAT = 8'h54;
localparam UIO_FILE_INDEX = 8'h55;
// data_io has its own SPI interface to the io controller
localparam CMD_IDECMD = 8'h04;
localparam CMD_IDEDAT = 8'h08;
localparam CMD_IDE_REGS_RD = 8'h80;
localparam CMD_IDE_REGS_WR = 8'h90;
localparam CMD_IDE_DATA_WR = 8'hA0;
localparam CMD_IDE_DATA_RD = 8'hB0;
localparam CMD_IDE_STATUS_WR = 8'hF0;
// SPI bit and byte counters
always@(posedge sck or posedge ss) begin
@@ -79,6 +106,63 @@ always@(posedge sck or posedge ss) begin
end
end
reg spi_receiver_strobe_sd_r = 0;
reg spi_transfer_end_sd_r = 1;
reg [7:0] spi_byte_in_sd;
// direct SD
always@(posedge sck or posedge ss_sd) begin
if(ss_sd == 1) begin
bit_cnt_sd <= 0;
spi_transfer_end_sd_r <= 1;
end else begin
bit_cnt_sd <= bit_cnt_sd + 1'd1;
spi_transfer_end_sd_r <= 0;
if(&bit_cnt_sd) begin
// finished reading a byte, prepare to transfer to clk_sys
spi_byte_in_sd <= { sbuf_sd, sdi};
spi_receiver_strobe_sd_r <= ~spi_receiver_strobe_sd_r;
end else
sbuf_sd[6:0] <= { sbuf_sd[5:0], sdi };
end
end
// SPI transmitter FPGA -> IO
// CMD_IDEDAT is required before the first sector of a write commands
// and just before the _first_ one, even with multiple sector writes.
wire [7:0] cmdcode = write_start ? CMD_IDEDAT : newcmd ? CMD_IDECMD : 8'h0;
wire [4:0] tf_o_pos = byte_cnt - 4'd5;
// need to know the ATA command sent by Archie for some local processing here
reg [7:0] ide_cmd;
always@(negedge sck or posedge ss) begin
reg [7:0] dout_r;
if(ss == 1) begin
sdo <= 1'bZ;
end else begin
if (&bit_cnt) begin
case(cmd)
CMD_IDE_REGS_RD:
begin
// send task file regs
dout_r <= ide_reg_i;
ide_reg_i_adr <= tf_o_pos[3:1];
if (tf_o_pos[3:1] == 3'd7) ide_cmd <= ide_reg_i;
end
CMD_IDE_DATA_RD: dout_r <= ide_data_i;
default: dout_r <= cmdcode;
endcase
end
sdo <= (cmd == 0) ? cmdcode[~bit_cnt] : dout_r[~bit_cnt];
end
end
// SPI receiver IO -> FPGA
reg spi_receiver_strobe_r = 0;
@@ -90,6 +174,7 @@ always@(posedge sck or posedge ss) begin
if(ss == 1) begin
spi_transfer_end_r <= 1;
cmd <= 0;
end else begin
spi_transfer_end_r <= 0;
@@ -97,11 +182,16 @@ always@(posedge sck or posedge ss) begin
// finished reading a byte, prepare to transfer to clk_sys
spi_byte_in <= { sbuf, sdi};
spi_receiver_strobe_r <= ~spi_receiver_strobe_r;
if (!byte_cnt) cmd <= { sbuf, sdi };
end else
sbuf[6:0] <= { sbuf[5:0], sdi };
end
end
reg newcmd = 0;
reg write_req = 0;
reg write_start = 0;
// Process bytes from SPI at the clk_sys domain
always @(posedge clk) begin
@@ -110,10 +200,45 @@ always @(posedge clk) begin
reg spi_receiver_strobeD;
reg spi_transfer_endD;
reg [7:0] acmd;
reg [3:0] abyte_cnt; // counts bytes
reg [4:0] abyte_cnt; // counts bytes
reg spi_receiver_strobe_sd;
reg spi_transfer_end_sd;
reg spi_receiver_strobe_sdD;
reg spi_transfer_end_sdD;
reg [4:0] abyte_cnt_sd;
wr <= 0;
// This "state-machine" is messy, but the firmware has to be clean up
// to make it more clear. And that would require changes in Minimig, too.
if (reset) begin
newcmd <= 0;
write_req <= 0;
write_start <= 0;
end
if (ide_req) begin
ide_data_addr <= 0;
ide_err <= 0;
newcmd <= 1;
write_start <= write_req;
end
ide_reg_we <= 0;
ide_ack <= 0;
ide_data_we <= 0;
if (ide_data_we) begin
ide_data_addr <= ide_data_addr + 1'd1;
newcmd <= 0;
end
ide_data_rd <= 0;
if (ide_data_rd) begin
ide_data_addr <= ide_data_addr + 1'b1;
write_req <= 0;
write_start <= 0;
end
//synchronize between SPI and sys clock domains
spi_receiver_strobeD <= spi_receiver_strobe_r;
spi_receiver_strobe <= spi_receiver_strobeD;
@@ -132,6 +257,39 @@ always @(posedge clk) begin
acmd <= spi_byte_in;
end else begin
case(acmd)
// IDE commands
CMD_IDE_STATUS_WR:
if (abyte_cnt == 1) begin
// "real" status register handling inside the IDE module,
// since firmware status codes are not real ATA-1 status codes
// (I wonder how it works for Amiga)
if (spi_byte_in[7]) ide_ack <= 1; // IDE_STATUS_END
if (spi_byte_in[4]) newcmd <= 0; // IDE_STATUS_IRQ
if (spi_byte_in[2] || ((ide_cmd == 8'h30 || ide_cmd == 8'hc5) && spi_byte_in[4] && ~spi_byte_in[7])) write_req <= 1;
if (spi_byte_in[1]) ide_err <= 1; // IDE_STATUS_ERR
end
CMD_IDE_REGS_WR:
begin
ide_reg_o <= spi_byte_in;
if (abyte_cnt == 9) begin ide_reg_o_adr <= 3'd1; ide_reg_we <= 1; end // error
if (abyte_cnt == 11) begin ide_reg_o_adr <= 3'd2; ide_reg_we <= 1; end // sector count
if (abyte_cnt == 13) begin ide_reg_o_adr <= 3'd3; ide_reg_we <= 1; end // sector number
if (abyte_cnt == 15) begin ide_reg_o_adr <= 3'd4; ide_reg_we <= 1; end // cyl low
if (abyte_cnt == 17) begin ide_reg_o_adr <= 3'd5; ide_reg_we <= 1; end // cyl high
if (abyte_cnt == 19) begin ide_reg_o_adr <= 3'd6; ide_reg_we <= 1; end // drive/head
end
CMD_IDE_DATA_WR:
if (abyte_cnt > 5) begin
ide_data_we <= 1;
ide_data_o <= spi_byte_in;
end
CMD_IDE_DATA_RD:
if (abyte_cnt > 4) ide_data_rd <= 1;
// file transfer commands
UIO_FILE_TX:
begin
// prepare
@@ -158,6 +316,28 @@ always @(posedge clk) begin
endcase;
end
end
// direct-sd connection
// synchronize between SPI and sys clock domains
spi_receiver_strobe_sdD <= spi_receiver_strobe_sd_r;
spi_receiver_strobe_sd <= spi_receiver_strobe_sdD;
spi_transfer_end_sdD <= spi_transfer_end_sd_r;
spi_transfer_end_sd <= spi_transfer_end_sdD;
// strobe is set whenever a valid byte has been received
if (~spi_transfer_end_sdD & spi_transfer_end_sd) begin
abyte_cnt_sd <= 0;
end else if (spi_receiver_strobe_sdD ^ spi_receiver_strobe_sd) begin
if(~&abyte_cnt_sd)
abyte_cnt_sd <= abyte_cnt_sd + 1'd1;
if (abyte_cnt_sd == 0 || ide_data_addr != 0) begin // filter spurious byte at the end
ide_data_we <= 1;
ide_data_o <= spi_byte_in_sd;
end
end
end
endmodule

51
cores/archie/rtl/archimedes_top.v
View File

@@ -80,6 +80,21 @@ module archimedes_top(
input sd_dout_strobe,
input sd_din_strobe,
// connection to the IDE controller
output ide_req, // new command request
input ide_err,
input ide_ack, // command finished on the IO controller side
input [2:0] ide_reg_o_adr,// requested task file register index
output [7:0] ide_reg_o, // task file register out
input ide_reg_we, // task file register write strobe from IO controller
input [2:0] ide_reg_i_adr,
input [7:0] ide_reg_i, // task file register input
input [8:0] ide_data_addr,
output [7:0] ide_data_o,
input [7:0] ide_data_i,
input ide_data_rd,
input ide_data_we,
// connection to keyboard controller
output [7:0] KBD_OUT_DATA,
output KBD_OUT_STROBE,
@@ -305,7 +320,10 @@ podules PODULES(
.wb_dat_o ( pod_dat_o ),
.wb_dat_i ( cpu_dat_o[15:0] ),
.wb_adr ( cpu_address[15:2] )
.wb_adr ( cpu_address[15:2] ),
.ide_sel ( ide_sel ),
.ide_din ( ide_dat_o )
);
wire [7:0] floppy_dat_o;
@@ -356,6 +374,37 @@ fdc1772 #(.CLK(40000000)) FDC1772 (
.floppy_reset ( floppy_reset )
);
wire [15:0] ide_dat_o;
wire ide_sel;
ide IDE (
.clk ( CLKCPU_I ),
.reset ( RESET_I ),
.ide_sel ( ide_sel ),
.ide_we ( cpu_we ),
.ide_reg ( cpu_address[4:2] ),
.ide_dat_o ( ide_dat_o ),
.ide_dat_i ( cpu_dat_o[31:16] ),
.ide_req ( ide_req ),
.ide_ack ( ide_ack ),
.ide_err ( ide_err ),
.ide_reg_o_adr ( ide_reg_o_adr ),
.ide_reg_o ( ide_reg_o ),
.ide_reg_we ( ide_reg_we ),
.ide_reg_i_adr ( ide_reg_i_adr ),
.ide_reg_i ( ide_reg_i ),
.ide_data_addr ( ide_data_addr ),
.ide_data_o ( ide_data_o ),
.ide_data_i ( ide_data_i ),
.ide_data_rd ( ide_data_rd ),
.ide_data_we ( ide_data_we )
);
wire [7:0] latches_dat_o;
wire latches_en = ioc_cs & ioc_select[5] & (ioc_speed == 2'd2);

199
cores/archie/rtl/ide.sv Normal file
View File

@@ -0,0 +1,199 @@
//
// ide.sv
//
// Copyright (c) 2019 György Szombathelyi
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module ide (
input clk, // system clock.
input reset,
input ide_sel,
input ide_we,
input [2:0] ide_reg,
input [15:0] ide_dat_i,
output reg [15:0] ide_dat_o,
// place any signals that need to be passed up to the top after here.
output reg ide_req,
input ide_err,
input ide_ack,
input [2:0] ide_reg_o_adr,
output reg [7:0] ide_reg_o,
input ide_reg_we,
input [2:0] ide_reg_i_adr,
input [7:0] ide_reg_i,
input [8:0] ide_data_addr,
output [7:0] ide_data_o,
input [7:0] ide_data_i,
input ide_data_rd,
input ide_data_we
);
assign ide_req = ide_cmd_req | ide_sector_req;
reg [7:0] taskfile[8];
reg [7:0] status;
// read from Task File Registers
always @(*) begin
reg [7:0] ide_dat_b;
//cpu read
ide_dat_b = (ide_reg == 3'd7) ? { status[7:1], ide_err } : taskfile[ide_reg];
ide_dat_o = 16'hFFFF;
if (ide_sel && !ide_we) begin
ide_dat_o = (ide_reg == 3'd0) ? data_out : { ide_dat_b, ide_dat_b };
end
// IO controller read
ide_reg_o = taskfile[ide_reg_o_adr];
end
reg ide_cmd_req;
// write to Task File Registers
always @(posedge clk) begin
ide_cmd_req <= 0;
// cpu write
if (ide_sel && ide_we) begin
taskfile[ide_reg] <= ide_dat_i[7:0];
// writing to the command register triggers the IO controller
if (ide_reg == 3'd7) ide_cmd_req <= 1;
end
// IO controller write
if (ide_reg_we) taskfile[ide_reg_i_adr] <= ide_reg_i;
end
reg ide_sector_req;
// status register handling
always @(posedge clk) begin
reg [7:0] sector_count;
if (reset) begin
status <= 8'h48;
ide_sector_req <= 0;
sector_count <= 8'd1;
end else begin
// write to command register starts the execution
if (ide_sel && ide_we && ide_reg == 3'd7) begin
sector_count <= taskfile[2];
case (taskfile[7])
8'h30, 8'hc5: status <= 8'h08; // request data
default: status <= 8'h80; // busy
endcase
end
if (ide_ack) begin
case (taskfile[7])
8'hec : status <= 8'h08; // ready to transfer
8'h20, 8'h30, 8'hc4, 8'hc5: ;
default: status <= 8'h40; // ready
endcase
end
// sector buffer - IO controller side
if ((ide_data_rd | ide_data_we) & ide_data_addr == 9'h1ff) status <= 8'h08; // sector buffer consumed/filled, ready to transfer
if (ide_data_rd | ide_data_we) ide_sector_req <= 0;
// sector buffer - CPU side
if (ide_sel_d && ~ide_sel && ide_reg == 3'd0 && data_addr == 8'hff) begin
status <= 8'h40; // ready
case (taskfile[7])
8'h20, 8'hc4: // reads
begin
sector_count <= sector_count - 1'd1;
if (sector_count != 1) ide_sector_req <= 1; // request the next sector
end
8'h30, 8'hc5:
begin
ide_sector_req <= 1; // write, signals the write buffer is ready
status <= 8'h80; // busy
end
default: ;
endcase
end
end
end
reg [7:0] data_addr;
wire [15:0] data_out;
reg ide_sel_d;
// read/write data register
always @(posedge clk) begin
ide_sel_d <= ide_sel;
if (ide_sel && ide_we && ide_reg == 3'd7) data_addr <= 0;
if (ide_sel_d && ~ide_sel && ide_reg == 3'd0) data_addr <= data_addr + 1'd1;
end
// mixed-width sector buffer
ide_dpram ide_databuf (
.clock ( clk ),
.address_a ( data_addr ),
.data_a ( ide_dat_i ),
.wren_a ( ide_sel && ide_we && ide_reg == 3'd0 ),
.q_a ( data_out ),
.address_b ( ide_data_addr ),
.data_b ( ide_data_i ),
.wren_b ( ide_data_we ),
.q_b ( ide_data_o )
);
endmodule
module ide_dpram
(
input clock,
input [7:0] address_a,
input [15:0] data_a,
input wren_a,
output reg [15:0] q_a,
input [8:0] address_b,
input [7:0] data_b,
input wren_b,
output reg [7:0] q_b
);
reg [1:0][7:0] ram[256];
always @(posedge clock) begin
if(wren_a) begin
ram[address_a] <= data_a;
q_a <= data_a;
end else begin
q_a <= ram[address_a];
end
end
always @(posedge clock) begin
if(wren_b) begin
ram[address_b[8:1]][address_b[0]] <= data_b;
q_b <= data_b;
end else begin
q_b <= ram[address_b[8:1]][address_b[0]];
end
end
endmodule

76
cores/archie/rtl/podules.v
View File

@@ -29,24 +29,26 @@
module podules(
input clkcpu, // system cpu clock.
input clk8m_en, // goes high in sync with 32m clock to give simulated 8mhz
input clk2m_en, // goes high in sync with 32m clock to give simulated 2mhz
input clkcpu, // system cpu clock.
input clk8m_en, // goes high in sync with 32m clock to give simulated 8mhz
input clk2m_en, // goes high in sync with 32m clock to give simulated 2mhz
input rst_i, // reset
input rst_i, // reset
input [1:0] speed_i, // podule access speed. (redundant except for address decode).
input [1:0] speed_i, // podule access speed. (redundant except for address decode).
// "wishbone bus" the ack is externally generated currently.
input wb_cyc,
input wb_stb,
input wb_we,
input wb_cyc,
input wb_stb,
input wb_we,
input [15:2] wb_adr, // la
input [15:0] wb_dat_i, // bd
output[15:0] wb_dat_o // bd
input [15:2] wb_adr, // la
input [15:0] wb_dat_i, // bd
output [15:0] wb_dat_o, // bd
// place any signals that need to be passed up to the top after here.
output ide_sel,
input [15:0] ide_din
);
localparam PODULE0 = 2'b00;
@@ -54,27 +56,41 @@ localparam PODULE1 = 2'b01;
localparam PODULE2 = 2'b10;
localparam PODULE3 = 2'b11;
wire [1:0] podule_addr = wb_adr[15:14];
wire [3:0] podule_select = podule_addr == PODULE0 ? 4'b0001 :
podule_addr == PODULE1 ? 4'b0010 :
podule_addr == PODULE2 ? 4'b0100 :
podule_addr == PODULE3 ? 4'b1000 : 4'd0;
wire [1:0] podule_addr = wb_adr[15:14];
wire [3:0] podule_select = podule_addr == PODULE0 ? 4'b0001 :
podule_addr == PODULE1 ? 4'b0010 :
podule_addr == PODULE2 ? 4'b0100 :
podule_addr == PODULE3 ? 4'b1000 : 4'd0;
wire [15:0] pod0_dat;
wire [15:0] pod1_dat;
wire [15:0] pod2_dat;
wire [15:0] pod3_dat;
always @(posedge clkcpu) begin
end
wire [15:0] pod0_dat;
wire [15:0] pod1_dat;
wire [15:0] pod2_dat;
wire [15:0] pod3_dat;
// emulate a simple podule as a test for *PODULES
assign pod0_dat = wb_adr[13:2] == 12'd0 ? {8'd0, 8'b0_1010_000} : 16'hFFFF;
// assign pod0_dat = wb_adr[13:2] == 12'd0 ? {8'd0, 8'b0_1010_000} : 16'hFFFF;
// RISC Developments IDE Interface in Podule 0
reg [7:0] rd_rom[16384];
reg [2:0] rd_page;
reg [7:0] rd_rom_q;
initial begin
$readmemh("riscdevide_rom.hex", rd_rom);
rd_page <= 0;
end
assign ide_sel = wb_stb && wb_cyc && podule_select[PODULE0] && wb_adr[13:10] == 4'hA;
wire page_sel = wb_stb && wb_cyc && podule_select[PODULE0] && wb_we && wb_adr[13:2] == 12'h800;
always @(posedge clkcpu) begin
if (page_sel) rd_page <= wb_dat_i[2:0];
rd_rom_q <= rd_rom[{rd_page, wb_adr[12:2]}];
end
assign pod0_dat = ide_sel ? ide_din : {8'd0, rd_rom_q};
assign wb_dat_o = podule_select[PODULE0] ? pod0_dat : 16'hFFFF;
endmodule

714
cores/archie/rtl/riscdevide_rom.hex Normal file
View File

@@ -0,0 +1,714 @@
/* http://srecord.sourceforge.net/ */
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@00003A0A FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003A21 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003A38 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003A4F FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003A66 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003A7D FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003A94 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003AAB FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003AC2 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003AD9 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003AF0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003B07 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003B1E FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003B35 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003B4C FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003B63 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003B7A FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003B91 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003BA8 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003BBF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003BD6 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003BED FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003C04 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003C1B FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003C32 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003C49 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003C60 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003C77 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003C8E FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003CA5 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003CBC FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003CD3 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003CEA FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003D01 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003D18 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003D2F FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003D46 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003D5D FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003D74 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003D8B FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003DA2 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003DB9 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003DD0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003DE7 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003DFE FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003E15 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003E2C FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003E43 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003E5A FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003E71 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003E88 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003E9F FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003EB6 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003ECD FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003EE4 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003EFB FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003F12 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003F29 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003F40 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003F57 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003F6E FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003F85 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003F9C FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003FB3 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003FCA FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003FE1 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
@00003FF8 FF FF FF FF FF FF FF FF

11
cores/archie/rtl/sdram/sdram_top.v
View File

@@ -77,6 +77,8 @@ reg [9:0] sd_refresh = 10'd0;
reg sd_auto_refresh = 1'b0;
reg sd_need_refresh = 1'b0;
wire sd_req = wb_stb & wb_cyc & ~wb_ack;
reg sd_req_reg;
reg sd_cache_hit;
reg [11:0] sd_active_row[3:0];
reg [3:0] sd_bank_active;
wire [1:0] sd_bank = wb_adr[22:21];
@@ -170,6 +172,9 @@ always @(posedge sd_clk) begin
sd_word <= sd_word + 1'd1;
sd_dat[sd_word[2:1]][{sd_word[0],4'b0000} +:16] <= sd_dq;
end
sd_req_reg <= sd_req;
sd_cache_hit <= ~wb_we && sd_last_adr[23:4] == wb_adr[23:4];
// this is the auto refresh code.
// it kicks in so that 8192 auto refreshes are
// issued in a 64ms period. Other bus operations
@@ -196,7 +201,7 @@ always @(posedge sd_clk) begin
default: ;
endcase
end else if ((sd_cycle != 0) | (sd_cycle == 0 && sd_req)) begin
end else if ((sd_cycle != 0) | (sd_cycle == 0 && sd_req_reg)) begin
// while the cycle is active count.
sd_cycle <= sd_cycle + 1'd1;
@@ -204,7 +209,7 @@ always @(posedge sd_clk) begin
CYCLE_PRECHARGE: begin
sd_we <= wb_we;
word_index <= 2'b00;
if (~wb_we && sd_last_adr[23:4] == wb_adr[23:4]) begin
if (sd_cache_hit) begin
// this word is already in sd_dat, but where?
word_index <= wb_adr[3:2] - sd_last_adr[3:2];
sd_done <= ~sd_done;
@@ -281,7 +286,7 @@ always @(posedge sd_clk) begin
sd_dat[0][15:0] <= sd_dq;
sd_word <= 3'b001;
end else
sd_cycle <= 5'd0;
sd_cycle <= CYCLE_END;
end
CYCLE_READ1: if (~sd_we) sd_done <= ~sd_done;