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PlusToo: update the CPU and some internal stuff
This commit is contained in:
Gyorgy Szombathelyi
File diff suppressed because it is too large
Load Diff
@@ -1,250 +1,180 @@
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- --
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-- Copyright (c) 2009-2013 Tobias Gubener --
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-- Subdesign fAMpIGA by TobiFlex --
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||||
-- --
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-- This source file is free software: you can redistribute it and/or modify --
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||||
-- it under the terms of the GNU General Public License as published --
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||||
-- by the Free Software Foundation, either version 3 of the License, or --
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||||
-- (at your option) any later version. --
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||||
-- --
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||||
-- This source file is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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||||
-- GNU General Public License for more details. --
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||||
-- --
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||||
-- You should have received a copy of the GNU General Public License --
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||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
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-- --
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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package TG68K_Pack is
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type micro_states is (idle, nop, ld_nn, st_nn, ld_dAn1, ld_AnXn1, ld_AnXn2, st_dAn1, ld_AnXnbd1, ld_AnXnbd2, ld_AnXnbd3,
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ld_229_1, ld_229_2, ld_229_3, ld_229_4, st_229_1, st_229_2, st_229_3, st_229_4,
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st_AnXn1, st_AnXn2, bra1, bsr1, bsr2, nopnop, dbcc1, movem1, movem2, movem3,
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andi, op_AxAy, cmpm, link1, link2, unlink1, unlink2, int1, int2, int3, int4, rte1, rte2, rte3, trap0, trap1, trap2, trap3,
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trap4, trap5, trap6, movec1, movep1, movep2, movep3, movep4, movep5, rota1, bf1,
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mul1, mul2, mul_end1, mul_end2, div1, div2, div3, div4, div_end1, div_end2, pack1, pack2, pack3);
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constant opcMOVE : integer := 0; --
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constant opcMOVEQ : integer := 1; --
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constant opcMOVESR : integer := 2; --
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constant opcADD : integer := 3; --
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constant opcADDQ : integer := 4; --
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constant opcOR : integer := 5; --
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constant opcAND : integer := 6; --
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constant opcEOR : integer := 7; --
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constant opcCMP : integer := 8; --
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constant opcROT : integer := 9; --
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constant opcCPMAW : integer := 10;
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constant opcEXT : integer := 11; --
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constant opcABCD : integer := 12; --
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constant opcSBCD : integer := 13; --
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constant opcBITS : integer := 14; --
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constant opcSWAP : integer := 15; --
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constant opcScc : integer := 16; --
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constant andiSR : integer := 17; --
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constant eoriSR : integer := 18; --
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constant oriSR : integer := 19; --
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constant opcMULU : integer := 20; --
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constant opcDIVU : integer := 21; --
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constant dispouter : integer := 22; --
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constant rot_nop : integer := 23; --
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constant ld_rot_cnt : integer := 24; --
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constant writePC_add : integer := 25; --
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constant ea_data_OP1 : integer := 26; --
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constant ea_data_OP2 : integer := 27; --
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constant use_XZFlag : integer := 28; --
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constant get_bfoffset : integer := 29; --
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constant save_memaddr : integer := 30; --
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constant opcCHK : integer := 31; --
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constant movec_rd : integer := 32; --
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constant movec_wr : integer := 33; --
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constant Regwrena : integer := 34; --
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constant update_FC : integer := 35; --
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constant linksp : integer := 36; --
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constant movepl : integer := 37; --
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constant update_ld : integer := 38; --
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constant OP1addr : integer := 39; --
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constant write_reg : integer := 40; --
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constant changeMode : integer := 41; --
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constant ea_build : integer := 42; --
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constant trap_chk : integer := 43; --
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constant store_ea_data : integer := 44; --
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constant addrlong : integer := 45; --
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constant postadd : integer := 46; --
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constant presub : integer := 47; --
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constant subidx : integer := 48; --
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constant no_Flags : integer := 49; --
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constant use_SP : integer := 50; --
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constant to_CCR : integer := 51; --
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constant to_SR : integer := 52; --
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constant OP2out_one : integer := 53; --
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constant OP1out_zero : integer := 54; --
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constant mem_addsub : integer := 55; --
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constant addsub : integer := 56; --
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constant directPC : integer := 57; --
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constant direct_delta : integer := 58; --
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constant directSR : integer := 59; --
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constant directCCR : integer := 60; --
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constant exg : integer := 61; --
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constant get_ea_now : integer := 62; --
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constant ea_to_pc : integer := 63; --
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constant hold_dwr : integer := 64; --
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constant to_USP : integer := 65; --
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constant from_USP : integer := 66; --
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constant write_lowlong : integer := 67; --
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constant write_reminder : integer := 68; --
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constant movem_action : integer := 69; --
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constant briefext : integer := 70; --
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constant get_2ndOPC : integer := 71; --
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constant mem_byte : integer := 72; --
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constant longaktion : integer := 73; --
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constant opcRESET : integer := 74; --
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constant opcBF : integer := 75; --
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constant opcBFwb : integer := 76; --
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constant s2nd_hbits : integer := 77; --
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constant opcPACK : integer := 77; --
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-- constant s2nd_hbits : integer := 77; --
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-- constant : integer := 75; --
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-- constant : integer := 76; --
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-- constant : integer := 7; --
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-- constant : integer := 7; --
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-- constant : integer := 7; --
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constant lastOpcBit : integer := 77;
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type rTG68K_opc is record
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opcMOVE : bit;
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opcMOVEQ : bit;
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opcMOVESR : bit;
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opcADD : bit;
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opcADDQ : bit;
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opcOR : bit;
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opcAND : bit;
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opcEOR : bit;
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opcCMP : bit;
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opcROT : bit;
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opcCPMAW : bit;
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opcEXT : bit;
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opcABCD : bit;
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opcSBCD : bit;
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opcBITS : bit;
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opcSWAP : bit;
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opcScc : bit;
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andiSR : bit;
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eoriSR : bit;
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oriSR : bit;
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opcMULU : bit;
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opcDIVU : bit;
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dispouter : bit;
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rot_nop : bit;
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ld_rot_cnt : bit;
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writePC_add : bit;
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ea_data_OP1 : bit;
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ea_data_OP2 : bit;
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use_XZFlag : bit;
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get_bfoffset : bit;
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save_memaddr : bit;
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opcCHK : bit;
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movec_rd : bit;
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movec_wr : bit;
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Regwrena : bit;
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update_FC : bit;
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linksp : bit;
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movepl : bit;
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update_ld : bit;
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OP1addr : bit;
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write_reg : bit;
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changeMode : bit;
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ea_build : bit;
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trap_chk : bit;
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store_ea_data : bit;
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addrlong : bit;
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postadd : bit;
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presub : bit;
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subidx : bit;
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no_Flags : bit;
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use_SP : bit;
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to_CCR : bit;
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to_SR : bit;
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OP2out_one : bit;
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OP1out_zero : bit;
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mem_addsub : bit;
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addsub : bit;
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directPC : bit;
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direct_delta : bit;
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directSR : bit;
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directCCR : bit;
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exg : bit;
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get_ea_now : bit;
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ea_to_pc : bit;
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hold_dwr : bit;
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to_USP : bit;
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from_USP : bit;
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write_lowlong : bit;
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write_reminder : bit;
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movem_action : bit;
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briefext : bit;
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get_2ndOPC : bit;
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mem_byte : bit;
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longaktion : bit;
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opcRESET : bit;
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opcBF : bit;
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opcBFwb : bit;
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s2nd_hbits : bit;
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end record;
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component TG68K_ALU
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generic(
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MUL_Mode : integer := 0; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
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DIV_Mode : integer := 0 --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
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);
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port(
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clk : in std_logic;
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Reset : in std_logic;
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clkena_lw : in std_logic:='1';
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execOPC : in bit;
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exe_condition : in std_logic;
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exec_tas : in std_logic;
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long_start : in bit;
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movem_presub : in bit;
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set_stop : in bit;
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Z_error : in bit;
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rot_bits : in std_logic_vector(1 downto 0);
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exec : in bit_vector(lastOpcBit downto 0);
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OP1out : in std_logic_vector(31 downto 0);
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OP2out : in std_logic_vector(31 downto 0);
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reg_QA : in std_logic_vector(31 downto 0);
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reg_QB : in std_logic_vector(31 downto 0);
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opcode : in std_logic_vector(15 downto 0);
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datatype : in std_logic_vector(1 downto 0);
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exe_opcode : in std_logic_vector(15 downto 0);
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exe_datatype : in std_logic_vector(1 downto 0);
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sndOPC : in std_logic_vector(15 downto 0);
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last_data_read : in std_logic_vector(15 downto 0);
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data_read : in std_logic_vector(15 downto 0);
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FlagsSR : in std_logic_vector(7 downto 0);
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micro_state : in micro_states;
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bf_ext_in : in std_logic_vector(7 downto 0);
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bf_ext_out : out std_logic_vector(7 downto 0);
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bf_shift : in std_logic_vector(5 downto 0);
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bf_width : in std_logic_vector(5 downto 0);
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bf_loffset : in std_logic_vector(4 downto 0);
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set_V_Flag : buffer bit;
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Flags : buffer std_logic_vector(7 downto 0);
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c_out : buffer std_logic_vector(2 downto 0);
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addsub_q : buffer std_logic_vector(31 downto 0);
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ALUout : out std_logic_vector(31 downto 0)
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);
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end component;
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end;
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- --
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-- Copyright (c) 2009-2020 Tobias Gubener --
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-- Patches by MikeJ, Till Harbaum, Rok Krajnk, ... --
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-- Subdesign fAMpIGA by TobiFlex --
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-- --
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-- This source file is free software: you can redistribute it and/or modify --
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-- it under the terms of the GNU Lesser General Public License as published --
|
||||
-- by the Free Software Foundation, either version 3 of the License, or --
|
||||
-- (at your option) any later version. --
|
||||
-- --
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||||
-- This source file is distributed in the hope that it will be useful, --
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||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
|
||||
-- GNU General Public License for more details. --
|
||||
-- --
|
||||
-- You should have received a copy of the GNU General Public License --
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
|
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-- --
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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package TG68K_Pack is
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type micro_states is (idle, nop, ld_nn, st_nn, ld_dAn1, ld_AnXn1, ld_AnXn2, st_dAn1, ld_AnXnbd1, ld_AnXnbd2, ld_AnXnbd3,
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ld_229_1, ld_229_2, ld_229_3, ld_229_4, st_229_1, st_229_2, st_229_3, st_229_4,
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st_AnXn1, st_AnXn2, bra1, bsr1, bsr2, nopnop, dbcc1, movem1, movem2, movem3,
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andi, pack1, pack2, pack3, op_AxAy, cmpm, link1, link2, unlink1, unlink2, int1, int2, int3, int4, rte1, rte2, rte3,
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rte4, rte5, rtd1, rtd2, trap00, trap0, trap1, trap2, trap3, cas1, cas2, cas21, cas22, cas23, cas24,
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cas25, cas26, cas27, cas28, chk20, chk21, chk22, chk23, chk24,
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trap4, trap5, trap6, movec1, movep1, movep2, movep3, movep4, movep5, rota1, bf1,
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mul1, mul2, mul_end1, mul_end2, div1, div2, div3, div4, div_end1, div_end2);
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constant opcMOVE : integer := 0; --
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constant opcMOVEQ : integer := 1; --
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constant opcMOVESR : integer := 2; --
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constant opcADD : integer := 3; --
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constant opcADDQ : integer := 4; --
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constant opcOR : integer := 5; --
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constant opcAND : integer := 6; --
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constant opcEOR : integer := 7; --
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constant opcCMP : integer := 8; --
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constant opcROT : integer := 9; --
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constant opcCPMAW : integer := 10;
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constant opcEXT : integer := 11; --
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constant opcABCD : integer := 12; --
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constant opcSBCD : integer := 13; --
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constant opcBITS : integer := 14; --
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constant opcSWAP : integer := 15; --
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constant opcScc : integer := 16; --
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constant andiSR : integer := 17; --
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constant eoriSR : integer := 18; --
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constant oriSR : integer := 19; --
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constant opcMULU : integer := 20; --
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constant opcDIVU : integer := 21; --
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constant dispouter : integer := 22; --
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constant rot_nop : integer := 23; --
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constant ld_rot_cnt : integer := 24; --
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constant writePC_add : integer := 25; --
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constant ea_data_OP1 : integer := 26; --
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constant ea_data_OP2 : integer := 27; --
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constant use_XZFlag : integer := 28; --
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constant get_bfoffset : integer := 29; --
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constant save_memaddr : integer := 30; --
|
||||
constant opcCHK : integer := 31; --
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constant movec_rd : integer := 32; --
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constant movec_wr : integer := 33; --
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constant Regwrena : integer := 34; --
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constant update_FC : integer := 35; --
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||||
constant linksp : integer := 36; --
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||||
constant movepl : integer := 37; --
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||||
constant update_ld : integer := 38; --
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||||
constant OP1addr : integer := 39; --
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constant write_reg : integer := 40; --
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constant changeMode : integer := 41; --
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||||
constant ea_build : integer := 42; --
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||||
constant trap_chk : integer := 43; --
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||||
constant store_ea_data : integer := 44; --
|
||||
constant addrlong : integer := 45; --
|
||||
constant postadd : integer := 46; --
|
||||
constant presub : integer := 47; --
|
||||
constant subidx : integer := 48; --
|
||||
constant no_Flags : integer := 49; --
|
||||
constant use_SP : integer := 50; --
|
||||
constant to_CCR : integer := 51; --
|
||||
constant to_SR : integer := 52; --
|
||||
constant OP2out_one : integer := 53; --
|
||||
constant OP1out_zero : integer := 54; --
|
||||
constant mem_addsub : integer := 55; --
|
||||
constant addsub : integer := 56; --
|
||||
constant directPC : integer := 57; --
|
||||
constant direct_delta : integer := 58; --
|
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constant directSR : integer := 59; --
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||||
constant directCCR : integer := 60; --
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||||
constant exg : integer := 61; --
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||||
constant get_ea_now : integer := 62; --
|
||||
constant ea_to_pc : integer := 63; --
|
||||
constant hold_dwr : integer := 64; --
|
||||
constant to_USP : integer := 65; --
|
||||
constant from_USP : integer := 66; --
|
||||
constant write_lowlong : integer := 67; --
|
||||
constant write_reminder : integer := 68; --
|
||||
constant movem_action : integer := 69; --
|
||||
constant briefext : integer := 70; --
|
||||
constant get_2ndOPC : integer := 71; --
|
||||
constant mem_byte : integer := 72; --
|
||||
constant longaktion : integer := 73; --
|
||||
constant opcRESET : integer := 74; --
|
||||
constant opcBF : integer := 75; --
|
||||
constant opcBFwb : integer := 76; --
|
||||
constant opcPACK : integer := 77; --
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||||
constant opcUNPACK : integer := 78; --
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||||
constant hold_ea_data : integer := 79; --
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||||
constant store_ea_packdata : integer := 80; --
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||||
constant exec_BS : integer := 81; --
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||||
constant hold_OP2 : integer := 82; --
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||||
constant restore_ADDR : integer := 83; --
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||||
constant alu_exec : integer := 84; --
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||||
constant alu_move : integer := 85; --
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||||
constant alu_setFlags : integer := 86; --
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constant opcCHK2 : integer := 87; --
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||||
constant opcEXTB : integer := 88; --
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||||
|
||||
constant lastOpcBit : integer := 88;
|
||||
|
||||
component TG68K_ALU
|
||||
generic(
|
||||
MUL_Mode :integer; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
|
||||
MUL_Hardware :integer; --0=>no, 1=>yes,
|
||||
DIV_Mode :integer; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
|
||||
BarrelShifter :integer --0=>no, 1=>yes, 2=>switchable with CPU(1)
|
||||
);
|
||||
port(
|
||||
clk : in std_logic;
|
||||
Reset : in std_logic;
|
||||
CPU : in std_logic_vector(1 downto 0):="00"; -- 00->68000 01->68010 11->68020(only some parts - yet)
|
||||
clkena_lw : in std_logic:='1';
|
||||
execOPC : in bit;
|
||||
decodeOPC : in bit;
|
||||
exe_condition : in std_logic;
|
||||
exec_tas : in std_logic;
|
||||
long_start : in bit;
|
||||
non_aligned : in std_logic;
|
||||
movem_presub : in bit;
|
||||
set_stop : in bit;
|
||||
Z_error : in bit;
|
||||
rot_bits : in std_logic_vector(1 downto 0);
|
||||
exec : in bit_vector(lastOpcBit downto 0);
|
||||
OP1out : in std_logic_vector(31 downto 0);
|
||||
OP2out : in std_logic_vector(31 downto 0);
|
||||
reg_QA : in std_logic_vector(31 downto 0);
|
||||
reg_QB : in std_logic_vector(31 downto 0);
|
||||
opcode : in std_logic_vector(15 downto 0);
|
||||
-- datatype : in std_logic_vector(1 downto 0);
|
||||
exe_opcode : in std_logic_vector(15 downto 0);
|
||||
exe_datatype : in std_logic_vector(1 downto 0);
|
||||
sndOPC : in std_logic_vector(15 downto 0);
|
||||
last_data_read : in std_logic_vector(15 downto 0);
|
||||
data_read : in std_logic_vector(15 downto 0);
|
||||
FlagsSR : in std_logic_vector(7 downto 0);
|
||||
micro_state : in micro_states;
|
||||
bf_ext_in : in std_logic_vector(7 downto 0);
|
||||
bf_ext_out : out std_logic_vector(7 downto 0);
|
||||
bf_shift : in std_logic_vector(5 downto 0);
|
||||
bf_width : in std_logic_vector(5 downto 0);
|
||||
bf_ffo_offset : in std_logic_vector(31 downto 0);
|
||||
bf_loffset : in std_logic_vector(4 downto 0);
|
||||
|
||||
set_V_Flag : buffer bit;
|
||||
Flags : buffer std_logic_vector(7 downto 0);
|
||||
c_out : buffer std_logic_vector(2 downto 0);
|
||||
addsub_q : buffer std_logic_vector(31 downto 0);
|
||||
ALUout : out std_logic_vector(31 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
end;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,7 +1,9 @@
|
||||
module addrController_top(
|
||||
// clocks:
|
||||
input clk8, // 8.125 MHz CPU clock
|
||||
|
||||
input clk,
|
||||
input clk8_en_p, // 8.125 MHz CPU clock enables
|
||||
input clk8_en_n,
|
||||
|
||||
// system config:
|
||||
input turbo, // 0 = normal, 1 = faster
|
||||
input configROMSize, // 0 = 64K ROM, 1 = 128K ROM
|
||||
@@ -60,12 +62,12 @@ module addrController_top(
|
||||
reg [19:0] snd_div;
|
||||
|
||||
reg sndReadAckD;
|
||||
always @(negedge clk8)
|
||||
sndReadAckD <= sndReadAck;
|
||||
always @(posedge clk)
|
||||
if (clk8_en_n) sndReadAckD <= sndReadAck;
|
||||
|
||||
reg vblankD, vblankD2;
|
||||
always @(posedge clk8) begin
|
||||
if(sndReadAckD) begin
|
||||
always @(posedge clk) begin
|
||||
if(clk8_en_p && sndReadAckD) begin
|
||||
vblankD <= _vblank;
|
||||
vblankD2 <= vblankD;
|
||||
|
||||
@@ -82,24 +84,24 @@ module addrController_top(
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
assign dioBusControl = extraBusControl;
|
||||
|
||||
// interleaved RAM access for CPU and video
|
||||
reg [1:0] busCycle;
|
||||
reg [1:0] extra_slot_count;
|
||||
reg [1:0] subCycle;
|
||||
|
||||
always @(posedge clk8)
|
||||
busCycle <= busCycle + 2'd1;
|
||||
|
||||
|
||||
always @(posedge clk)
|
||||
if (clk8_en_p) busCycle <= busCycle + 2'd1;
|
||||
|
||||
reg extra_slot_advance;
|
||||
always @(negedge clk8)
|
||||
extra_slot_advance <= (busCycle == 2'b11);
|
||||
|
||||
always @(posedge clk)
|
||||
if (clk8_en_n) extra_slot_advance <= (busCycle == 2'b11);
|
||||
|
||||
// allocate memory slots in the extra cycle
|
||||
always @(posedge clk8) begin
|
||||
if(extra_slot_advance) begin
|
||||
always @(posedge clk) begin
|
||||
if(clk8_en_p && extra_slot_advance) begin
|
||||
extra_slot_count <= extra_slot_count + 2'd1;
|
||||
|
||||
// the subcycle counter counts 0-1-2-0-1-2 and is used to give
|
||||
@@ -194,7 +196,8 @@ module addrController_top(
|
||||
|
||||
// video
|
||||
videoTimer vt(
|
||||
.clk8(clk8),
|
||||
.clk(clk),
|
||||
.clk_en(clk8_en_p),
|
||||
.busCycle(busCycle),
|
||||
.videoAddr(videoAddr),
|
||||
.hsync(hsync),
|
||||
|
||||
@@ -2,6 +2,8 @@ module dataController_top(
|
||||
// clocks:
|
||||
input clk32, // 32.5 MHz pixel clock
|
||||
output clk8, // 8.125 MHz CPU clock
|
||||
output clk8_en_p,
|
||||
output clk8_en_n,
|
||||
|
||||
// system control:
|
||||
input _systemReset,
|
||||
@@ -60,6 +62,8 @@ module dataController_top(
|
||||
input [1:0] insertDisk,
|
||||
input [1:0] diskSides,
|
||||
output [1:0] diskEject,
|
||||
output [1:0] diskMotor,
|
||||
output [1:0] diskAct,
|
||||
|
||||
output [21:0] dskReadAddrInt,
|
||||
input dskReadAckInt,
|
||||
@@ -67,14 +71,16 @@ module dataController_top(
|
||||
input dskReadAckExt,
|
||||
|
||||
// connections to io controller
|
||||
output [31:0] io_lba,
|
||||
output io_rd,
|
||||
output io_wr,
|
||||
input io_ack,
|
||||
input [7:0] io_din,
|
||||
input io_din_strobe,
|
||||
output [7:0] io_dout,
|
||||
input io_dout_strobe
|
||||
input [1:0] img_mounted,
|
||||
input [31:0] img_size,
|
||||
output [31:0] io_lba,
|
||||
output [1:0] io_rd,
|
||||
output [1:0] io_wr,
|
||||
input io_ack,
|
||||
input [8:0] sd_buff_addr,
|
||||
input [7:0] sd_buff_dout,
|
||||
output [7:0] sd_buff_din,
|
||||
input sd_buff_wr
|
||||
);
|
||||
|
||||
// add binary volume levels according to volume setting
|
||||
@@ -89,13 +95,13 @@ module dataController_top(
|
||||
wire [10:0] audio_x4 = { audio_latch[7] , audio_latch, 2'b00};
|
||||
|
||||
reg loadSoundD;
|
||||
always @(negedge clk8)
|
||||
loadSoundD <= loadSound;
|
||||
always @(posedge clk32)
|
||||
if (clk8_en_n) loadSoundD <= loadSound;
|
||||
|
||||
// read audio data and convert to signed for further volume adjustment
|
||||
reg [7:0] audio_latch;
|
||||
always @(posedge clk8) begin
|
||||
if(loadSoundD) begin
|
||||
always @(posedge clk32) begin
|
||||
if(clk8_en_p && loadSoundD) begin
|
||||
if(snd_ena) audio_latch <= 8'h00;
|
||||
else audio_latch <= memoryDataIn[15:8] - 8'd128;
|
||||
end
|
||||
@@ -106,6 +112,8 @@ module dataController_top(
|
||||
always @(posedge clk32)
|
||||
clkPhase <= clkPhase + 2'd1;
|
||||
assign clk8 = clkPhase[1];
|
||||
assign clk8_en_p = clkPhase == 2'b01;
|
||||
assign clk8_en_n = clkPhase == 2'b11;
|
||||
|
||||
// CPU reset generation
|
||||
// For initial CPU reset, RESET and HALT must be asserted for at least 100ms = 800,000 clocks of clk8
|
||||
@@ -117,11 +125,11 @@ module dataController_top(
|
||||
resetDelay <= 20'hFFFFF;
|
||||
end
|
||||
|
||||
always @(posedge clk8 or negedge _systemReset) begin
|
||||
always @(posedge clk32 or negedge _systemReset) begin
|
||||
if (_systemReset == 1'b0) begin
|
||||
resetDelay <= 20'hFFFFF;
|
||||
end
|
||||
else if (isResetting) begin
|
||||
else if (clk8_en_p && isResetting) begin
|
||||
resetDelay <= resetDelay - 1'b1;
|
||||
end
|
||||
end
|
||||
@@ -154,36 +162,41 @@ module dataController_top(
|
||||
|
||||
// Memory-side
|
||||
assign memoryDataOut = cpuDataIn;
|
||||
|
||||
|
||||
// SCSI
|
||||
ncr5380 scsi(
|
||||
.sysclk(clk8),
|
||||
.reset(!_cpuReset),
|
||||
.bus_cs(selectSCSI && cpuBusControl),
|
||||
.bus_we(!_cpuRW),
|
||||
.bus_rs(cpuAddrRegMid),
|
||||
.dack(cpuAddrRegHi[0]), // A9
|
||||
.wdata(cpuDataIn[15:8]),
|
||||
.rdata(scsiDataOut),
|
||||
.clk(clk32),
|
||||
.ce(clk8_en_p),
|
||||
.reset(!_cpuReset),
|
||||
.bus_cs(selectSCSI && cpuBusControl),
|
||||
.bus_we(!_cpuRW),
|
||||
.bus_rs(cpuAddrRegMid),
|
||||
.dack(cpuAddrRegHi[0]), // A9
|
||||
.wdata(cpuDataIn[15:8]),
|
||||
.rdata(scsiDataOut),
|
||||
|
||||
// connections to io controller
|
||||
.img_mounted( img_mounted ),
|
||||
.img_size( img_size ),
|
||||
.io_lba ( io_lba ),
|
||||
.io_rd ( io_rd ),
|
||||
.io_wr ( io_wr ),
|
||||
.io_ack ( io_ack ),
|
||||
.io_din ( io_din ),
|
||||
.io_din_strobe ( io_din_strobe ),
|
||||
.io_dout ( io_dout ),
|
||||
.io_dout_strobe ( io_dout_strobe )
|
||||
|
||||
.sd_buff_addr(sd_buff_addr),
|
||||
.sd_buff_dout(sd_buff_dout),
|
||||
.sd_buff_din(sd_buff_din),
|
||||
.sd_buff_wr(sd_buff_wr)
|
||||
);
|
||||
|
||||
|
||||
// VIA
|
||||
wire [2:0] snd_vol;
|
||||
wire snd_ena;
|
||||
|
||||
via v(
|
||||
.clk8(clk8),
|
||||
.clk32(clk32),
|
||||
.clk8_en_p(clk8_en_p),
|
||||
.clk8_en_n(clk8_en_n),
|
||||
._reset(_cpuReset),
|
||||
.selectVIA(selectVIA && cpuBusControl),
|
||||
._cpuRW(_cpuRW),
|
||||
@@ -213,7 +226,9 @@ module dataController_top(
|
||||
|
||||
// IWM
|
||||
iwm i(
|
||||
.clk8(clk8),
|
||||
.clk(clk32),
|
||||
.cep(clk8_en_p),
|
||||
.cen(clk8_en_n),
|
||||
._reset(_cpuReset),
|
||||
.selectIWM(selectIWM && cpuBusControl),
|
||||
._cpuRW(_cpuRW),
|
||||
@@ -225,7 +240,9 @@ module dataController_top(
|
||||
.insertDisk(insertDisk),
|
||||
.diskSides(diskSides),
|
||||
.diskEject(diskEject),
|
||||
|
||||
.diskMotor(diskMotor),
|
||||
.diskAct(diskAct),
|
||||
|
||||
.dskReadAddrInt(dskReadAddrInt),
|
||||
.dskReadAckInt(dskReadAckInt),
|
||||
.dskReadAddrExt(dskReadAddrExt),
|
||||
@@ -235,14 +252,16 @@ module dataController_top(
|
||||
|
||||
// SCC
|
||||
scc s(
|
||||
.sysclk(clk8),
|
||||
.reset_hw(~_cpuReset),
|
||||
.cs(selectSCC && (_cpuLDS == 1'b0 || _cpuUDS == 1'b0) && cpuBusControl),
|
||||
.we(!_cpuRW),
|
||||
.rs(cpuAddrRegLo),
|
||||
.wdata(cpuDataIn[15:8]),
|
||||
.rdata(sccDataOut),
|
||||
._irq(_sccIrq),
|
||||
.clk(clk32),
|
||||
.cep(clk8_en_p),
|
||||
.cen(clk8_en_n),
|
||||
.reset_hw(~_cpuReset),
|
||||
.cs(selectSCC && (_cpuLDS == 1'b0 || _cpuUDS == 1'b0) && cpuBusControl),
|
||||
.we(!_cpuRW),
|
||||
.rs(cpuAddrRegLo),
|
||||
.wdata(cpuDataIn[15:8]),
|
||||
.rdata(sccDataOut),
|
||||
._irq(_sccIrq),
|
||||
.dcd_a(mouseX1),
|
||||
.dcd_b(mouseY1),
|
||||
.wreq(sccWReq));
|
||||
@@ -257,7 +276,8 @@ module dataController_top(
|
||||
|
||||
// Mouse
|
||||
ps2_mouse mouse(
|
||||
.sysclk(clk8),
|
||||
.sysclk(clk32),
|
||||
.clk_en(clk8_en_p),
|
||||
.reset(~_cpuReset),
|
||||
.ps2dat(mouseData),
|
||||
.ps2clk(mouseClk),
|
||||
@@ -267,14 +287,15 @@ module dataController_top(
|
||||
.y2(mouseY2),
|
||||
.button(mouseButton));
|
||||
|
||||
wire [7:0] kbd_in_data;
|
||||
wire [7:0] kbd_in_data;
|
||||
wire kbd_in_strobe;
|
||||
wire [7:0] kbd_out_data;
|
||||
wire [7:0] kbd_out_data;
|
||||
wire kbd_out_strobe;
|
||||
|
||||
|
||||
// Keyboard
|
||||
ps2_kbd kbd(
|
||||
.sysclk(clk8),
|
||||
.sysclk(clk32),
|
||||
.clk_en(clk8_en_p),
|
||||
.reset(~_cpuReset),
|
||||
.ps2dat(keyData),
|
||||
.ps2clk(keyClk),
|
||||
|
||||
@@ -58,8 +58,12 @@
|
||||
`define DRIVE_REG_INSTALLED 14 /* R: drive present (0 = yes ??) */
|
||||
`define DRIVE_REG_DRVIN 15 /* R: 400K/800k: drive present (0=yes, 1=no), Superdrive: disk capacity (0=HD, 1=DD) */
|
||||
|
||||
module floppy(
|
||||
input clk8,
|
||||
module floppy
|
||||
(
|
||||
input clk,
|
||||
input cep,
|
||||
input cen,
|
||||
|
||||
input _reset,
|
||||
input ca0, // PH0
|
||||
input ca1, // PH1
|
||||
@@ -76,11 +80,17 @@ module floppy(
|
||||
input diskSides,
|
||||
output diskEject,
|
||||
|
||||
output motor,
|
||||
output act,
|
||||
|
||||
output [21:0] dskReadAddr,
|
||||
input dskReadAck,
|
||||
input [7:0] dskReadData
|
||||
);
|
||||
|
||||
assign motor = ~driveRegs[`DRIVE_REG_MOTORON];
|
||||
assign act = lstrbEdge;
|
||||
|
||||
reg [15:0] driveRegs;
|
||||
reg [6:0] driveTrack;
|
||||
reg driveSide;
|
||||
@@ -107,20 +117,24 @@ module floppy(
|
||||
};
|
||||
|
||||
reg dskReadAckD;
|
||||
always @(negedge clk8)
|
||||
dskReadAckD <= dskReadAck;
|
||||
always @(posedge clk) if(cen) dskReadAckD <= dskReadAck;
|
||||
|
||||
// latch incoming data
|
||||
reg [7:0] dskReadDataLatch;
|
||||
always @(posedge clk8)
|
||||
if(dskReadAckD)
|
||||
dskReadDataLatch <= dskReadData;
|
||||
always @(posedge clk) if(cep && dskReadAckD) dskReadDataLatch <= dskReadData;
|
||||
|
||||
wire [7:0] dskReadDataEnc;
|
||||
|
||||
reg old_newByteReady;
|
||||
always @(posedge clk) old_newByteReady <= newByteReady;
|
||||
|
||||
// include track encoder
|
||||
floppy_track_encoder enc (
|
||||
.clk ( newByteReady ),
|
||||
floppy_track_encoder enc
|
||||
(
|
||||
|
||||
.clk ( clk ),
|
||||
.ready ( ~old_newByteReady & newByteReady ),
|
||||
|
||||
.rst ( !_reset ),
|
||||
|
||||
.side ( driveSide ),
|
||||
@@ -128,8 +142,6 @@ module floppy(
|
||||
.track ( driveTrack ),
|
||||
|
||||
.addr ( dskReadAddr ),
|
||||
|
||||
.strobe ( ),
|
||||
.idata ( dskReadDataLatch ),
|
||||
.odata ( dskReadDataEnc )
|
||||
);
|
||||
@@ -144,8 +156,8 @@ module floppy(
|
||||
reg [6:0] diskDataByteTimer;
|
||||
reg [7:0] diskImageData;
|
||||
reg readyToAdvanceHead;
|
||||
always @(posedge clk8 or negedge _reset) begin
|
||||
if (_reset == 1'b0) begin
|
||||
always @(posedge clk or negedge _reset) begin
|
||||
if (_reset == 0) begin
|
||||
driveSide <= 0;
|
||||
diskImageData <= 8'h00;
|
||||
diskDataIn <= 8'hFF;
|
||||
@@ -154,10 +166,11 @@ module floppy(
|
||||
newByteReady <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
if(cep) begin
|
||||
// at time 0, latch a new byte and advance the drive head
|
||||
if (diskDataByteTimer == 0 && readyToAdvanceHead && diskImageData != 0) begin
|
||||
diskDataIn <= diskImageData;
|
||||
newByteReady <= 1'b1;
|
||||
newByteReady <= 1;
|
||||
diskDataByteTimer <= 1; // make timer run again
|
||||
|
||||
// clear diskImageData after it's used, so we can tell when we get a new one from the disk
|
||||
@@ -194,11 +207,11 @@ module floppy(
|
||||
driveSide <= 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// create a signal on the falling edge of lstrb
|
||||
reg lstrbPrev;
|
||||
always @(posedge clk8)
|
||||
lstrbPrev <= lstrb;
|
||||
always @(posedge clk) if(cep) lstrbPrev <= lstrb;
|
||||
|
||||
wire lstrbEdge = lstrb == 1'b0 && lstrbPrev == 1'b1;
|
||||
|
||||
@@ -209,11 +222,11 @@ module floppy(
|
||||
wire [2:0] driveWriteAddr = {ca1,ca0,SEL};
|
||||
|
||||
// DRIVE_REG_DIRTN 0 /* R/W: step direction (0=toward track 79, 1=toward track 0) */
|
||||
always @(posedge clk8 or negedge _reset) begin
|
||||
always @(posedge clk or negedge _reset) begin
|
||||
if (_reset == 1'b0) begin
|
||||
driveRegs[`DRIVE_REG_DIRTN] <= 1'b0;
|
||||
end
|
||||
else if (_enable == 1'b0 && lstrbEdge == 1'b1 && driveWriteAddr == `DRIVE_REG_DIRTN) begin
|
||||
else if(cep && _enable == 1'b0 && lstrbEdge == 1'b1 && driveWriteAddr == `DRIVE_REG_DIRTN) begin
|
||||
driveRegs[`DRIVE_REG_DIRTN] <= ca2;
|
||||
end
|
||||
end
|
||||
@@ -225,33 +238,35 @@ module floppy(
|
||||
reg [23:0] ejectIndicatorTimer;
|
||||
assign diskEject = (ejectIndicatorTimer != 0);
|
||||
|
||||
always @(posedge clk8 or negedge _reset) begin
|
||||
always @(posedge clk or negedge _reset) begin
|
||||
if (_reset == 1'b0) begin
|
||||
driveRegs[`DRIVE_REG_CSTIN] <= 1'b1;
|
||||
ejectIndicatorTimer <= 24'd0;
|
||||
end
|
||||
else if (_enable == 1'b0 && lstrbEdge == 1'b1 && driveWriteAddr == `DRIVE_REG_EJECT && ca2 == 1'b1) begin
|
||||
// eject the disk
|
||||
driveRegs[`DRIVE_REG_CSTIN] <= 1'b1;
|
||||
ejectIndicatorTimer <= 24'hFFFFFF;
|
||||
end
|
||||
else if (insertDisk) begin
|
||||
// insert a disk
|
||||
driveRegs[`DRIVE_REG_CSTIN] <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
if (ejectIndicatorTimer != 0)
|
||||
ejectIndicatorTimer <= ejectIndicatorTimer - 1'b1;
|
||||
else if(cep) begin
|
||||
if (_enable == 1'b0 && lstrbEdge == 1'b1 && driveWriteAddr == `DRIVE_REG_EJECT && ca2 == 1'b1) begin
|
||||
// eject the disk
|
||||
driveRegs[`DRIVE_REG_CSTIN] <= 1'b1;
|
||||
ejectIndicatorTimer <= 24'hFFFFFF;
|
||||
end
|
||||
else if (insertDisk) begin
|
||||
// insert a disk
|
||||
driveRegs[`DRIVE_REG_CSTIN] <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
if (ejectIndicatorTimer != 0)
|
||||
ejectIndicatorTimer <= ejectIndicatorTimer - 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
//`define DRIVE_REG_STEP 2 /* R: drive head stepping (1 = complete) */
|
||||
/* W: 0 = step drive head */
|
||||
always @(posedge clk8 or negedge _reset) begin
|
||||
always @(posedge clk or negedge _reset) begin
|
||||
if (_reset == 1'b0) begin
|
||||
driveTrack <= 0;
|
||||
end
|
||||
else if (_enable == 1'b0 && lstrbEdge == 1'b1 && driveWriteAddr == `DRIVE_REG_STEP && ca2 == 1'b0) begin
|
||||
else if(cep && _enable == 1'b0 && lstrbEdge == 1'b1 && driveWriteAddr == `DRIVE_REG_STEP && ca2 == 1'b0) begin
|
||||
if (driveRegs[`DRIVE_REG_DIRTN] == 1'b0 && driveTrack != 7'h4F) begin
|
||||
driveTrack <= driveTrack + 1'b1;
|
||||
end
|
||||
@@ -262,11 +277,11 @@ module floppy(
|
||||
end
|
||||
|
||||
// DRIVE_REG_MOTORON 4 /* R/W: 0 = motor on */
|
||||
always @(posedge clk8 or negedge _reset) begin
|
||||
always @(posedge clk or negedge _reset) begin
|
||||
if (_reset == 1'b0) begin
|
||||
driveRegs[`DRIVE_REG_MOTORON] <= 1'b1;
|
||||
end
|
||||
else if (_enable == 1'b0 && lstrbEdge == 1'b1 && driveWriteAddr == `DRIVE_REG_MOTORON) begin
|
||||
else if (cep && _enable == 1'b0 && lstrbEdge == 1'b1 && driveWriteAddr == `DRIVE_REG_MOTORON) begin
|
||||
driveRegs[`DRIVE_REG_MOTORON] <= ca2;
|
||||
end
|
||||
end
|
||||
@@ -307,12 +322,12 @@ module floppy(
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk8 or negedge _reset) begin
|
||||
always @(posedge clk or negedge _reset) begin
|
||||
if (_reset == 1'b0) begin
|
||||
driveRegs[`DRIVE_REG_TACH] <= 1'b0;
|
||||
driveTachTimer <= 0;
|
||||
end
|
||||
else begin
|
||||
else if(cep) begin
|
||||
if (driveTachTimer == driveTachPeriod) begin
|
||||
driveTachTimer <= 0;
|
||||
driveRegs[`DRIVE_REG_TACH] <= ~driveRegs[`DRIVE_REG_TACH];
|
||||
|
||||
@@ -12,23 +12,26 @@
|
||||
module floppy_track_encoder (
|
||||
// system signals
|
||||
input clk, // clock at which data bytes are delivered via odata
|
||||
input ready,
|
||||
input rst,
|
||||
|
||||
input side,
|
||||
input sides,
|
||||
input [6:0] track, // current track
|
||||
|
||||
output [21:0] addr, // address to fetch from
|
||||
output reg [21:0] addr, // address to fetch from
|
||||
input [7:0] idata,
|
||||
|
||||
output [7:0] odata
|
||||
);
|
||||
|
||||
assign addr =
|
||||
{ 3'b00, soff, 9'd0 } + // sector offset * 512 for two sides
|
||||
(sides?{ 3'b00, soff, 9'd0 }:22'd0) + // another sector offset * 512 for two sides
|
||||
(side?{ 9'd0, spt, 9'd0 }:22'd0) + // side * sectors * 512
|
||||
{ 9'd0, sector, src_offset }; // offset within track
|
||||
always @(posedge clk) begin
|
||||
addr <=
|
||||
{ 3'b00, soff, 9'd0 } + // sector offset * 512 for two sides
|
||||
(sides?{ 3'b00, soff, 9'd0 }:22'd0) + // another sector offset * 512 for two sides
|
||||
(side?{ 9'd0, spt, 9'd0 }:22'd0) + // side * sectors * 512
|
||||
{ 9'd0, sector, src_offset }; // offset within track
|
||||
end
|
||||
|
||||
// number of sectors on current track
|
||||
wire [3:0] spt =
|
||||
@@ -189,11 +192,9 @@ assign addr =
|
||||
((state == STATE_DATA) && (count < 683-4-1)))
|
||||
&& (cnt != 3);
|
||||
|
||||
reg [7:0] data_latch;
|
||||
always @(posedge clk)
|
||||
if(strobe)
|
||||
data_latch <= idata;
|
||||
|
||||
reg [7:0] data_latch;
|
||||
always @(posedge clk) if(ready && strobe) data_latch <= idata;
|
||||
|
||||
always @(posedge clk or posedge nibbler_reset) begin
|
||||
if(nibbler_reset) begin
|
||||
c1 <= 8'h00;
|
||||
@@ -205,7 +206,7 @@ always @(posedge clk or posedge nibbler_reset) begin
|
||||
nib_xor_0 <= 8'h00;
|
||||
nib_xor_1 <= 8'h00;
|
||||
nib_xor_2 <= 8'h00;
|
||||
end else if((state == STATE_DPRE) || (state == STATE_DATA)) begin
|
||||
end else if(ready && ((state == STATE_DPRE) || (state == STATE_DATA))) begin
|
||||
cnt <= cnt + 2'd1;
|
||||
|
||||
// memory read during cnt 0-3
|
||||
@@ -263,7 +264,7 @@ always @(posedge clk or posedge rst) begin
|
||||
state <= STATE_SYN0;
|
||||
sector <= 4'd0;
|
||||
src_offset <= 9'd0;
|
||||
end else begin
|
||||
end else if(ready) begin
|
||||
count <= count + 10'd1;
|
||||
|
||||
if(strobe)
|
||||
|
||||
@@ -29,8 +29,12 @@
|
||||
being defined as both /DEV being low and D7 (the MSB) outputting a one from the read data register for at least one fclk period.
|
||||
*/
|
||||
|
||||
module iwm(
|
||||
input clk8,
|
||||
module iwm
|
||||
(
|
||||
input clk,
|
||||
input cep,
|
||||
input cen,
|
||||
|
||||
input _reset,
|
||||
input selectIWM,
|
||||
input _cpuRW,
|
||||
@@ -43,6 +47,9 @@ module iwm(
|
||||
output [1:0] diskEject,
|
||||
input [1:0] diskSides,
|
||||
|
||||
output [1:0] diskMotor,
|
||||
output [1:0] diskAct,
|
||||
|
||||
// interface to fetch data for internal drive
|
||||
output [21:0] dskReadAddrInt,
|
||||
input dskReadAckInt,
|
||||
@@ -75,8 +82,12 @@ module iwm(
|
||||
wire [7:0] readDataExt;
|
||||
wire senseExt = readDataExt[7]; // bit 7 doubles as the sense line here
|
||||
|
||||
floppy floppyInt(
|
||||
.clk8(clk8),
|
||||
floppy floppyInt
|
||||
(
|
||||
.clk(clk),
|
||||
.cep(cep),
|
||||
.cen(cen),
|
||||
|
||||
._reset(_reset),
|
||||
.ca0(ca0),
|
||||
.ca1(ca1),
|
||||
@@ -91,14 +102,21 @@ module iwm(
|
||||
.insertDisk(insertDisk[0]),
|
||||
.diskSides(diskSides[0]),
|
||||
.diskEject(diskEject[0]),
|
||||
|
||||
|
||||
.motor(diskMotor[0]),
|
||||
.act(diskAct[0]),
|
||||
|
||||
.dskReadAddr(dskReadAddrInt),
|
||||
.dskReadAck(dskReadAckInt),
|
||||
.dskReadData(dskReadData)
|
||||
);
|
||||
|
||||
floppy floppyExt(
|
||||
.clk8(clk8),
|
||||
floppy floppyExt
|
||||
(
|
||||
.clk(clk),
|
||||
.cep(cep),
|
||||
.cen(cen),
|
||||
|
||||
._reset(_reset),
|
||||
.ca0(ca0),
|
||||
.ca1(ca1),
|
||||
@@ -114,6 +132,9 @@ module iwm(
|
||||
.diskSides(diskSides[1]),
|
||||
.diskEject(diskEject[1]),
|
||||
|
||||
.motor(diskMotor[1]),
|
||||
.act(diskAct[1]),
|
||||
|
||||
.dskReadAddr(dskReadAddrExt),
|
||||
.dskReadAck(dskReadAckExt),
|
||||
.dskReadData(dskReadData)
|
||||
@@ -185,7 +206,7 @@ module iwm(
|
||||
end
|
||||
|
||||
// update IWM bit registers
|
||||
always @(negedge clk8 or negedge _reset) begin
|
||||
always @(posedge clk or negedge _reset) begin
|
||||
if (_reset == 1'b0) begin
|
||||
ca0 <= 0;
|
||||
ca1 <= 0;
|
||||
@@ -197,7 +218,7 @@ module iwm(
|
||||
q6 <= 0;
|
||||
q7 <= 0;
|
||||
end
|
||||
else begin
|
||||
else if(cen) begin
|
||||
ca0 <= ca0Next;
|
||||
ca1 <= ca1Next;
|
||||
ca2 <= ca2Next;
|
||||
@@ -228,12 +249,12 @@ module iwm(
|
||||
end
|
||||
|
||||
// write IWM state
|
||||
always @(negedge clk8 or negedge _reset) begin
|
||||
always @(posedge clk or negedge _reset) begin
|
||||
if (_reset == 1'b0) begin
|
||||
iwmMode <= 0;
|
||||
writeData <= 0;
|
||||
end
|
||||
else begin
|
||||
else if(cen) begin
|
||||
if (_cpuRW == 0 && selectIWM == 1'b1 && _cpuLDS == 1'b0) begin
|
||||
// writing to any IWM address modifies state as selected by Q7 and Q6
|
||||
case ({q7Next,q6Next})
|
||||
@@ -252,13 +273,13 @@ module iwm(
|
||||
wire iwmRead = (_cpuRW == 1'b1 && selectIWM == 1'b1 && _cpuLDS == 1'b0);
|
||||
reg iwmReadPrev;
|
||||
reg [3:0] readLatchClearTimer;
|
||||
always @(negedge clk8 or negedge _reset) begin
|
||||
always @(posedge clk or negedge _reset) begin
|
||||
if (_reset == 1'b0) begin
|
||||
readDataLatch <= 0;
|
||||
readLatchClearTimer <= 0;
|
||||
iwmReadPrev <= 0;
|
||||
end
|
||||
else begin
|
||||
else if(cen) begin
|
||||
// a countdown timer governs how long after a data latch read before the latch is cleared
|
||||
if (readLatchClearTimer != 0) begin
|
||||
readLatchClearTimer <= readLatchClearTimer - 1'b1;
|
||||
|
||||
@@ -13,7 +13,7 @@
|
||||
`define RREG_RST 3'h7 /* Reset */
|
||||
|
||||
/* Write registers */
|
||||
`define WREG_ODR 3'h0 /* Ouptut data */
|
||||
`define WREG_ODR 3'h0 /* Output data */
|
||||
`define WREG_ICR 3'h1 /* Initiator Command */
|
||||
`define WREG_MR 3'h2 /* Mode register */
|
||||
`define WREG_TCR 3'h3 /* Target Command */
|
||||
@@ -42,148 +42,170 @@
|
||||
`define TCR_A_CD 1
|
||||
`define TCR_A_IO 0
|
||||
|
||||
module ncr5380(input sysclk,
|
||||
input reset,
|
||||
|
||||
/* Bus interface. 3-bit address, to be wired
|
||||
* appropriately upstream (to A4..A6) plus one
|
||||
* more bit (A9) wired as dack.
|
||||
*/
|
||||
input bus_cs,
|
||||
input bus_we,
|
||||
input [2:0] bus_rs,
|
||||
input dack,
|
||||
input [7:0] wdata,
|
||||
output [7:0] rdata,
|
||||
|
||||
|
||||
// connections to io controller
|
||||
output [31:0] io_lba,
|
||||
output io_rd,
|
||||
output io_wr,
|
||||
input io_ack,
|
||||
output [7:0] io_dout,
|
||||
input io_dout_strobe,
|
||||
input [7:0] io_din,
|
||||
input io_din_strobe
|
||||
);
|
||||
|
||||
reg [7:0] mr; /* Mode Register */
|
||||
reg [7:0] icr; /* Initiator Command Register */
|
||||
reg [3:0] tcr; /* Target Command Register */
|
||||
wire [7:0] csr; /* SCSI bus status register */
|
||||
|
||||
/* Data in and out latches and associated
|
||||
* control logic for DMA
|
||||
*/
|
||||
wire [7:0] din;
|
||||
reg [7:0] dout;
|
||||
reg dphase;
|
||||
reg dma_en;
|
||||
|
||||
/* --- Main host-side interface --- */
|
||||
|
||||
/* Register & DMA accesses decodes */
|
||||
wire dma_rd = bus_cs & dack & ~bus_we;
|
||||
wire dma_wr = bus_cs & dack & bus_we;
|
||||
wire reg_rd = bus_cs & ~dack & ~bus_we;
|
||||
wire reg_wr = bus_cs & ~dack & bus_we;
|
||||
|
||||
/* System bus reads */
|
||||
assign rdata = dack ? cur_data :
|
||||
bus_rs == `RREG_CDR ? cur_data :
|
||||
bus_rs == `RREG_ICR ? icr_read :
|
||||
bus_rs == `RREG_MR ? mr :
|
||||
bus_rs == `RREG_TCR ? { 4'h0, tcr } :
|
||||
bus_rs == `RREG_CSR ? csr :
|
||||
bus_rs == `RREG_BSR ? bsr :
|
||||
bus_rs == `RREG_IDR ? cur_data :
|
||||
bus_rs == `RREG_RST ? 8'hff :
|
||||
8'hff;
|
||||
|
||||
module ncr5380
|
||||
(
|
||||
input clk,
|
||||
input ce,
|
||||
|
||||
input reset,
|
||||
|
||||
/* Bus interface. 3-bit address, to be wired
|
||||
* appropriately upstream (to A4..A6) plus one
|
||||
* more bit (A9) wired as dack.
|
||||
*/
|
||||
input bus_cs,
|
||||
input bus_we,
|
||||
input [2:0] bus_rs,
|
||||
input dack,
|
||||
input [7:0] wdata,
|
||||
output [7:0] rdata,
|
||||
|
||||
|
||||
// connections to io controller
|
||||
input [1:0] img_mounted,
|
||||
input [31:0] img_size,
|
||||
|
||||
output [15:0] io_req_type,
|
||||
output [31:0] io_lba,
|
||||
output [1:0] io_rd,
|
||||
output [1:0] io_wr,
|
||||
input io_ack,
|
||||
|
||||
input [8:0] sd_buff_addr,
|
||||
input [7:0] sd_buff_dout,
|
||||
output [7:0] sd_buff_din,
|
||||
input sd_buff_wr
|
||||
);
|
||||
|
||||
reg [7:0] mr; /* Mode Register */
|
||||
reg [7:0] icr; /* Initiator Command Register */
|
||||
reg [3:0] tcr; /* Target Command Register */
|
||||
wire [7:0] csr; /* SCSI bus status register */
|
||||
|
||||
/* Data in and out latches and associated
|
||||
* control logic for DMA
|
||||
*/
|
||||
wire [7:0] din;
|
||||
reg [7:0] dout;
|
||||
reg dphase;
|
||||
reg dma_en;
|
||||
|
||||
/* --- Main host-side interface --- */
|
||||
|
||||
/* Register & DMA accesses decodes */
|
||||
reg dma_rd;
|
||||
reg dma_wr;
|
||||
reg reg_wr;
|
||||
|
||||
wire i_dma_rd = bus_cs & dack & ~bus_we;
|
||||
wire i_dma_wr = bus_cs & dack & bus_we;
|
||||
wire i_reg_wr = bus_cs & ~dack & bus_we;
|
||||
|
||||
always @(posedge clk) begin
|
||||
reg old_dma_rd, old_dma_wr, old_reg_wr;
|
||||
|
||||
old_dma_rd <= i_dma_rd;
|
||||
old_dma_wr <= i_dma_wr;
|
||||
old_reg_wr <= i_reg_wr;
|
||||
|
||||
dma_rd <= 0;
|
||||
dma_wr <= 0;
|
||||
reg_wr <= 0;
|
||||
|
||||
if(~old_dma_wr & i_dma_wr) dma_wr <= 1;
|
||||
else if(~old_dma_rd & i_dma_rd) dma_rd <= 1;
|
||||
else if(~old_reg_wr & i_reg_wr) reg_wr <= 1;
|
||||
end
|
||||
|
||||
/* System bus reads */
|
||||
assign rdata = dack ? cur_data :
|
||||
bus_rs == `RREG_CDR ? cur_data :
|
||||
bus_rs == `RREG_ICR ? icr_read :
|
||||
bus_rs == `RREG_MR ? mr :
|
||||
bus_rs == `RREG_TCR ? { 4'h0, tcr } :
|
||||
bus_rs == `RREG_CSR ? csr :
|
||||
bus_rs == `RREG_BSR ? bsr :
|
||||
bus_rs == `RREG_IDR ? cur_data :
|
||||
bus_rs == `RREG_RST ? 8'hff :
|
||||
8'hff;
|
||||
|
||||
/* DMA handhsaking logic. Two phase logic, in phase 0
|
||||
* DRQ follows SCSI _REQ until we see DACK. In phase 1
|
||||
* we just wait for SCSI _REQ to go down and go back to
|
||||
* phase 0. We assert SCSI _ACK in phase 1.
|
||||
*/
|
||||
always@(negedge sysclk or posedge reset) begin
|
||||
if (reset) begin
|
||||
dphase <= 0;
|
||||
end else begin
|
||||
if (!dma_en) begin
|
||||
dphase <= 0;
|
||||
end else if (dphase == 0) begin
|
||||
/* Be careful to do that in bus phase 1,
|
||||
* not phase 0, or we would incorrectly
|
||||
* assert bus_hold and lock up the system
|
||||
*/
|
||||
if ((dma_rd || dma_wr) && scsi_req) begin
|
||||
dphase <= 1;
|
||||
end
|
||||
end else if (!scsi_req) begin
|
||||
dphase <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
always@(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
dphase <= 0;
|
||||
end else begin
|
||||
if (!dma_en) begin
|
||||
dphase <= 0;
|
||||
end else if (dphase == 0) begin
|
||||
/* Be careful to do that in bus phase 1,
|
||||
* not phase 0, or we would incorrectly
|
||||
* assert bus_hold and lock up the system
|
||||
*/
|
||||
if ((dma_rd || dma_wr) && scsi_req) begin
|
||||
dphase <= 1;
|
||||
end
|
||||
end else if (!scsi_req) begin
|
||||
dphase <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
/* Data out latch (in DMA mode, this is one cycle after we've
|
||||
* asserted ACK)
|
||||
/* Data out latch (in DMA mode, this is one cycle after we've
|
||||
* asserted ACK)
|
||||
*/
|
||||
always@(posedge clk) if((reg_wr && bus_rs == `WREG_ODR) || dma_wr) dout <= wdata;
|
||||
|
||||
/* Current data register. Simplified logic: We loop back the
|
||||
* output data if we are asserting the bus, else we get the
|
||||
* input latch
|
||||
*/
|
||||
always@(negedge sysclk)
|
||||
if ((reg_wr && bus_rs == `WREG_ODR) || dma_wr)
|
||||
dout <= wdata;
|
||||
wire [7:0] cur_data = out_en ? dout : din;
|
||||
|
||||
/* Current data register. Simplified logic: We loop back the
|
||||
* output data if we are asserting the bus, else we get the
|
||||
* input latch
|
||||
*/
|
||||
wire [7:0] cur_data = out_en ? dout : din;
|
||||
/* Logic for "asserting the bus" simplified */
|
||||
wire out_en = icr[`ICR_A_DATA] | mr[`MR_ARB];
|
||||
|
||||
/* Logic for "asserting the bus" simplified */
|
||||
wire out_en = icr[`ICR_A_DATA] | mr[`MR_ARB];
|
||||
/* ICR read wires */
|
||||
wire [7:0] icr_read = { icr[`ICR_A_RST],
|
||||
icr_aip,
|
||||
icr_la,
|
||||
icr[`ICR_A_ACK],
|
||||
icr[`ICR_A_BSY],
|
||||
icr[`ICR_A_SEL],
|
||||
icr[`ICR_A_ATN],
|
||||
icr[`ICR_A_DATA] };
|
||||
|
||||
/* ICR write */
|
||||
always@(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
icr <= 0;
|
||||
end else if (reg_wr && (bus_rs == `WREG_ICR)) begin
|
||||
icr <= wdata;
|
||||
end
|
||||
end
|
||||
|
||||
/* ICR read wires */
|
||||
wire [7:0] icr_read = { icr[`ICR_A_RST],
|
||||
icr_aip,
|
||||
icr_la,
|
||||
icr[`ICR_A_ACK],
|
||||
icr[`ICR_A_BSY],
|
||||
icr[`ICR_A_SEL],
|
||||
icr[`ICR_A_ATN],
|
||||
icr[`ICR_A_DATA] };
|
||||
/* MR write */
|
||||
always@(posedge clk or posedge reset) begin
|
||||
if (reset) mr <= 8'b0;
|
||||
else if (reg_wr && (bus_rs == `WREG_MR)) mr <= wdata;
|
||||
end
|
||||
|
||||
/* ICR write */
|
||||
always@(negedge sysclk or posedge reset) begin
|
||||
if (reset) begin
|
||||
icr <= 0;
|
||||
end else if (reg_wr && (bus_rs == `WREG_ICR)) begin
|
||||
icr <= wdata;
|
||||
end
|
||||
end
|
||||
/* TCR write */
|
||||
always@(posedge clk or posedge reset) begin
|
||||
if (reset) tcr <= 4'b0;
|
||||
else if (reg_wr && (bus_rs == `WREG_TCR)) tcr <= wdata[3:0];
|
||||
end
|
||||
|
||||
/* MR write */
|
||||
always@(negedge sysclk or posedge reset) begin
|
||||
if (reset)
|
||||
mr <= 8'b0;
|
||||
else if (reg_wr && (bus_rs == `WREG_MR))
|
||||
mr <= wdata;
|
||||
end
|
||||
|
||||
/* TCR write */
|
||||
always@(negedge sysclk or posedge reset) begin
|
||||
if (reset)
|
||||
tcr <= 4'b0;
|
||||
else if (reg_wr && (bus_rs == `WREG_TCR))
|
||||
tcr <= wdata[3:0];
|
||||
end
|
||||
|
||||
/* DMA start send & receive registers. We currently ignore
|
||||
* the direction.
|
||||
*/
|
||||
always@(negedge sysclk or posedge reset) begin
|
||||
if (reset) begin
|
||||
/* DMA start send & receive registers. We currently ignore
|
||||
* the direction.
|
||||
*/
|
||||
always@(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
dma_en <= 0;
|
||||
end else begin
|
||||
end else begin
|
||||
if (!mr[`MR_DMA_MODE]) begin
|
||||
dma_en <= 0;
|
||||
end else if (reg_wr && (bus_rs == `WREG_DMAS)) begin
|
||||
@@ -191,87 +213,155 @@ module ncr5380(input sysclk,
|
||||
end else if (reg_wr && (bus_rs == `WREG_IDMAR)) begin
|
||||
dma_en <= 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
/* CSR (read only). We don't do parity */
|
||||
assign csr = { scsi_rst, scsi_bsy, scsi_req, scsi_msg,
|
||||
scsi_cd, scsi_io, scsi_sel, 1'b0 };
|
||||
|
||||
/* Bus and Status register */
|
||||
/* BSR (read only). We don't do a few things... */
|
||||
wire bsr_eodma = 1'b0; /* We don't do EOP */
|
||||
wire bsr_dmarq = scsi_req & ~dphase & dma_en;
|
||||
wire bsr_perr = 1'b0; /* We don't do parity */
|
||||
wire bsr_irq = 1'b0; /* XXX ? Does MacOS use this ? */
|
||||
wire bsr_pmatch =
|
||||
tcr[`TCR_A_MSG] == scsi_msg &&
|
||||
tcr[`TCR_A_CD ] == scsi_cd &&
|
||||
tcr[`TCR_A_IO ] == scsi_io;
|
||||
|
||||
wire bsr_berr = 1'b0; /* XXX ? Does MacOS use this ? */
|
||||
wire [7:0] bsr = { bsr_eodma, bsr_dmarq, bsr_perr, bsr_irq,
|
||||
bsr_pmatch, bsr_berr, scsi_atn, scsi_ack };
|
||||
end
|
||||
end
|
||||
|
||||
/* CSR (read only). We don't do parity */
|
||||
assign csr = { scsi_rst, scsi_bsy, scsi_req, scsi_msg,
|
||||
scsi_cd, scsi_io, scsi_sel, 1'b0 };
|
||||
|
||||
/* Bus and Status register */
|
||||
/* BSR (read only). We don't do a few things... */
|
||||
wire bsr_eodma = 1'b0; /* We don't do EOP */
|
||||
wire bsr_dmarq = scsi_req & dma_en;
|
||||
wire bsr_perr = 1'b0; /* We don't do parity */
|
||||
wire bsr_irq = 1'b0; /* XXX ? Does MacOS use this ? */
|
||||
wire bsr_pmatch =
|
||||
tcr[`TCR_A_MSG] == scsi_msg &&
|
||||
tcr[`TCR_A_CD ] == scsi_cd &&
|
||||
tcr[`TCR_A_IO ] == scsi_io;
|
||||
|
||||
wire bsr_berr = 1'b0; /* XXX ? Does MacOS use this ? */
|
||||
wire [7:0] bsr = { bsr_eodma, bsr_dmarq, bsr_perr, bsr_irq,
|
||||
bsr_pmatch, bsr_berr, scsi_atn, scsi_ack };
|
||||
|
||||
/* --- Simulated SCSI Signals --- */
|
||||
|
||||
/* BSY logic (simplified arbitration, see notes) */
|
||||
wire scsi_bsy =
|
||||
icr[`ICR_A_BSY] |
|
||||
scsi2_bsy |
|
||||
mr[`MR_ARB];
|
||||
|
||||
/* Remains of simplified arbitration logic */
|
||||
wire icr_aip = mr[`MR_ARB];
|
||||
wire icr_la = 0;
|
||||
wire scsi_bsy =
|
||||
icr[`ICR_A_BSY] |
|
||||
scsi2_bsy |
|
||||
//scsi6_bsy |
|
||||
mr[`MR_ARB];
|
||||
|
||||
reg dma_ack;
|
||||
always @(posedge sysclk)
|
||||
dma_ack <= dphase;
|
||||
|
||||
/* Other ORed SCSI signals */
|
||||
wire scsi_sel = icr[`ICR_A_SEL];
|
||||
wire scsi_rst = icr[`ICR_A_RST];
|
||||
wire scsi_ack = icr[`ICR_A_ACK] | dma_ack;
|
||||
wire scsi_atn = icr[`ICR_A_ATN];
|
||||
|
||||
/* Other trivial lines set by target */
|
||||
wire scsi_cd = scsi2_cd;
|
||||
wire scsi_io = scsi2_io;
|
||||
wire scsi_msg = scsi2_msg;
|
||||
wire scsi_req = scsi2_req;
|
||||
/* Remains of simplified arbitration logic */
|
||||
wire icr_aip = mr[`MR_ARB];
|
||||
wire icr_la = 0;
|
||||
|
||||
assign din = scsi2_bsy?scsi2_dout:8'h55;
|
||||
|
||||
// input signals from target 2
|
||||
wire scsi2_bsy, scsi2_msg, scsi2_io, scsi2_cd, scsi2_req;
|
||||
wire [7:0] scsi2_dout;
|
||||
reg dma_ack;
|
||||
always @(posedge clk) if(ce) dma_ack <= dphase;
|
||||
|
||||
// connect a target
|
||||
scsi #(.ID(2)) scsi2(.sysclk ( sysclk ),
|
||||
.rst ( scsi_rst ),
|
||||
.sel ( scsi_sel ),
|
||||
.atn ( scsi_atn ),
|
||||
.bsy ( scsi2_bsy ),
|
||||
.msg ( scsi2_msg ),
|
||||
.cd ( scsi2_cd ),
|
||||
.io ( scsi2_io ),
|
||||
.req ( scsi2_req ),
|
||||
.ack ( scsi_ack ),
|
||||
.dout ( scsi2_dout ),
|
||||
.din ( dout ),
|
||||
/* Other ORed SCSI signals */
|
||||
wire scsi_sel = icr[`ICR_A_SEL];
|
||||
wire scsi_rst = icr[`ICR_A_RST];
|
||||
wire scsi_ack = icr[`ICR_A_ACK] | dma_ack;
|
||||
wire scsi_atn = icr[`ICR_A_ATN];
|
||||
|
||||
wire scsi_cd = scsi2_cd;
|
||||
wire scsi_io = scsi2_io;
|
||||
wire scsi_msg = scsi2_msg;
|
||||
wire scsi_req = scsi2_req;
|
||||
|
||||
assign din = scsi2_dout;
|
||||
|
||||
assign io_lba = io_lba_2;
|
||||
assign sd_buff_din = sd_buff_din_2;
|
||||
/* Other trivial lines set by target */
|
||||
/*
|
||||
wire scsi_cd = (scsi2_bsy) ? scsi2_cd : scsi6_cd;
|
||||
wire scsi_io = (scsi2_bsy) ? scsi2_io : scsi6_io;
|
||||
wire scsi_msg = (scsi2_bsy) ? scsi2_msg : scsi6_msg;
|
||||
wire scsi_req = (scsi2_bsy) ? scsi2_req : scsi6_req;
|
||||
|
||||
assign din = scsi2_bsy ? scsi2_dout :
|
||||
scsi6_bsy ? scsi6_dout :
|
||||
8'h55;
|
||||
|
||||
assign io_lba = (scsi2_bsy) ? io_lba_2 : io_lba_6;
|
||||
assign sd_buff_din = (scsi2_bsy) ? sd_buff_din_2 : sd_buff_din_6;
|
||||
assign io_req_type = 16'h0000; // Not used atm. Could be used for CD-ROM sector requests later. ElectronAsh.
|
||||
*/
|
||||
// input signals from target 2
|
||||
wire scsi2_bsy, scsi2_msg, scsi2_io, scsi2_cd, scsi2_req;
|
||||
wire [7:0] scsi2_dout;
|
||||
|
||||
wire [31:0] io_lba_2;
|
||||
wire [7:0] sd_buff_din_2;
|
||||
|
||||
// connect a target
|
||||
scsi #(.ID(2)) scsi2
|
||||
(
|
||||
.clk ( clk ),
|
||||
.rst ( scsi_rst ),
|
||||
.sel ( scsi_sel ),
|
||||
.atn ( scsi_atn ),
|
||||
|
||||
.ack ( scsi_ack ),
|
||||
|
||||
.bsy ( scsi2_bsy ),
|
||||
.msg ( scsi2_msg ),
|
||||
.cd ( scsi2_cd ),
|
||||
.io ( scsi2_io ),
|
||||
.req ( scsi2_req ),
|
||||
.dout ( scsi2_dout ),
|
||||
|
||||
.din ( dout ),
|
||||
|
||||
// connection to io controller to read and write sectors
|
||||
// to sd card
|
||||
.img_mounted(img_mounted[0]),
|
||||
.img_blocks(img_size[31:9]),
|
||||
.io_lba ( io_lba_2 ),
|
||||
.io_rd ( io_rd[0] ),
|
||||
.io_wr ( io_wr[0] ),
|
||||
.io_ack ( io_ack & scsi2_bsy ),
|
||||
|
||||
.sd_buff_addr( sd_buff_addr ),
|
||||
.sd_buff_dout( sd_buff_dout ),
|
||||
.sd_buff_din( sd_buff_din_2 ),
|
||||
.sd_buff_wr( sd_buff_wr & scsi2_bsy )
|
||||
);
|
||||
|
||||
/*
|
||||
// input signals from target 6
|
||||
wire scsi6_bsy, scsi6_msg, scsi6_io, scsi6_cd, scsi6_req;
|
||||
wire [7:0] scsi6_dout;
|
||||
|
||||
wire [31:0] io_lba_6;
|
||||
wire [7:0] sd_buff_din_6;
|
||||
|
||||
scsi #(.ID(6)) scsi6
|
||||
(
|
||||
.clk ( clk ) , // input clk
|
||||
.rst ( scsi_rst ) , // input rst
|
||||
.sel ( scsi_sel ) , // input sel
|
||||
.atn ( scsi_atn ) , // input atn
|
||||
|
||||
.ack ( scsi_ack ) , // input ack
|
||||
|
||||
.bsy ( scsi6_bsy ) , // output bsy
|
||||
.msg ( scsi6_msg ) , // output msg
|
||||
.cd ( scsi6_cd ) , // output cd
|
||||
.io ( scsi6_io ) , // output io
|
||||
.req ( scsi6_req ) , // output req
|
||||
.dout ( scsi6_dout ) , // output [7:0] dout
|
||||
|
||||
.din ( dout ) , // input [7:0] din
|
||||
|
||||
// connection to io controller to read and write sectors
|
||||
// to sd card
|
||||
.img_mounted( img_mounted[1] ),
|
||||
.img_blocks( img_size[31:9] ),
|
||||
.io_lba ( io_lba_6 ) , // output [31:0] io_lba
|
||||
.io_rd ( io_rd[1] ) , // output io_rd
|
||||
.io_wr ( io_wr[1] ) , // output io_wr
|
||||
.io_ack ( io_ack & scsi6_bsy ) , // input io_ack
|
||||
|
||||
.sd_buff_addr( sd_buff_addr ) , // input [8:0] sd_buff_addr
|
||||
.sd_buff_dout( sd_buff_dout ) , // input [7:0] sd_buff_dout
|
||||
.sd_buff_din( sd_buff_din_6 ) , // output [7:0] sd_buff_din
|
||||
.sd_buff_wr( sd_buff_wr & scsi6_bsy ) // input sd_buff_wr
|
||||
);
|
||||
*/
|
||||
|
||||
// connection to io controller to read and write sectors
|
||||
// to sd card
|
||||
.io_lba ( io_lba ),
|
||||
.io_rd ( io_rd ),
|
||||
.io_wr ( io_wr ),
|
||||
.io_ack ( io_ack ),
|
||||
.io_dout ( io_dout ),
|
||||
.io_dout_strobe ( io_dout_strobe ),
|
||||
.io_din ( io_din ),
|
||||
.io_din_strobe ( io_din_strobe )
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -1,182 +0,0 @@
|
||||
// A simple OSD implementation. Can be hooked up between a cores
|
||||
// VGA output and the physical VGA pins
|
||||
|
||||
module osd (
|
||||
// OSDs pixel clock, should be synchronous to cores pixel clock to
|
||||
// avoid jitter.
|
||||
input pclk,
|
||||
|
||||
// SPI interface
|
||||
input sck,
|
||||
input ss,
|
||||
input sdi,
|
||||
|
||||
// VGA signals coming from core
|
||||
input [5:0] red_in,
|
||||
input [5:0] green_in,
|
||||
input [5:0] blue_in,
|
||||
input hs_in,
|
||||
input vs_in,
|
||||
|
||||
// VGA signals going to video connector
|
||||
output [5:0] red_out,
|
||||
output [5:0] green_out,
|
||||
output [5:0] blue_out,
|
||||
output hs_out,
|
||||
output vs_out
|
||||
);
|
||||
|
||||
parameter OSD_X_OFFSET = 10'd0;
|
||||
parameter OSD_Y_OFFSET = 10'd0;
|
||||
parameter OSD_COLOR = 3'd0;
|
||||
|
||||
localparam OSD_WIDTH = 10'd256;
|
||||
localparam OSD_HEIGHT = 10'd128;
|
||||
|
||||
// *********************************************************************************
|
||||
// spi client
|
||||
// *********************************************************************************
|
||||
|
||||
// this core supports only the display related OSD commands
|
||||
// of the minimig
|
||||
reg [7:0] sbuf;
|
||||
reg [7:0] cmd;
|
||||
reg [4:0] cnt;
|
||||
reg [10:0] bcnt;
|
||||
reg osd_enable;
|
||||
|
||||
reg [7:0] osd_buffer [2047:0]; // the OSD buffer itself
|
||||
|
||||
// the OSD has its own SPI interface to the io controller
|
||||
always@(posedge sck, posedge ss) begin
|
||||
if(ss == 1'b1) begin
|
||||
cnt <= 5'd0;
|
||||
bcnt <= 11'd0;
|
||||
end else begin
|
||||
sbuf <= { sbuf[6:0], sdi};
|
||||
|
||||
// 0:7 is command, rest payload
|
||||
if(cnt < 15)
|
||||
cnt <= cnt + 4'd1;
|
||||
else
|
||||
cnt <= 4'd8;
|
||||
|
||||
if(cnt == 7) begin
|
||||
cmd <= {sbuf[6:0], sdi};
|
||||
|
||||
// lower three command bits are line address
|
||||
bcnt <= { sbuf[1:0], sdi, 8'h00};
|
||||
|
||||
// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
|
||||
if(sbuf[6:3] == 4'b0100)
|
||||
osd_enable <= sdi;
|
||||
end
|
||||
|
||||
// command 0x20: OSDCMDWRITE
|
||||
if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
|
||||
osd_buffer[bcnt] <= {sbuf[6:0], sdi};
|
||||
bcnt <= bcnt + 11'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// *********************************************************************************
|
||||
// video timing and sync polarity anaylsis
|
||||
// *********************************************************************************
|
||||
|
||||
// horizontal counter
|
||||
reg [9:0] h_cnt;
|
||||
reg hsD, hsD2;
|
||||
reg [9:0] hs_low, hs_high;
|
||||
wire hs_pol = hs_high < hs_low;
|
||||
wire [9:0] h_dsp_width = hs_pol?hs_low:hs_high;
|
||||
wire [9:0] h_dsp_ctr = { 1'b0, h_dsp_width[9:1] };
|
||||
|
||||
always @(posedge pclk) begin
|
||||
// bring hsync into local clock domain
|
||||
hsD <= hs_in;
|
||||
hsD2 <= hsD;
|
||||
|
||||
// falling edge of hs_in
|
||||
if(!hsD && hsD2) begin
|
||||
h_cnt <= 10'd0;
|
||||
hs_high <= h_cnt;
|
||||
end
|
||||
|
||||
// rising edge of hs_in
|
||||
else if(hsD && !hsD2) begin
|
||||
h_cnt <= 10'd0;
|
||||
hs_low <= h_cnt;
|
||||
end
|
||||
|
||||
else
|
||||
h_cnt <= h_cnt + 10'd1;
|
||||
end
|
||||
|
||||
// vertical counter
|
||||
reg [9:0] v_cnt;
|
||||
reg vsD, vsD2;
|
||||
reg [9:0] vs_low, vs_high;
|
||||
wire vs_pol = vs_high < vs_low;
|
||||
wire [9:0] v_dsp_width = vs_pol?vs_low:vs_high;
|
||||
wire [9:0] v_dsp_ctr = { 1'b0, v_dsp_width[9:1] };
|
||||
|
||||
always @(posedge hs_in) begin
|
||||
// bring vsync into local clock domain
|
||||
vsD <= vs_in;
|
||||
vsD2 <= vsD;
|
||||
|
||||
// falling edge of vs_in
|
||||
if(!vsD && vsD2) begin
|
||||
v_cnt <= 10'd0;
|
||||
vs_high <= v_cnt;
|
||||
end
|
||||
|
||||
// rising edge of vs_in
|
||||
else if(vsD && !vsD2) begin
|
||||
v_cnt <= 10'd0;
|
||||
vs_low <= v_cnt;
|
||||
end
|
||||
|
||||
else
|
||||
v_cnt <= v_cnt + 10'd1;
|
||||
end
|
||||
|
||||
// area in which OSD is being displayed
|
||||
wire [9:0] h_osd_start = h_dsp_ctr + OSD_X_OFFSET - (OSD_WIDTH >> 1);
|
||||
wire [9:0] h_osd_end = h_dsp_ctr + OSD_X_OFFSET + (OSD_WIDTH >> 1) - 1;
|
||||
wire [9:0] v_osd_start = v_dsp_ctr + OSD_Y_OFFSET - (OSD_HEIGHT >> 1);
|
||||
wire [9:0] v_osd_end = v_dsp_ctr + OSD_Y_OFFSET + (OSD_HEIGHT >> 1) - 1;
|
||||
|
||||
reg h_osd_active, v_osd_active;
|
||||
always @(posedge pclk) begin
|
||||
if(hs_in != hs_pol) begin
|
||||
if(h_cnt == h_osd_start) h_osd_active <= 1'b1;
|
||||
if(h_cnt == h_osd_end) h_osd_active <= 1'b0;
|
||||
end
|
||||
if(vs_in != vs_pol) begin
|
||||
if(v_cnt == v_osd_start) v_osd_active <= 1'b1;
|
||||
if(v_cnt == v_osd_end) v_osd_active <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
wire osd_de = osd_enable && h_osd_active && v_osd_active;
|
||||
|
||||
wire [7:0] osd_hcnt = h_cnt - h_osd_start + 7'd1; // one pixel offset for osd_byte register
|
||||
wire [6:0] osd_vcnt = v_cnt - v_osd_start;
|
||||
|
||||
wire osd_pixel = osd_byte[osd_vcnt[3:1]];
|
||||
|
||||
reg [7:0] osd_byte;
|
||||
always @(posedge pclk)
|
||||
osd_byte <= osd_buffer[{osd_vcnt[6:4], osd_hcnt}];
|
||||
|
||||
wire [2:0] osd_color = OSD_COLOR;
|
||||
assign red_out = !osd_de?red_in: {osd_pixel, osd_pixel, osd_color[2], red_in[5:3] };
|
||||
assign green_out = !osd_de?green_in:{osd_pixel, osd_pixel, osd_color[1], green_in[5:3]};
|
||||
assign blue_out = !osd_de?blue_in: {osd_pixel, osd_pixel, osd_color[0], blue_in[5:3] };
|
||||
|
||||
assign hs_out = hs_in;
|
||||
assign vs_out = vs_in;
|
||||
|
||||
endmodule
|
||||
@@ -14,7 +14,7 @@
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
|
||||
// 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
@@ -102,10 +102,10 @@ module pll (
|
||||
altpll_component.clk0_duty_cycle = 50,
|
||||
altpll_component.clk0_multiply_by = 65,
|
||||
altpll_component.clk0_phase_shift = "0",
|
||||
altpll_component.clk1_divide_by = 27,
|
||||
altpll_component.clk1_divide_by = 54,
|
||||
altpll_component.clk1_duty_cycle = 50,
|
||||
altpll_component.clk1_multiply_by = 65,
|
||||
altpll_component.clk1_phase_shift = "-2500",
|
||||
altpll_component.clk1_phase_shift = "0",
|
||||
altpll_component.compensate_clock = "CLK0",
|
||||
altpll_component.inclk0_input_frequency = 37037,
|
||||
altpll_component.intended_device_family = "Cyclone III",
|
||||
@@ -184,7 +184,7 @@ endmodule
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "65.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "65.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "32.500000"
|
||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
@@ -213,7 +213,7 @@ endmodule
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "65.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "65.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "32.50000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
@@ -221,7 +221,7 @@ endmodule
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-2500.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
|
||||
@@ -263,10 +263,10 @@ endmodule
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "65"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
|
||||
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "54"
|
||||
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "65"
|
||||
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-2500"
|
||||
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
|
||||
@@ -26,13 +26,13 @@ set_global_assignment -name DEVICE EP3C25E144C8
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY plusToo_top
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:27:29 OCTOBER 30, 2007"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
|
||||
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
|
||||
set_global_assignment -name FITTER_EFFORT "FAST FIT"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
|
||||
set_global_assignment -name FITTER_EFFORT "AUTO FIT"
|
||||
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
|
||||
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
|
||||
@@ -122,13 +122,13 @@ set_location_assignment PIN_43 -to SDRAM_CLK
|
||||
|
||||
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED
|
||||
set_global_assignment -name SMART_RECOMPILE ON
|
||||
set_global_assignment -name ENABLE_SIGNALTAP ON
|
||||
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
|
||||
set_global_assignment -name ENABLE_SIGNALTAP OFF
|
||||
set_global_assignment -name USE_SIGNALTAP_FILE out/cpu.stp
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
|
||||
set_global_assignment -name FMAX_REQUIREMENT "114 MHz"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
|
||||
@@ -136,7 +136,7 @@ set_global_assignment -name TPD_REQUIREMENT "2 ns"
|
||||
set_global_assignment -name TSU_REQUIREMENT "2 ns"
|
||||
set_global_assignment -name TCO_REQUIREMENT "2 ns"
|
||||
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
|
||||
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION OFF
|
||||
set_global_assignment -name AUTO_RAM_RECOGNITION ON
|
||||
set_global_assignment -name AUTO_ROM_RECOGNITION ON
|
||||
@@ -237,6 +237,8 @@ set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[13]
|
||||
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[14]
|
||||
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[15]
|
||||
|
||||
set_location_assignment PLL_1 -to "pll:cs0|altpll:altpll_component"
|
||||
|
||||
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk8
|
||||
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk64
|
||||
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to SDRAM_CLK
|
||||
@@ -337,208 +339,10 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_R
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to UART_RX
|
||||
|
||||
|
||||
set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
|
||||
set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "TG68:m68k|data_in[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "TG68:m68k|data_in[10]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "TG68:m68k|data_in[11]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to "TG68:m68k|data_in[12]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "TG68:m68k|data_in[13]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "TG68:m68k|data_in[14]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "TG68:m68k|data_in[15]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "TG68:m68k|data_in[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "TG68:m68k|data_in[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "TG68:m68k|data_in[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "TG68:m68k|data_in[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "TG68:m68k|data_in[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "TG68:m68k|data_in[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "TG68:m68k|data_in[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to "TG68:m68k|data_in[8]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to "TG68:m68k|data_in[9]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "TG68:m68k|reset" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "TG68KdotC_Kernel:m68k|IPL[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "TG68KdotC_Kernel:m68k|IPL[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "TG68KdotC_Kernel:m68k|IPL[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "TG68KdotC_Kernel:m68k|addr[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to "TG68KdotC_Kernel:m68k|addr[10]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "TG68KdotC_Kernel:m68k|addr[11]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "TG68KdotC_Kernel:m68k|addr[12]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "TG68KdotC_Kernel:m68k|addr[13]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "TG68KdotC_Kernel:m68k|addr[14]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "TG68KdotC_Kernel:m68k|addr[15]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "TG68KdotC_Kernel:m68k|addr[16]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "TG68KdotC_Kernel:m68k|addr[17]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "TG68KdotC_Kernel:m68k|addr[18]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "TG68KdotC_Kernel:m68k|addr[19]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "TG68KdotC_Kernel:m68k|addr[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "TG68KdotC_Kernel:m68k|addr[20]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to "TG68KdotC_Kernel:m68k|addr[21]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to "TG68KdotC_Kernel:m68k|addr[22]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to "TG68KdotC_Kernel:m68k|addr[23]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to "TG68KdotC_Kernel:m68k|addr[24]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to "TG68KdotC_Kernel:m68k|addr[25]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to "TG68KdotC_Kernel:m68k|addr[26]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to "TG68KdotC_Kernel:m68k|addr[27]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to "TG68KdotC_Kernel:m68k|addr[28]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to "TG68KdotC_Kernel:m68k|addr[29]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to "TG68KdotC_Kernel:m68k|addr[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to "TG68KdotC_Kernel:m68k|addr[30]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to "TG68KdotC_Kernel:m68k|addr[31]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to "TG68KdotC_Kernel:m68k|addr[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to "TG68KdotC_Kernel:m68k|addr[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to "TG68KdotC_Kernel:m68k|addr[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to "TG68KdotC_Kernel:m68k|addr[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to "TG68KdotC_Kernel:m68k|addr[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to "TG68KdotC_Kernel:m68k|addr[8]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to "TG68KdotC_Kernel:m68k|addr[9]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to "TG68KdotC_Kernel:m68k|busstate[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to "TG68KdotC_Kernel:m68k|busstate[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[54] -to "TG68KdotC_Kernel:m68k|clk" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[55] -to "TG68KdotC_Kernel:m68k|clkena_in" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[56] -to "TG68KdotC_Kernel:m68k|data_write[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[57] -to "TG68KdotC_Kernel:m68k|data_write[10]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[58] -to "TG68KdotC_Kernel:m68k|data_write[11]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[59] -to "TG68KdotC_Kernel:m68k|data_write[12]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[60] -to "TG68KdotC_Kernel:m68k|data_write[13]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[61] -to "TG68KdotC_Kernel:m68k|data_write[14]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[62] -to "TG68KdotC_Kernel:m68k|data_write[15]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[63] -to "TG68KdotC_Kernel:m68k|data_write[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[64] -to "TG68KdotC_Kernel:m68k|data_write[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[65] -to "TG68KdotC_Kernel:m68k|data_write[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[66] -to "TG68KdotC_Kernel:m68k|data_write[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[67] -to "TG68KdotC_Kernel:m68k|data_write[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[68] -to "TG68KdotC_Kernel:m68k|data_write[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[69] -to "TG68KdotC_Kernel:m68k|data_write[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[70] -to "TG68KdotC_Kernel:m68k|data_write[8]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[71] -to "TG68KdotC_Kernel:m68k|data_write[9]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[72] -to "TG68KdotC_Kernel:m68k|exe_opcode[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[73] -to "TG68KdotC_Kernel:m68k|exe_opcode[10]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[74] -to "TG68KdotC_Kernel:m68k|exe_opcode[11]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[75] -to "TG68KdotC_Kernel:m68k|exe_opcode[12]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[76] -to "TG68KdotC_Kernel:m68k|exe_opcode[13]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[77] -to "TG68KdotC_Kernel:m68k|exe_opcode[14]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[78] -to "TG68KdotC_Kernel:m68k|exe_opcode[15]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[79] -to "TG68KdotC_Kernel:m68k|exe_opcode[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[80] -to "TG68KdotC_Kernel:m68k|exe_opcode[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[81] -to "TG68KdotC_Kernel:m68k|exe_opcode[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[82] -to "TG68KdotC_Kernel:m68k|exe_opcode[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[83] -to "TG68KdotC_Kernel:m68k|exe_opcode[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[84] -to "TG68KdotC_Kernel:m68k|exe_opcode[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[85] -to "TG68KdotC_Kernel:m68k|exe_opcode[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[86] -to "TG68KdotC_Kernel:m68k|exe_opcode[8]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[87] -to "TG68KdotC_Kernel:m68k|exe_opcode[9]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[88] -to "TG68KdotC_Kernel:m68k|nLDS" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[89] -to "TG68KdotC_Kernel:m68k|nReset" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[90] -to "TG68KdotC_Kernel:m68k|nUDS" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[91] -to "TG68KdotC_Kernel:m68k|nWr" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[92] -to "addrController_top:ac0|_cpuDTACK" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "TG68:m68k|data_in[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "TG68:m68k|data_in[10]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "TG68:m68k|data_in[11]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "TG68:m68k|data_in[12]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "TG68:m68k|data_in[13]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "TG68:m68k|data_in[14]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "TG68:m68k|data_in[15]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "TG68:m68k|data_in[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "TG68:m68k|data_in[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "TG68:m68k|data_in[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "TG68:m68k|data_in[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "TG68:m68k|data_in[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "TG68:m68k|data_in[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "TG68:m68k|data_in[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "TG68:m68k|data_in[8]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "TG68:m68k|data_in[9]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "TG68:m68k|reset" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "TG68KdotC_Kernel:m68k|IPL[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "TG68KdotC_Kernel:m68k|IPL[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "TG68KdotC_Kernel:m68k|IPL[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "TG68KdotC_Kernel:m68k|addr[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "TG68KdotC_Kernel:m68k|addr[10]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "TG68KdotC_Kernel:m68k|addr[11]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "TG68KdotC_Kernel:m68k|addr[12]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "TG68KdotC_Kernel:m68k|addr[13]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "TG68KdotC_Kernel:m68k|addr[14]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "TG68KdotC_Kernel:m68k|addr[15]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "TG68KdotC_Kernel:m68k|addr[16]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "TG68KdotC_Kernel:m68k|addr[17]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "TG68KdotC_Kernel:m68k|addr[18]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "TG68KdotC_Kernel:m68k|addr[19]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "TG68KdotC_Kernel:m68k|addr[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "TG68KdotC_Kernel:m68k|addr[20]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "TG68KdotC_Kernel:m68k|addr[21]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "TG68KdotC_Kernel:m68k|addr[22]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "TG68KdotC_Kernel:m68k|addr[23]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "TG68KdotC_Kernel:m68k|addr[24]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "TG68KdotC_Kernel:m68k|addr[25]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "TG68KdotC_Kernel:m68k|addr[26]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "TG68KdotC_Kernel:m68k|addr[27]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "TG68KdotC_Kernel:m68k|addr[28]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "TG68KdotC_Kernel:m68k|addr[29]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "TG68KdotC_Kernel:m68k|addr[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "TG68KdotC_Kernel:m68k|addr[30]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "TG68KdotC_Kernel:m68k|addr[31]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "TG68KdotC_Kernel:m68k|addr[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "TG68KdotC_Kernel:m68k|addr[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "TG68KdotC_Kernel:m68k|addr[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "TG68KdotC_Kernel:m68k|addr[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to "TG68KdotC_Kernel:m68k|addr[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to "TG68KdotC_Kernel:m68k|addr[8]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to "TG68KdotC_Kernel:m68k|addr[9]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to "TG68KdotC_Kernel:m68k|busstate[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to "TG68KdotC_Kernel:m68k|busstate[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to "TG68KdotC_Kernel:m68k|clk" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to "TG68KdotC_Kernel:m68k|clkena_in" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to "TG68KdotC_Kernel:m68k|data_write[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to "TG68KdotC_Kernel:m68k|data_write[10]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to "TG68KdotC_Kernel:m68k|data_write[11]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to "TG68KdotC_Kernel:m68k|data_write[12]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to "TG68KdotC_Kernel:m68k|data_write[13]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to "TG68KdotC_Kernel:m68k|data_write[14]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to "TG68KdotC_Kernel:m68k|data_write[15]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to "TG68KdotC_Kernel:m68k|data_write[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to "TG68KdotC_Kernel:m68k|data_write[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to "TG68KdotC_Kernel:m68k|data_write[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to "TG68KdotC_Kernel:m68k|data_write[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to "TG68KdotC_Kernel:m68k|data_write[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to "TG68KdotC_Kernel:m68k|data_write[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to "TG68KdotC_Kernel:m68k|data_write[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to "TG68KdotC_Kernel:m68k|data_write[8]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to "TG68KdotC_Kernel:m68k|data_write[9]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to "TG68KdotC_Kernel:m68k|exe_opcode[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[73] -to "TG68KdotC_Kernel:m68k|exe_opcode[10]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[74] -to "TG68KdotC_Kernel:m68k|exe_opcode[11]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[75] -to "TG68KdotC_Kernel:m68k|exe_opcode[12]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[76] -to "TG68KdotC_Kernel:m68k|exe_opcode[13]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[77] -to "TG68KdotC_Kernel:m68k|exe_opcode[14]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[78] -to "TG68KdotC_Kernel:m68k|exe_opcode[15]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[79] -to "TG68KdotC_Kernel:m68k|exe_opcode[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[80] -to "TG68KdotC_Kernel:m68k|exe_opcode[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[81] -to "TG68KdotC_Kernel:m68k|exe_opcode[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[82] -to "TG68KdotC_Kernel:m68k|exe_opcode[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[83] -to "TG68KdotC_Kernel:m68k|exe_opcode[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[84] -to "TG68KdotC_Kernel:m68k|exe_opcode[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[85] -to "TG68KdotC_Kernel:m68k|exe_opcode[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[86] -to "TG68KdotC_Kernel:m68k|exe_opcode[8]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[87] -to "TG68KdotC_Kernel:m68k|exe_opcode[9]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[88] -to "TG68KdotC_Kernel:m68k|nLDS" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[89] -to "TG68KdotC_Kernel:m68k|nReset" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[90] -to "TG68KdotC_Kernel:m68k|nUDS" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[91] -to "TG68KdotC_Kernel:m68k|nWr" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[92] -to "addrController_top:ac0|_cpuDTACK" -section_id auto_signaltap_0
|
||||
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=AUTO" -section_id auto_signaltap_0
|
||||
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
|
||||
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
|
||||
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0
|
||||
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
|
||||
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
|
||||
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
|
||||
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
|
||||
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
|
||||
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
|
||||
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
|
||||
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
|
||||
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
|
||||
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
|
||||
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
|
||||
set_global_assignment -name ENABLE_NCE_PIN OFF
|
||||
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE plusToo_top.sv
|
||||
set_global_assignment -name VERILOG_FILE scsi.v
|
||||
set_global_assignment -name VERILOG_FILE ncr5380.v
|
||||
set_global_assignment -name VERILOG_FILE sigma_delta_dac.v
|
||||
@@ -548,8 +352,6 @@ set_global_assignment -name VHDL_FILE TG68K_Pack.vhd
|
||||
set_global_assignment -name VHDL_FILE TG68KdotC_Kernel.vhd
|
||||
set_global_assignment -name VHDL_FILE TG68K_ALU.vhd
|
||||
set_global_assignment -name VERILOG_FILE data_io.v
|
||||
set_global_assignment -name VERILOG_FILE user_io.v
|
||||
set_global_assignment -name VERILOG_FILE osd.v
|
||||
set_global_assignment -name VERILOG_FILE sdram.v
|
||||
set_global_assignment -name SDC_FILE plusToo_top.sdc
|
||||
set_global_assignment -name VERILOG_FILE scc.v
|
||||
@@ -562,362 +364,8 @@ set_global_assignment -name VERILOG_FILE addrController_top.v
|
||||
set_global_assignment -name VERILOG_FILE dataController_top.v
|
||||
set_global_assignment -name VERILOG_FILE videoTimer.v
|
||||
set_global_assignment -name VERILOG_FILE videoShifter.v
|
||||
set_global_assignment -name VERILOG_FILE plusToo_top.v
|
||||
set_global_assignment -name VERILOG_FILE floppy.v
|
||||
set_global_assignment -name SIGNALTAP_FILE stp1.stp
|
||||
set_global_assignment -name QIP_FILE pll.qip
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[93] -to "addrController_top:ac0|_memoryLDS" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[94] -to "addrController_top:ac0|_memoryUDS" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[93] -to "addrController_top:ac0|_memoryLDS" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[94] -to "addrController_top:ac0|_memoryUDS" -section_id auto_signaltap_0
|
||||
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=256" -section_id auto_signaltap_0
|
||||
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=256" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "pll:cs0|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[95] -to "addrController_top:ac0|videoBusControl" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[96] -to "clock325MHz:cs0|locked" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[97] -to "dataController_top:dc0|ncr5380:scsi|bus_cs" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[98] -to "dataController_top:dc0|ncr5380:scsi|bus_rs[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[99] -to "dataController_top:dc0|ncr5380:scsi|bus_rs[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[100] -to "dataController_top:dc0|ncr5380:scsi|bus_rs[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[101] -to "dataController_top:dc0|ncr5380:scsi|bus_we" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[102] -to "dataController_top:dc0|ncr5380:scsi|dack" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[103] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|ack" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[104] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|bsy" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[105] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|buffer_dout[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[106] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|buffer_dout[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[107] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|buffer_dout[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[108] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|buffer_dout[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[109] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|buffer_dout[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[110] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|buffer_dout[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[111] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|buffer_dout[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[112] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|buffer_dout[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[113] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cd" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[95] -to "addrController_top:ac0|videoBusControl" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[96] -to "clock325MHz:cs0|locked" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[97] -to "dataController_top:dc0|ncr5380:scsi|bus_cs" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[98] -to "dataController_top:dc0|ncr5380:scsi|bus_rs[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[99] -to "dataController_top:dc0|ncr5380:scsi|bus_rs[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[100] -to "dataController_top:dc0|ncr5380:scsi|bus_rs[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[101] -to "dataController_top:dc0|ncr5380:scsi|bus_we" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[102] -to "dataController_top:dc0|ncr5380:scsi|dack" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[103] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|ack" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[104] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|bsy" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[105] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|buffer_dout[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[106] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|buffer_dout[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[107] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|buffer_dout[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[108] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|buffer_dout[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[109] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|buffer_dout[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[110] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|buffer_dout[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[111] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|buffer_dout[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[112] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|buffer_dout[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[113] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cd" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[114] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd[0][0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[115] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd[0][1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[116] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd[0][2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[117] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd[0][3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[118] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd[0][4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[119] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd[0][5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[120] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd[0][6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[121] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd[0][7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[122] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd_cnt[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[123] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd_cnt[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[124] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd_cnt[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[125] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd_cnt[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[126] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd_cpl" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[127] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd_read" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[128] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[129] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[10]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[130] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[11]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[131] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[12]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[132] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[13]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[133] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[14]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[134] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[15]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[135] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[16]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[136] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[17]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[137] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[18]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[138] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[19]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[139] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[140] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[20]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[141] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[21]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[142] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[22]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[143] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[23]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[144] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[24]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[145] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[25]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[146] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[26]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[147] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[27]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[148] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[28]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[149] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[29]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[150] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[151] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[30]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[152] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[31]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[153] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[154] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[155] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[156] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[157] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[158] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[8]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[159] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[9]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[160] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dbg_cmds[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[161] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dbg_cmds[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[162] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dbg_cmds[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[163] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dbg_cmds[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[164] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dbg_cmds[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[165] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dbg_cmds[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[166] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dbg_cmds[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[167] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dbg_cmds[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[168] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|din[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[169] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|din[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[170] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|din[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[171] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|din[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[172] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|din[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[173] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|din[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[174] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|din[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[175] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|din[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[176] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dout[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[177] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dout[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[178] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dout[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[179] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dout[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[180] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dout[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[181] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dout[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[182] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dout[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[183] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dout[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[184] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_ack" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[185] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[186] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[10]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[187] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[11]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[188] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[12]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[189] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[13]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[190] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[14]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[191] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[15]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[192] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[16]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[193] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[17]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[194] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[18]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[195] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[19]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[196] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[197] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[20]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[198] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[21]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[199] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[22]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[200] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[23]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[201] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[24]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[202] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[25]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[203] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[26]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[204] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[27]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[205] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[28]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[206] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[29]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[207] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[208] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[30]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[209] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[31]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[210] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[211] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[212] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[213] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[214] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[215] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[8]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[216] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[9]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[217] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_rd" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[114] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd[0][0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[115] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd[0][1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[116] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd[0][2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[117] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd[0][3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[118] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd[0][4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[119] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd[0][5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[120] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd[0][6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[121] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd[0][7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[122] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd_cnt[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[123] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd_cnt[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[124] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd_cnt[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[125] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd_cnt[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[126] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd_cpl" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[127] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd_read" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[128] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[129] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[10]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[130] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[11]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[131] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[12]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[132] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[13]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[133] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[14]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[134] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[15]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[135] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[16]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[136] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[17]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[137] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[18]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[138] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[19]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[139] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[140] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[20]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[141] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[21]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[142] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[22]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[143] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[23]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[144] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[24]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[145] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[25]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[146] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[26]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[147] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[27]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[148] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[28]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[149] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[29]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[150] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[151] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[30]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[152] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[31]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[153] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[154] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[155] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[156] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[157] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[158] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[8]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[159] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[9]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[160] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dbg_cmds[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[161] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dbg_cmds[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[162] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dbg_cmds[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[163] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dbg_cmds[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[164] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dbg_cmds[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[165] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dbg_cmds[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[166] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dbg_cmds[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[167] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dbg_cmds[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[168] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|din[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[169] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|din[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[170] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|din[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[171] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|din[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[172] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|din[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[173] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|din[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[174] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|din[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[175] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|din[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[176] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dout[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[177] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dout[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[178] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dout[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[179] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dout[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[180] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dout[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[181] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dout[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[182] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dout[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[183] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dout[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[184] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_ack" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[185] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[186] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[10]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[187] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[11]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[188] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[12]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[189] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[13]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[190] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[14]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[191] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[15]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[192] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[16]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[193] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[17]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[194] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[18]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[195] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[19]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[196] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[197] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[20]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[198] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[21]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[199] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[22]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[200] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[23]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[201] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[24]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[202] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[25]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[203] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[26]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[204] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[27]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[205] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[28]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[206] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[29]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[207] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[208] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[30]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[209] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[31]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[210] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[211] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[212] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[213] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[214] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[215] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[8]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[216] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[9]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[217] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_rd" -section_id auto_signaltap_0
|
||||
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=265" -section_id auto_signaltap_0
|
||||
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=265" -section_id auto_signaltap_0
|
||||
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0
|
||||
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=817" -section_id auto_signaltap_0
|
||||
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=40745" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[218] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_wr" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[219] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|phase.000" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[220] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|phase.001" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[221] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|phase.010" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[222] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|phase.011" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[223] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|phase.100" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[224] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|phase.101" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[225] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|req" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[226] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|rst" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[227] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|sel" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[228] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[229] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[10]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[230] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[11]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[231] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[12]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[232] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[13]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[233] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[14]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[234] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[15]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[235] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[236] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[237] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[238] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[239] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[240] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[241] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[242] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[8]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[243] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[9]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[244] -to "dataController_top:dc0|ncr5380:scsi|scsi_bsy" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[245] -to "user_io:user_io|bit_cnt[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[246] -to "user_io:user_io|bit_cnt[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[247] -to "user_io:user_io|bit_cnt[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[248] -to "user_io:user_io|byte_cnt[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[249] -to "user_io:user_io|byte_cnt[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[250] -to "user_io:user_io|byte_cnt[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[251] -to "user_io:user_io|byte_cnt[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[252] -to "user_io:user_io|byte_cnt[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[253] -to "user_io:user_io|byte_cnt[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[254] -to "user_io:user_io|byte_cnt[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[255] -to "user_io:user_io|byte_cnt[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[256] -to "user_io:user_io|sd_din[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[257] -to "user_io:user_io|sd_din[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[258] -to "user_io:user_io|sd_din[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[259] -to "user_io:user_io|sd_din[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[260] -to "user_io:user_io|sd_din[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[261] -to "user_io:user_io|sd_din[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[262] -to "user_io:user_io|sd_din[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[263] -to "user_io:user_io|sd_din[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[264] -to "user_io:user_io|sd_din_strobe" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[218] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_wr" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[219] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|phase.000" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[220] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|phase.001" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[221] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|phase.010" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[222] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|phase.011" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[223] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|phase.100" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[224] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|phase.101" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[225] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|req" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[226] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|rst" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[227] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|sel" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[228] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[229] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[10]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[230] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[11]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[231] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[12]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[232] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[13]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[233] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[14]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[234] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[15]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[235] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[236] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[237] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[238] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[239] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[240] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[241] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[242] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[8]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[243] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[9]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[244] -to "dataController_top:dc0|ncr5380:scsi|scsi_bsy" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[245] -to "user_io:user_io|bit_cnt[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[246] -to "user_io:user_io|bit_cnt[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[247] -to "user_io:user_io|bit_cnt[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[248] -to "user_io:user_io|byte_cnt[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[249] -to "user_io:user_io|byte_cnt[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[250] -to "user_io:user_io|byte_cnt[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[251] -to "user_io:user_io|byte_cnt[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[252] -to "user_io:user_io|byte_cnt[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[253] -to "user_io:user_io|byte_cnt[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[254] -to "user_io:user_io|byte_cnt[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[255] -to "user_io:user_io|byte_cnt[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[256] -to "user_io:user_io|sd_din[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[257] -to "user_io:user_io|sd_din[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[258] -to "user_io:user_io|sd_din[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[259] -to "user_io:user_io|sd_din[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[260] -to "user_io:user_io|sd_din[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[261] -to "user_io:user_io|sd_din[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[262] -to "user_io:user_io|sd_din[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[263] -to "user_io:user_io|sd_din[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[264] -to "user_io:user_io|sd_din_strobe" -section_id auto_signaltap_0
|
||||
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=9780" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp
|
||||
set_global_assignment -name QIP_FILE "../../mist-modules/mist_core.qip"
|
||||
set_global_assignment -name SIGNALTAP_FILE out/cpu.stp
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
@@ -38,17 +38,19 @@ set_time_format -unit ns -decimal_places 3
|
||||
# Create Clock
|
||||
#**************************************************************
|
||||
|
||||
create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}]
|
||||
create_clock -name {clk50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {clk50}]
|
||||
create_clock -name {dataController_top:dc0|clkPhase[1]} -period 123.076 -waveform { 0.000 61.538 } [get_registers { dataController_top:dc0|clkPhase[1] }]
|
||||
|
||||
|
||||
create_clock -name "CLOCK_27" -period 37.037 [get_ports {CLOCK_27[0]}]
|
||||
create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Create Generated Clock
|
||||
#**************************************************************
|
||||
|
||||
create_generated_clock -name {clock325MHz:cs0|altpll:altpll_component|_clk0} -source [get_pins {cs0|altpll_component|pll|inclk[0]}] -duty_cycle 50.000 -multiply_by 13 -divide_by 20 -master_clock {clk50} [get_pins {cs0|altpll_component|pll|clk[0]}]
|
||||
|
||||
derive_pll_clocks -create_base_clocks
|
||||
|
||||
# Automatically calculate clock uncertainty to jitter and other effects.
|
||||
derive_clock_uncertainty
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Latency
|
||||
@@ -78,7 +80,7 @@ create_generated_clock -name {clock325MHz:cs0|altpll:altpll_component|_clk0} -so
|
||||
# Set Clock Groups
|
||||
#**************************************************************
|
||||
|
||||
set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
|
||||
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {cs0|altpll_component|auto_generated|pll1|clk[*]}]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
@@ -109,3 +111,17 @@ set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
|
||||
# Set Input Transition
|
||||
#**************************************************************
|
||||
|
||||
|
||||
# SDRAM delays
|
||||
set_input_delay -clock [get_clocks {cs0|altpll_component|auto_generated|pll1|clk[0]}] -reference_pin [get_ports {SDRAM_CLK}] -max 6.4 [get_ports SDRAM_DQ[*]]
|
||||
set_input_delay -clock [get_clocks {cs0|altpll_component|auto_generated|pll1|clk[0]}] -reference_pin [get_ports {SDRAM_CLK}] -min 3.2 [get_ports SDRAM_DQ[*]]
|
||||
|
||||
set_output_delay -clock [get_clocks {cs0|altpll_component|auto_generated|pll1|clk[0]}] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
|
||||
set_output_delay -clock [get_clocks {cs0|altpll_component|auto_generated|pll1|clk[0]}] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
|
||||
|
||||
# VGA delayes
|
||||
set_output_delay -clock [get_clocks {cs0|altpll_component|auto_generated|pll1|clk[1]}] -max 0 [get_ports {VGA_*}]
|
||||
set_output_delay -clock [get_clocks {cs0|altpll_component|auto_generated|pll1|clk[1]}] -min -5 [get_ports {VGA_*}]
|
||||
|
||||
set_multicycle_path -to {VGA_*[*]} -setup 2
|
||||
set_multicycle_path -to {VGA_*[*]} -hold 1
|
||||
|
||||
@@ -39,6 +39,8 @@ module plusToo_top(
|
||||
input wire CONF_DATA0 // SPI_SS for user_io
|
||||
);
|
||||
|
||||
assign LED = ~(dio_download || |(diskAct ^ diskMotor));
|
||||
|
||||
// ------------------------------ Plus Too Bus Timing ---------------------------------
|
||||
// for stability and maintainability reasons the whole timing has been simplyfied:
|
||||
// 00 01 10 11
|
||||
@@ -48,28 +50,6 @@ module plusToo_top(
|
||||
// | | |
|
||||
// video cpu cpu
|
||||
// read write read
|
||||
|
||||
// include the OSD into the video data path
|
||||
osd #(10,0,2) osd (
|
||||
.pclk ( clk32 ),
|
||||
|
||||
// spi for OSD
|
||||
.sdi ( SPI_DI ),
|
||||
.sck ( SPI_SCK ),
|
||||
.ss ( SPI_SS3 ),
|
||||
|
||||
.red_in ( { red, 2'b00 } ),
|
||||
.green_in ( { green, 2'b00 } ),
|
||||
.blue_in ( { blue, 2'b00 } ),
|
||||
.hs_in ( hsync ),
|
||||
.vs_in ( vsync ),
|
||||
|
||||
.red_out ( VGA_R ),
|
||||
.green_out ( VGA_G ),
|
||||
.blue_out ( VGA_B ),
|
||||
.hs_out ( VGA_HS ),
|
||||
.vs_out ( VGA_VS )
|
||||
);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// ------------------------------ data_io ----------------------------------
|
||||
@@ -92,21 +72,24 @@ wire dsk_ext_ins = dsk_ext_ds || dsk_ext_ss;
|
||||
|
||||
// at the end of a download latch file size
|
||||
// diskEject is set by macos on eject
|
||||
always @(negedge dio_download or posedge diskEject[0]) begin
|
||||
reg dio_download_d;
|
||||
always @(posedge clk32) dio_download_d <= dio_download;
|
||||
|
||||
always @(posedge clk32) begin
|
||||
if(diskEject[0]) begin
|
||||
dsk_int_ds <= 1'b0;
|
||||
dsk_int_ss <= 1'b0;
|
||||
end else if(dio_index == 1) begin
|
||||
end else if(~dio_download && dio_download_d && dio_index == 1) begin
|
||||
dsk_int_ds <= (dio_addr == 409599); // double sides disk, addr counts words, not bytes
|
||||
dsk_int_ss <= (dio_addr == 204799); // single sided disk
|
||||
end
|
||||
end
|
||||
|
||||
always @(negedge dio_download or posedge diskEject[1]) begin
|
||||
|
||||
always @(posedge clk32) begin
|
||||
if(diskEject[1]) begin
|
||||
dsk_ext_ds <= 1'b0;
|
||||
dsk_ext_ss <= 1'b0;
|
||||
end else if(dio_index == 2) begin
|
||||
end else if(~dio_download && dio_download_d && dio_index == 2) begin
|
||||
dsk_ext_ds <= (dio_addr == 409599); // double sided disk, addr counts words, not bytes
|
||||
dsk_ext_ss <= (dio_addr == 204799); // single sided disk
|
||||
end
|
||||
@@ -142,37 +125,26 @@ wire [3:0] key = 4'd0;
|
||||
// send to the VGA
|
||||
wire hsync;
|
||||
wire vsync;
|
||||
wire [3:0] red;
|
||||
wire [3:0] green;
|
||||
wire [3:0] blue;
|
||||
|
||||
// ps2 interface for mouse, to be mapped into user_io
|
||||
wire mouseClk;
|
||||
wire mouseData;
|
||||
wire keyClk;
|
||||
wire keyData;
|
||||
|
||||
|
||||
// synthesize a 32.5 MHz clock
|
||||
wire clk64;
|
||||
wire pll_locked;
|
||||
|
||||
reg clk32;
|
||||
always @(posedge clk64)
|
||||
clk32 <= !clk32;
|
||||
|
||||
wire clk32;
|
||||
|
||||
pll cs0(
|
||||
.inclk0 ( CLOCK_27[0] ),
|
||||
.c0 ( clk64 ),
|
||||
.c1 ( SDRAM_CLK ),
|
||||
.c0 ( clk64 ),
|
||||
.c1 ( clk32 ),
|
||||
.locked ( pll_locked )
|
||||
);
|
||||
|
||||
// generate ~16kHz for ps2
|
||||
wire ps2_clk = ps2_clk_div[8];
|
||||
reg [8:0] ps2_clk_div;
|
||||
always @(posedge clk8)
|
||||
ps2_clk_div <= ps2_clk_div + 9'd1;
|
||||
|
||||
assign SDRAM_CLK = clk64;
|
||||
|
||||
// set the real-world inputs to sane defaults
|
||||
localparam serialIn = 1'b0,
|
||||
configROMSize = 1'b1; // 128K ROM
|
||||
@@ -182,6 +154,7 @@ wire keyData;
|
||||
// interconnects
|
||||
// CPU
|
||||
wire clk8, _cpuReset, _cpuUDS, _cpuLDS, _cpuRW;
|
||||
wire clk8_en_p, clk8_en_n;
|
||||
wire [2:0] _cpuIPL;
|
||||
wire [7:0] cpuAddrHi;
|
||||
wire [23:0] cpuAddr;
|
||||
@@ -211,79 +184,81 @@ wire keyData;
|
||||
wire [21:0] dskReadAddrInt;
|
||||
wire dskReadAckExt;
|
||||
wire [21:0] dskReadAddrExt;
|
||||
|
||||
// convert 1-bit pixel data to 4:4:4 RGB
|
||||
assign red[3:0] = { pixelOut, pixelOut, pixelOut, pixelOut };
|
||||
assign green[3:0] = { pixelOut, pixelOut, pixelOut, pixelOut };
|
||||
assign blue[3:0] = { pixelOut, pixelOut, pixelOut, pixelOut };
|
||||
|
||||
|
||||
// the configuration string is returned to the io controller to allow
|
||||
// it to control the menu on the OSD
|
||||
parameter CONF_STR = {
|
||||
"PLUS_TOO;;",
|
||||
"F1,DSK;",
|
||||
"F2,DSK;",
|
||||
"S3,IMG;",
|
||||
"O4,Memory,1MB,4MB;",
|
||||
"O5,Speed,Normal,Turbo;",
|
||||
"T6,Reset"
|
||||
"PLUS_TOO;;",
|
||||
"F1,DSK;",
|
||||
"F2,DSK;",
|
||||
"S0,IMG;",
|
||||
"O4,Memory,1MB,4MB;",
|
||||
"O5,Speed,Normal,Turbo;",
|
||||
"O67,CPU,68000,68010,68020;",
|
||||
"T0,Reset"
|
||||
};
|
||||
|
||||
|
||||
wire status_mem = status[4];
|
||||
wire status_turbo = status[5];
|
||||
wire status_reset = status[6];
|
||||
|
||||
parameter CONF_STR_LEN = 10+7+7+7+18+22+8;
|
||||
wire [1:0] status_cpu = status[7:6];
|
||||
wire status_reset = status[0];
|
||||
|
||||
// the status register is controlled by the on screen display (OSD)
|
||||
wire [7:0] status;
|
||||
wire [1:0] buttons;
|
||||
wire ypbpr;
|
||||
|
||||
wire [31:0] io_lba;
|
||||
wire io_rd;
|
||||
wire io_wr;
|
||||
wire io_ack;
|
||||
wire [7:0] io_din;
|
||||
wire io_din_strobe;
|
||||
wire [7:0] io_dout;
|
||||
wire io_dout_strobe;
|
||||
|
||||
wire [1:0] io_rd;
|
||||
wire [1:0] io_wr;
|
||||
wire io_ack;
|
||||
wire [1:0] img_mounted;
|
||||
wire [31:0] img_size;
|
||||
wire [7:0] sd_buff_dout;
|
||||
wire sd_buff_wr;
|
||||
wire [8:0] sd_buff_addr;
|
||||
wire [7:0] sd_buff_din;
|
||||
|
||||
// include user_io module for arm controller communication
|
||||
user_io #(.STRLEN(CONF_STR_LEN)) user_io (
|
||||
.conf_str ( CONF_STR ),
|
||||
user_io #(.STRLEN($size(CONF_STR)>>3)) user_io (
|
||||
.clk_sys ( clk32 ),
|
||||
.clk_sd ( clk32 ),
|
||||
.conf_str ( CONF_STR ),
|
||||
|
||||
.SPI_CLK ( SPI_SCK ),
|
||||
.SPI_SS_IO ( CONF_DATA0 ),
|
||||
.SPI_MISO ( SPI_DO ),
|
||||
.SPI_MOSI ( SPI_DI ),
|
||||
.SPI_CLK ( SPI_SCK ),
|
||||
.SPI_SS_IO ( CONF_DATA0 ),
|
||||
.SPI_MISO ( SPI_DO ),
|
||||
.SPI_MOSI ( SPI_DI ),
|
||||
|
||||
.status ( status ),
|
||||
.buttons ( buttons ),
|
||||
|
||||
// ps2 interface
|
||||
.ps2_clk ( ps2_clk ),
|
||||
.ps2_kbd_clk ( keyClk ),
|
||||
.ps2_kbd_data ( keyData ),
|
||||
.ps2_mouse_clk ( mouseClk ),
|
||||
.ps2_mouse_data( mouseData ),
|
||||
.status ( status ),
|
||||
.buttons ( buttons ),
|
||||
.ypbpr ( ypbpr ),
|
||||
|
||||
// ps2 interface
|
||||
.ps2_kbd_clk ( keyClk ),
|
||||
.ps2_kbd_data ( keyData ),
|
||||
.ps2_mouse_clk ( mouseClk ),
|
||||
.ps2_mouse_data ( mouseData ),
|
||||
|
||||
// SD/block device interface
|
||||
.sd_lba ( io_lba ),
|
||||
.sd_rd ( io_rd ),
|
||||
.sd_wr ( io_wr ),
|
||||
.sd_ack ( io_ack ),
|
||||
.sd_conf ( 1'b0 ),
|
||||
.sd_sdhc ( 1'b1 ),
|
||||
.sd_dout ( io_din ),
|
||||
.sd_dout_strobe( io_din_strobe ),
|
||||
.sd_din ( io_dout ),
|
||||
.sd_din_strobe ( io_dout_strobe )
|
||||
.img_mounted ( img_mounted ),
|
||||
.img_size ( img_size ),
|
||||
.sd_lba ( io_lba ),
|
||||
.sd_rd ( io_rd ),
|
||||
.sd_wr ( io_wr ),
|
||||
.sd_ack ( io_ack ),
|
||||
.sd_conf ( 1'b0 ),
|
||||
.sd_sdhc ( 1'b1 ),
|
||||
.sd_dout ( sd_buff_dout ),
|
||||
.sd_dout_strobe ( sd_buff_wr ),
|
||||
.sd_buff_addr ( sd_buff_addr ),
|
||||
.sd_din ( sd_buff_din )
|
||||
);
|
||||
|
||||
wire [1:0] cpu_busstate;
|
||||
wire cpu_clkena = cpuBusControl || (cpu_busstate == 2'b01);
|
||||
TG68KdotC_Kernel #(0,0,0,0,0,0) m68k (
|
||||
.clk ( clk8 ),
|
||||
wire cpu_clkena = clk8_en_p && (cpuBusControl || (cpu_busstate == 2'b01));
|
||||
TG68KdotC_Kernel #(2,2,2,2,2,2,0,0) m68k (
|
||||
.clk ( clk32 ),
|
||||
.nReset ( _cpuReset ),
|
||||
.clkena_in ( cpu_clkena ),
|
||||
.data_in ( dataControllerDataOut ),
|
||||
@@ -291,8 +266,8 @@ wire keyData;
|
||||
.IPL_autovector ( 1'b1 ),
|
||||
.berr ( 1'b0 ),
|
||||
.clr_berr ( 1'b0 ),
|
||||
.CPU ( 2'b00 ), // 00=68000
|
||||
.addr ( {cpuAddrHi, cpuAddr} ),
|
||||
.CPU ( { status_cpu[1], |status_cpu } ), // 00->68000 01->68010 11->68020
|
||||
.addr_out ( {cpuAddrHi, cpuAddr} ),
|
||||
.data_write ( cpuDataOut ),
|
||||
.nUDS ( _cpuUDS ),
|
||||
.nLDS ( _cpuLDS ),
|
||||
@@ -300,11 +275,12 @@ wire keyData;
|
||||
.busstate ( cpu_busstate ), // 00-> fetch code 10->read data 11->write data 01->no memaccess
|
||||
.nResetOut ( ),
|
||||
.FC ( )
|
||||
);
|
||||
);
|
||||
|
||||
|
||||
addrController_top ac0(
|
||||
.clk8(clk8),
|
||||
.clk(clk32),
|
||||
.clk8_en_p(clk8_en_p),
|
||||
.clk8_en_n(clk8_en_n),
|
||||
.cpuAddr(cpuAddr),
|
||||
._cpuUDS(_cpuUDS),
|
||||
._cpuLDS(_cpuLDS),
|
||||
@@ -340,23 +316,26 @@ wire keyData;
|
||||
.dskReadAddrExt(dskReadAddrExt),
|
||||
.dskReadAckExt(dskReadAckExt)
|
||||
);
|
||||
|
||||
|
||||
wire [1:0] diskEject;
|
||||
|
||||
wire [1:0] diskMotor, diskAct;
|
||||
|
||||
// addional ~8ms delay in reset
|
||||
wire rom_download = dio_download && (dio_index == 0);
|
||||
wire n_reset = (rst_cnt == 0);
|
||||
reg [15:0] rst_cnt;
|
||||
reg last_mem_config;
|
||||
always @(posedge clk8) begin
|
||||
last_mem_config <= status_mem;
|
||||
always @(posedge clk32) begin
|
||||
if (clk8_en_p) begin
|
||||
last_mem_config <= status_mem;
|
||||
|
||||
// various sources can reset the mac
|
||||
if(!pll_locked || status[0] || status_reset || buttons[1] ||
|
||||
rom_download || (last_mem_config != status_mem))
|
||||
rst_cnt <= 16'd65535;
|
||||
else if(rst_cnt != 0)
|
||||
rst_cnt <= rst_cnt - 16'd1;
|
||||
// various sources can reset the mac
|
||||
if(!pll_locked || status_reset || buttons[1] ||
|
||||
rom_download || (last_mem_config != status_mem))
|
||||
rst_cnt <= 16'd65535;
|
||||
else if(rst_cnt != 0)
|
||||
rst_cnt <= rst_cnt - 16'd1;
|
||||
end
|
||||
end
|
||||
|
||||
wire [10:0] audio;
|
||||
@@ -370,8 +349,10 @@ wire keyData;
|
||||
|
||||
dataController_top dc0(
|
||||
.clk32(clk32),
|
||||
.clk8(clk8),
|
||||
._systemReset(n_reset),
|
||||
.clk8(clk8),
|
||||
.clk8_en_p(clk8_en_p),
|
||||
.clk8_en_n(clk8_en_n),
|
||||
._systemReset(n_reset),
|
||||
._cpuReset(_cpuReset),
|
||||
._cpuIPL(_cpuIPL),
|
||||
._cpuUDS(_cpuUDS),
|
||||
@@ -390,26 +371,26 @@ wire keyData;
|
||||
.videoBusControl(videoBusControl),
|
||||
.memoryDataOut(memoryDataOut),
|
||||
.memoryDataIn(sdram_do),
|
||||
|
||||
|
||||
// peripherals
|
||||
.keyClk(keyClk),
|
||||
.keyData(keyData),
|
||||
.mouseClk(mouseClk),
|
||||
.mouseData(mouseData),
|
||||
.serialIn(serialIn),
|
||||
|
||||
|
||||
// video
|
||||
._hblank(_hblank),
|
||||
._vblank(_vblank),
|
||||
.pixelOut(pixelOut),
|
||||
.loadPixels(loadPixels),
|
||||
|
||||
|
||||
.memoryOverlayOn(memoryOverlayOn),
|
||||
|
||||
.audioOut(audio),
|
||||
.snd_alt(snd_alt),
|
||||
.loadSound(loadSound),
|
||||
|
||||
|
||||
// floppy disk interface
|
||||
.insertDisk( { dsk_ext_ins, dsk_int_ins} ),
|
||||
.diskSides( { dsk_ext_ds, dsk_int_ds} ),
|
||||
@@ -418,18 +399,59 @@ wire keyData;
|
||||
.dskReadAckInt(dskReadAckInt),
|
||||
.dskReadAddrExt(dskReadAddrExt),
|
||||
.dskReadAckExt(dskReadAckExt),
|
||||
.diskMotor(diskMotor),
|
||||
.diskAct(diskAct),
|
||||
|
||||
// block device interface for scsi disk
|
||||
.io_lba ( io_lba ),
|
||||
.io_rd ( io_rd ),
|
||||
.io_wr ( io_wr ),
|
||||
.io_ack ( io_ack ),
|
||||
.io_din ( io_din ),
|
||||
.io_din_strobe ( io_din_strobe ),
|
||||
.io_dout ( io_dout ),
|
||||
.io_dout_strobe( io_dout_strobe )
|
||||
.img_mounted ( img_mounted ),
|
||||
.img_size ( img_size ),
|
||||
.io_lba ( io_lba ),
|
||||
.io_rd ( io_rd ),
|
||||
.io_wr ( io_wr ),
|
||||
.io_ack ( io_ack ),
|
||||
.sd_buff_addr ( sd_buff_addr ),
|
||||
.sd_buff_dout ( sd_buff_dout ),
|
||||
.sd_buff_din ( sd_buff_din ),
|
||||
.sd_buff_wr ( sd_buff_wr )
|
||||
);
|
||||
|
||||
|
||||
// video output
|
||||
mist_video #(.COLOR_DEPTH(1)) mist_video (
|
||||
.clk_sys ( clk32 ),
|
||||
|
||||
// OSD SPI interface
|
||||
.SPI_SCK ( SPI_SCK ),
|
||||
.SPI_SS3 ( SPI_SS3 ),
|
||||
.SPI_DI ( SPI_DI ),
|
||||
|
||||
// 0 = HVSync 31KHz, 1 = CSync 15KHz
|
||||
// no scandoubler for plus_too
|
||||
.scandoubler_disable ( 1'b1 ),
|
||||
// disable csync without scandoubler
|
||||
.no_csync ( 1'b1 ),
|
||||
// YPbPr always uses composite sync
|
||||
.ypbpr ( ypbpr ),
|
||||
// Rotate OSD [0] - rotate [1] - left or right
|
||||
.rotate ( 2'b00 ),
|
||||
// composite-like blending
|
||||
.blend ( 1'b0 ),
|
||||
|
||||
// video in
|
||||
.R ( pixelOut ),
|
||||
.G ( pixelOut ),
|
||||
.B ( pixelOut ),
|
||||
|
||||
.HSync ( hsync ),
|
||||
.VSync ( vsync ),
|
||||
|
||||
// MiST video output signals
|
||||
.VGA_R ( VGA_R ),
|
||||
.VGA_G ( VGA_G ),
|
||||
.VGA_B ( VGA_B ),
|
||||
.VGA_VS ( VGA_VS ),
|
||||
.VGA_HS ( VGA_HS )
|
||||
);
|
||||
|
||||
// sdram used for ram/rom maps directly into 68k address space
|
||||
wire download_cycle = dio_download && dioBusControl;
|
||||
|
||||
@@ -440,7 +462,6 @@ wire [1:0] sdram_ds = download_cycle?2'b11:{ !_memoryUDS, !_memoryLDS };
|
||||
wire sdram_we = download_cycle?dio_write:!_ramWE;
|
||||
wire sdram_oe = download_cycle?1'b0:(!_ramOE || !_romOE);
|
||||
|
||||
|
||||
// during rom/disk download ffff is returned so the screen is black during download
|
||||
// "extra rom" is used to hold the disk image. It's expected to be byte wide and
|
||||
// we thus need to properly demultiplex the word returned from sdram in that case
|
||||
@@ -449,35 +470,35 @@ wire [15:0] extra_rom_data_demux = memoryAddr[0]?
|
||||
wire [15:0] sdram_do = download_cycle?16'hffff:
|
||||
(dskReadAckInt || dskReadAckExt)?extra_rom_data_demux:
|
||||
sdram_out;
|
||||
|
||||
|
||||
wire [15:0] sdram_out;
|
||||
|
||||
|
||||
assign SDRAM_CKE = 1'b1;
|
||||
|
||||
sdram sdram (
|
||||
// interface to the MT48LC16M16 chip
|
||||
.sd_data ( SDRAM_DQ ),
|
||||
.sd_addr ( SDRAM_A ),
|
||||
.sd_dqm ( {SDRAM_DQMH, SDRAM_DQML} ),
|
||||
.sd_cs ( SDRAM_nCS ),
|
||||
.sd_ba ( SDRAM_BA ),
|
||||
.sd_we ( SDRAM_nWE ),
|
||||
.sd_ras ( SDRAM_nRAS ),
|
||||
.sd_cas ( SDRAM_nCAS ),
|
||||
.sd_data ( SDRAM_DQ ),
|
||||
.sd_addr ( SDRAM_A ),
|
||||
.sd_dqm ( {SDRAM_DQMH, SDRAM_DQML} ),
|
||||
.sd_cs ( SDRAM_nCS ),
|
||||
.sd_ba ( SDRAM_BA ),
|
||||
.sd_we ( SDRAM_nWE ),
|
||||
.sd_ras ( SDRAM_nRAS ),
|
||||
.sd_cas ( SDRAM_nCAS ),
|
||||
|
||||
// system interface
|
||||
.clk_64 ( clk64 ),
|
||||
.clk_8 ( clk8 ),
|
||||
.init ( !pll_locked ),
|
||||
// system interface
|
||||
.clk_64 ( clk64 ),
|
||||
.clk_8 ( clk8 ),
|
||||
.init ( !pll_locked ),
|
||||
|
||||
// cpu/chipset interface
|
||||
// cpu/chipset interface
|
||||
// map rom to sdram word address $200000 - $20ffff
|
||||
.din ( sdram_din ),
|
||||
.addr ( sdram_addr ),
|
||||
.ds ( sdram_ds ),
|
||||
.we ( sdram_we ),
|
||||
.oe ( sdram_oe ),
|
||||
.dout ( sdram_out )
|
||||
.din ( sdram_din ),
|
||||
.addr ( sdram_addr ),
|
||||
.ds ( sdram_ds ),
|
||||
.we ( sdram_we ),
|
||||
.oe ( sdram_oe ),
|
||||
.dout ( sdram_out )
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -12,24 +12,25 @@
|
||||
*/
|
||||
|
||||
module ps2(input sysclk,
|
||||
input reset,
|
||||
input clk_en,
|
||||
input reset,
|
||||
|
||||
// inout ps2dat,
|
||||
// inout ps2clk,
|
||||
input ps2dat,
|
||||
input ps2clk,
|
||||
input ps2dat,
|
||||
input ps2clk,
|
||||
|
||||
output istrobe,
|
||||
output [7:0] ibyte,
|
||||
output istrobe,
|
||||
output [7:0] ibyte,
|
||||
|
||||
input oreq,
|
||||
input [7:0] obyte,
|
||||
output oack,
|
||||
input oreq,
|
||||
input [7:0] obyte,
|
||||
output oack,
|
||||
|
||||
output timeout,
|
||||
output timeout,
|
||||
|
||||
output[1:0] dbg_state
|
||||
);
|
||||
output[1:0] dbg_state
|
||||
);
|
||||
|
||||
reg [7:0] clkbuf;
|
||||
reg [7:0] datbuf;
|
||||
@@ -54,7 +55,7 @@ module ps2(input sysclk,
|
||||
always@(posedge sysclk or posedge reset) begin
|
||||
if (reset)
|
||||
state <= ps2_state_idle;
|
||||
else begin
|
||||
else if (clk_en) begin
|
||||
if (timeout && !oreq)
|
||||
state <= ps2_state_idle;
|
||||
else
|
||||
@@ -93,7 +94,7 @@ module ps2(input sysclk,
|
||||
always@(posedge sysclk or posedge reset) begin
|
||||
if (reset)
|
||||
shiftcnt <= 10;
|
||||
else begin
|
||||
else if (clk_en) begin
|
||||
if (state == ps2_state_idle)
|
||||
shiftcnt <= 10;
|
||||
else if (state == ps2_state_ring)
|
||||
@@ -107,7 +108,7 @@ module ps2(input sysclk,
|
||||
always@(posedge sysclk or posedge reset) begin
|
||||
if (reset)
|
||||
shiftreg <= 0;
|
||||
else begin
|
||||
else if (clk_en) begin
|
||||
if (oreq)
|
||||
shiftreg <= { 1'b1, opar, obyte, 1'b0 };
|
||||
else if (clkdown && state != ps2_state_ring)
|
||||
@@ -128,7 +129,7 @@ module ps2(input sysclk,
|
||||
clkbuf <= 0;
|
||||
clksync <= 0;
|
||||
clkprev <= 0;
|
||||
end else begin
|
||||
end else if (clk_en) begin
|
||||
clkprev <= clksync;
|
||||
clkbuf <= { clkbuf[6:0], ps2clk };
|
||||
if (clkbuf[7:2] == 6'b000000)
|
||||
@@ -144,7 +145,7 @@ module ps2(input sysclk,
|
||||
if (reset) begin
|
||||
datbuf <= 0;
|
||||
datsync <= 0;
|
||||
end else begin
|
||||
end else if (clk_en) begin
|
||||
datbuf <= { datbuf[6:0], ps2dat };
|
||||
if (datbuf[7:2] == 6'b000000)
|
||||
datsync <= 0;
|
||||
@@ -161,7 +162,7 @@ module ps2(input sysclk,
|
||||
always@(posedge sysclk or posedge reset) begin
|
||||
if (reset)
|
||||
timecnt <= 0;
|
||||
else begin
|
||||
else if (clk_en) begin
|
||||
if (clkdown | oreq)
|
||||
timecnt <= 0;
|
||||
else
|
||||
|
||||
@@ -4,16 +4,17 @@
|
||||
* PS2 Keyboard to Mac interface module
|
||||
*/
|
||||
module ps2_kbd( input sysclk,
|
||||
input reset,
|
||||
input clk_en,
|
||||
input reset,
|
||||
|
||||
inout ps2dat,
|
||||
inout ps2clk,
|
||||
inout ps2dat,
|
||||
inout ps2clk,
|
||||
|
||||
input [7:0] data_out,
|
||||
input strobe_out,
|
||||
input [7:0] data_out,
|
||||
input strobe_out,
|
||||
|
||||
output [7:0] data_in,
|
||||
output strobe_in
|
||||
output [7:0] data_in,
|
||||
output strobe_in
|
||||
);
|
||||
|
||||
reg [8:0] keymac;
|
||||
@@ -49,16 +50,17 @@ module ps2_kbd( input sysclk,
|
||||
wire [1:0] dbg_lowstate;
|
||||
|
||||
ps2 ps20(.sysclk(sysclk),
|
||||
.reset(reset),
|
||||
.ps2dat(ps2dat),
|
||||
.ps2clk(ps2clk),
|
||||
.istrobe(istrobe),
|
||||
.ibyte(ibyte),
|
||||
.oreq(oreq),
|
||||
.obyte(obyte),
|
||||
.oack(oack),
|
||||
.timeout(timeout),
|
||||
.dbg_state(dbg_lowstate));
|
||||
.clk_en(clk_en),
|
||||
.reset(reset),
|
||||
.ps2dat(ps2dat),
|
||||
.ps2clk(ps2clk),
|
||||
.istrobe(istrobe),
|
||||
.ibyte(ibyte),
|
||||
.oreq(oreq),
|
||||
.obyte(obyte),
|
||||
.oack(oack),
|
||||
.timeout(timeout),
|
||||
.dbg_state(dbg_lowstate));
|
||||
|
||||
/* --- PS2 side State machine ---
|
||||
*
|
||||
@@ -148,17 +150,17 @@ module ps2_kbd( input sysclk,
|
||||
always@(posedge sysclk or posedge reset)
|
||||
if (reset)
|
||||
state <= ps2k_state_wait; // ps2k_state_init
|
||||
else
|
||||
else if (clk_en)
|
||||
state <= next;
|
||||
always@(posedge sysclk or posedge reset)
|
||||
if (reset)
|
||||
oreq <= 0;
|
||||
else
|
||||
else if (clk_en)
|
||||
oreq <= nreq;
|
||||
always@(posedge sysclk or posedge reset)
|
||||
if (reset)
|
||||
obyte <= 0;
|
||||
else
|
||||
else if (clk_en)
|
||||
obyte <= nbyte;
|
||||
|
||||
assign got_key = (state == ps2k_state_wait) && istrobe;
|
||||
@@ -172,7 +174,7 @@ module ps2_kbd( input sysclk,
|
||||
extended <= 0;
|
||||
keybreak <= 0;
|
||||
capslock <= 0;
|
||||
end else if (got_key) begin
|
||||
end else if (clk_en && got_key) begin
|
||||
if (got_break)
|
||||
keybreak <= 1;
|
||||
else if (got_extend)
|
||||
@@ -196,7 +198,7 @@ module ps2_kbd( input sysclk,
|
||||
cmd_instant <= 0;
|
||||
cmd_model <= 0;
|
||||
cmd_test <= 0;
|
||||
end else begin
|
||||
end else if (clk_en) begin
|
||||
if (strobe_out) begin
|
||||
cmd_inquiry <= 0;
|
||||
cmd_instant <= 0;
|
||||
@@ -218,12 +220,12 @@ module ps2_kbd( input sysclk,
|
||||
always@(posedge sysclk or posedge reset)
|
||||
if (reset)
|
||||
pacetimer <= 0;
|
||||
else begin
|
||||
else if (clk_en) begin
|
||||
/* reset counter on command from Mac */
|
||||
if (strobe_out)
|
||||
pacetimer <= 0;
|
||||
else if (!tick_long)
|
||||
pacetimer <= pacetimer + 1;
|
||||
pacetimer <= pacetimer + 1'd1;
|
||||
end
|
||||
assign tick_long = pacetimer == 22'h3fffff;
|
||||
assign tick_short = pacetimer == 22'h000fff;
|
||||
@@ -232,7 +234,7 @@ module ps2_kbd( input sysclk,
|
||||
always@(posedge sysclk or posedge reset)
|
||||
if (reset)
|
||||
inquiry_active <= 0;
|
||||
else begin
|
||||
else if (clk_en) begin
|
||||
if (strobe_out | strobe_in)
|
||||
inquiry_active <= 0;
|
||||
else if (tick_short)
|
||||
@@ -250,24 +252,24 @@ module ps2_kbd( input sysclk,
|
||||
/* Handle key_pending, and multi-byte keypad responses */
|
||||
reg keypad_byte2;
|
||||
always @(posedge sysclk or posedge reset)
|
||||
if (reset) begin
|
||||
key_pending <= 0;
|
||||
keypad_byte2 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (cmd_model | cmd_test)
|
||||
key_pending <= 0;
|
||||
else if (pop_key) begin
|
||||
if (keymac[8] & !keypad_byte2)
|
||||
keypad_byte2 <= 1;
|
||||
else begin
|
||||
key_pending <= 0;
|
||||
keypad_byte2 <= 0;
|
||||
end
|
||||
end
|
||||
else if (!key_pending & got_key && !got_break && !got_extend && !ignore_capslock)
|
||||
key_pending <= 1;
|
||||
end
|
||||
if (reset) begin
|
||||
key_pending <= 0;
|
||||
keypad_byte2 <= 0;
|
||||
end
|
||||
else if (clk_en) begin
|
||||
if (cmd_model | cmd_test)
|
||||
key_pending <= 0;
|
||||
else if (pop_key) begin
|
||||
if (keymac[8] & !keypad_byte2)
|
||||
keypad_byte2 <= 1;
|
||||
else begin
|
||||
key_pending <= 0;
|
||||
keypad_byte2 <= 0;
|
||||
end
|
||||
end
|
||||
else if (!key_pending & got_key && !got_break && !got_extend && !ignore_capslock)
|
||||
key_pending <= 1;
|
||||
end
|
||||
|
||||
/* Data to Mac */
|
||||
assign data_in = cmd_test ? 8'h7d :
|
||||
@@ -279,7 +281,7 @@ module ps2_kbd( input sysclk,
|
||||
* differently
|
||||
*/
|
||||
always @(posedge sysclk)
|
||||
if (got_key && !key_pending) begin
|
||||
if (clk_en && got_key && !key_pending) begin
|
||||
case({extended,ibyte}) // Scan Code Set 2
|
||||
9'h000: keymac[8:0] <= 9'h07b;
|
||||
9'h001: keymac[8:0] <= 9'h07b; //F9
|
||||
|
||||
@@ -12,17 +12,19 @@
|
||||
* PS2 Mouse to Mac interface module
|
||||
*/
|
||||
module ps2_mouse(input sysclk,
|
||||
input reset,
|
||||
input clk_en,
|
||||
input reset,
|
||||
|
||||
input ps2dat,
|
||||
input ps2clk,
|
||||
|
||||
output reg x1,
|
||||
output reg y1,
|
||||
output reg x2,
|
||||
output reg y2,
|
||||
output reg button
|
||||
input ps2dat,
|
||||
input ps2clk,
|
||||
|
||||
output reg x1,
|
||||
output reg y1,
|
||||
output reg x2,
|
||||
output reg y2,
|
||||
output reg button
|
||||
);
|
||||
|
||||
wire istrobe;
|
||||
wire [7:0] ibyte;
|
||||
wire timeout;
|
||||
@@ -40,19 +42,21 @@ module ps2_mouse(input sysclk,
|
||||
reg [11:0] clkdiv;
|
||||
wire tick;
|
||||
wire[1:0] dbg_lowstate;
|
||||
|
||||
|
||||
ps2 ps20(.sysclk(sysclk),
|
||||
.reset(reset),
|
||||
.ps2dat(ps2dat),
|
||||
.ps2clk(ps2clk),
|
||||
.istrobe(istrobe),
|
||||
.ibyte(ibyte),
|
||||
.oreq(oreq),
|
||||
.obyte(obyte),
|
||||
.oack(oack),
|
||||
.timeout(timeout),
|
||||
.dbg_state(dbg_lowstate));
|
||||
|
||||
.clk_en(clk_en),
|
||||
.reset(reset),
|
||||
.ps2dat(ps2dat),
|
||||
.ps2clk(ps2clk),
|
||||
.istrobe(istrobe),
|
||||
.ibyte(ibyte),
|
||||
.oreq(oreq),
|
||||
.obyte(obyte),
|
||||
.oack(oack),
|
||||
.timeout(timeout),
|
||||
.dbg_state(dbg_lowstate)
|
||||
);
|
||||
|
||||
/* State machine:
|
||||
*
|
||||
* - at state_init: wait for BAT reply
|
||||
@@ -149,24 +153,26 @@ module ps2_mouse(input sysclk,
|
||||
always@(posedge sysclk or posedge reset)
|
||||
if (reset)
|
||||
state <= ps2m_state_byte0; // ps2m_state_init
|
||||
else
|
||||
else if (clk_en)
|
||||
state <= next;
|
||||
|
||||
always@(posedge sysclk or posedge reset)
|
||||
if (reset)
|
||||
oreq <= 0;
|
||||
else
|
||||
else if (clk_en)
|
||||
oreq <= nreq;
|
||||
|
||||
always@(posedge sysclk or posedge reset)
|
||||
if (reset)
|
||||
obyte <= 0;
|
||||
else
|
||||
else if (clk_en)
|
||||
obyte <= nbyte;
|
||||
|
||||
/* Capture button state */
|
||||
always@(posedge sysclk or posedge reset)
|
||||
if (reset)
|
||||
button <= 1;
|
||||
else if (istrobe && state == ps2m_state_byte0)
|
||||
else if (clk_en && istrobe && state == ps2m_state_byte0)
|
||||
if(ibyte[3])
|
||||
button <= ~ibyte[0];
|
||||
|
||||
@@ -174,7 +180,7 @@ module ps2_mouse(input sysclk,
|
||||
always@(posedge sysclk or posedge reset)
|
||||
if (reset)
|
||||
clkdiv <= 0;
|
||||
else
|
||||
else if (clk_en)
|
||||
clkdiv <= clkdiv + 1'b1;
|
||||
assign tick = clkdiv == 0;
|
||||
|
||||
@@ -183,7 +189,7 @@ module ps2_mouse(input sysclk,
|
||||
if (reset) begin
|
||||
x1 <= 0;
|
||||
x2 <= 0;
|
||||
end else if (tick && xacc != 0) begin
|
||||
end else if (clk_en && tick && xacc != 0) begin
|
||||
x1 <= ~x1;
|
||||
x2 <= ~x1 ^ ~xacc[9];
|
||||
end
|
||||
@@ -192,7 +198,7 @@ module ps2_mouse(input sysclk,
|
||||
if (reset) begin
|
||||
y1 <= 0;
|
||||
y2 <= 0;
|
||||
end else if (tick && yacc != 0) begin
|
||||
end else if (clk_en && tick && yacc != 0) begin
|
||||
y1 <= ~y1;
|
||||
y2 <= ~y1 ^ ~yacc[9];
|
||||
end
|
||||
@@ -215,7 +221,7 @@ module ps2_mouse(input sysclk,
|
||||
always@(posedge sysclk or posedge reset) begin
|
||||
if (reset)
|
||||
xacc <= 0;
|
||||
else begin
|
||||
else if (clk_en) begin
|
||||
/* Add movement, convert to a 10-bit number if not over */
|
||||
if (istrobe && state == ps2m_state_byte1 && xacc[8] == xacc[9])
|
||||
xacc <= xacc + { xsign, xsign, ibyte };
|
||||
@@ -229,7 +235,7 @@ module ps2_mouse(input sysclk,
|
||||
always@(posedge sysclk or posedge reset) begin
|
||||
if (reset)
|
||||
yacc <= 0;
|
||||
else begin
|
||||
else if (clk_en) begin
|
||||
/* Add movement, convert to a 10-bit number if not over*/
|
||||
if (istrobe && state == ps2m_state_byte2 && yacc[8] == yacc[9])
|
||||
yacc <= yacc + { ysign, ysign, ibyte };
|
||||
|
||||
@@ -12,48 +12,49 @@
|
||||
* for now, it's all very simplified
|
||||
*/
|
||||
|
||||
module scc(input sysclk,
|
||||
input reset_hw,
|
||||
module scc
|
||||
(
|
||||
input clk,
|
||||
input cep,
|
||||
input cen,
|
||||
|
||||
input reset_hw,
|
||||
|
||||
/* Bus interface. 2-bit address, to be wired
|
||||
* appropriately upstream (to A1..A2).
|
||||
*/
|
||||
input cs,
|
||||
input we,
|
||||
input [1:0] rs, /* [1] = data(1)/ctl [0] = a_side(1)/b_side */
|
||||
input [7:0] wdata,
|
||||
output [7:0] rdata,
|
||||
output _irq,
|
||||
/* Bus interface. 2-bit address, to be wired
|
||||
* appropriately upstream (to A1..A2).
|
||||
*/
|
||||
input cs,
|
||||
input we,
|
||||
input [1:0] rs, /* [1] = data(1)/ctl [0] = a_side(1)/b_side */
|
||||
input [7:0] wdata,
|
||||
output [7:0] rdata,
|
||||
output _irq,
|
||||
|
||||
/* A single serial port on Minimig */
|
||||
input rxd,
|
||||
output txd,
|
||||
input cts, /* normally wired to device DTR output
|
||||
* on Mac cables. That same line is also
|
||||
* connected to the TRxC input of the SCC
|
||||
* to do fast clocking but we don't do that
|
||||
* here
|
||||
*/
|
||||
output rts, /* on a real mac this activates line
|
||||
* drivers when low */
|
||||
/* A single serial port on Minimig */
|
||||
input rxd,
|
||||
output txd,
|
||||
input cts, /* normally wired to device DTR output
|
||||
* on Mac cables. That same line is also
|
||||
* connected to the TRxC input of the SCC
|
||||
* to do fast clocking but we don't do that
|
||||
* here
|
||||
*/
|
||||
output rts, /* on a real mac this activates line
|
||||
* drivers when low */
|
||||
|
||||
/* DCD for both ports are hijacked by mouse interface */
|
||||
input dcd_a, /* We don't synchronize those inputs */
|
||||
input dcd_b,
|
||||
/* DCD for both ports are hijacked by mouse interface */
|
||||
input dcd_a, /* We don't synchronize those inputs */
|
||||
input dcd_b,
|
||||
|
||||
/* Write request */
|
||||
output wreq
|
||||
);
|
||||
/* Write request */
|
||||
output wreq
|
||||
);
|
||||
|
||||
/* Register access is semi-insane */
|
||||
reg [3:0] rindex;
|
||||
reg [3:0] rindex_latch;
|
||||
wire wreg_a;
|
||||
wire wreg_b;
|
||||
wire wdata_a;
|
||||
wire wdata_b;
|
||||
wire rdata_a;
|
||||
wire rdata_b;
|
||||
|
||||
/* Resets via WR9, one clk pulses */
|
||||
wire reset_a;
|
||||
@@ -83,23 +84,15 @@ module scc(input sysclk,
|
||||
reg [7:0] wr1_a;
|
||||
reg [7:0] wr1_b;
|
||||
reg [7:0] wr2;
|
||||
reg [7:0] wr3_a;
|
||||
reg [7:0] wr3_b;
|
||||
reg [7:0] wr4_a;
|
||||
reg [7:0] wr4_b;
|
||||
reg [7:0] wr5_a;
|
||||
reg [7:0] wr5_b;
|
||||
reg [7:0] wr6_a;
|
||||
reg [7:0] wr6_b;
|
||||
reg [7:0] wr7_a;
|
||||
reg [7:0] wr7_b;
|
||||
reg [7:0] wr8_a;
|
||||
reg [7:0] wr8_b;
|
||||
reg [5:0] wr9;
|
||||
reg [7:0] wr10_a;
|
||||
reg [7:0] wr10_b;
|
||||
reg [7:0] wr11_a;
|
||||
reg [7:0] wr11_b;
|
||||
reg [7:0] wr12_a;
|
||||
reg [7:0] wr12_b;
|
||||
reg [7:0] wr13_a;
|
||||
@@ -135,23 +128,18 @@ module scc(input sysclk,
|
||||
/* Register/Data access helpers */
|
||||
assign wreg_a = cs & we & (~rs[1]) & rs[0];
|
||||
assign wreg_b = cs & we & (~rs[1]) & ~rs[0];
|
||||
assign wdata_a = cs & we & (rs[1] | (rindex == 8)) & rs[0];
|
||||
assign wdata_b = cs & we & (rs[1] | (rindex == 8)) & ~rs[0];
|
||||
assign rdata_a = cs & (~we) & (rs[1] | (rindex == 8)) & rs[0];
|
||||
assign rdata_b = cs & (~we) & (rs[1] | (rindex == 8)) & ~rs[0];
|
||||
|
||||
// make sure rindex changes after the cpu cycle has ended so
|
||||
// read data is still stable while cpu advances
|
||||
always@(negedge sysclk)
|
||||
rindex <= rindex_latch;
|
||||
always@(posedge clk) if(cen) rindex <= rindex_latch;
|
||||
|
||||
/* Register index is set by a write to WR0 and reset
|
||||
* after any subsequent write. We ignore the side
|
||||
*/
|
||||
always@(negedge sysclk or posedge reset) begin
|
||||
always@(posedge clk or posedge reset) begin
|
||||
if (reset)
|
||||
rindex_latch <= 0;
|
||||
else if (cs && !rs[1]) begin
|
||||
else if (cen && cs && !rs[1]) begin
|
||||
/* Default, reset index */
|
||||
rindex_latch <= 0;
|
||||
|
||||
@@ -179,20 +167,20 @@ module scc(input sysclk,
|
||||
|
||||
/* WR1
|
||||
* Reset: bit 5 and 2 unchanged */
|
||||
always@(negedge sysclk or posedge reset_hw) begin
|
||||
always@(posedge clk or posedge reset_hw) begin
|
||||
if (reset_hw)
|
||||
wr1_a <= 0;
|
||||
else begin
|
||||
else if(cen) begin
|
||||
if (reset_a)
|
||||
wr1_a <= { 2'b00, wr1_a[5], 2'b00, wr1_a[2], 2'b00 };
|
||||
else if (wreg_a && rindex == 1)
|
||||
wr1_a <= wdata;
|
||||
end
|
||||
end
|
||||
always@(negedge sysclk or posedge reset_hw) begin
|
||||
always@(posedge clk or posedge reset_hw) begin
|
||||
if (reset_hw)
|
||||
wr1_b <= 0;
|
||||
else begin
|
||||
else if(cen) begin
|
||||
if (reset_b)
|
||||
wr1_b <= { 2'b00, wr1_b[5], 2'b00, wr1_b[2], 2'b00 };
|
||||
else if (wreg_b && rindex == 1)
|
||||
@@ -203,78 +191,30 @@ module scc(input sysclk,
|
||||
/* WR2
|
||||
* Reset: unchanged
|
||||
*/
|
||||
always@(negedge sysclk or posedge reset_hw) begin
|
||||
always@(posedge clk or posedge reset_hw) begin
|
||||
if (reset_hw)
|
||||
wr2 <= 0;
|
||||
else if ((wreg_a || wreg_b) && rindex == 2)
|
||||
else if (cen && (wreg_a || wreg_b) && rindex == 2)
|
||||
wr2 <= wdata;
|
||||
end
|
||||
|
||||
/* WR3
|
||||
* Reset: bit 0 to 0, otherwise unchanged.
|
||||
*/
|
||||
always@(negedge sysclk or posedge reset_hw) begin
|
||||
if (reset_hw)
|
||||
wr3_a <= 0;
|
||||
else begin
|
||||
if (reset_a)
|
||||
wr3_a[0] <= 0;
|
||||
else if (wreg_a && rindex == 3)
|
||||
wr3_a <= wdata;
|
||||
end
|
||||
end
|
||||
always@(negedge sysclk or posedge reset_hw) begin
|
||||
if (reset_hw)
|
||||
wr3_b <= 0;
|
||||
else begin
|
||||
if (reset_b)
|
||||
wr3_b[0] <= 0;
|
||||
else if (wreg_b && rindex == 3)
|
||||
wr3_b <= wdata;
|
||||
end
|
||||
end
|
||||
|
||||
/* WR4
|
||||
* Reset: Bit 2 to 1, otherwise unchanged
|
||||
*/
|
||||
always@(negedge sysclk or posedge reset_hw) begin
|
||||
if (reset_hw)
|
||||
wr4_a <= 0;
|
||||
else begin
|
||||
if (reset_a)
|
||||
wr4_a[2] <= 1;
|
||||
else if (wreg_a && rindex == 4)
|
||||
wr4_a <= wdata;
|
||||
end
|
||||
end
|
||||
always@(negedge sysclk or posedge reset_hw) begin
|
||||
if (reset_hw)
|
||||
wr4_b <= 0;
|
||||
else begin
|
||||
if (reset_b)
|
||||
wr4_b[2] <= 1;
|
||||
else if (wreg_b && rindex == 4)
|
||||
wr4_b <= wdata;
|
||||
end
|
||||
end
|
||||
|
||||
/* WR5
|
||||
* Reset: Bits 7,4,3,2,1 to 0
|
||||
*/
|
||||
always@(negedge sysclk or posedge reset_hw) begin
|
||||
always@(posedge clk or posedge reset_hw) begin
|
||||
if (reset_hw)
|
||||
wr5_a <= 0;
|
||||
else begin
|
||||
else if(cen) begin
|
||||
if (reset_a)
|
||||
wr5_a <= { 1'b0, wr5_a[6:5], 4'b0000, wr5_a[0] };
|
||||
else if (wreg_a && rindex == 5)
|
||||
wr5_a <= wdata;
|
||||
end
|
||||
end
|
||||
always@(negedge sysclk or posedge reset_hw) begin
|
||||
always@(posedge clk or posedge reset_hw) begin
|
||||
if (reset_hw)
|
||||
wr5_b <= 0;
|
||||
else begin
|
||||
else if(cen) begin
|
||||
if (reset_b)
|
||||
wr5_b <= { 1'b0, wr5_b[6:5], 4'b0000, wr5_b[0] };
|
||||
else if (wreg_b && rindex == 5)
|
||||
@@ -282,65 +222,33 @@ module scc(input sysclk,
|
||||
end
|
||||
end
|
||||
|
||||
/* WR6
|
||||
* Reset: Unchanged.
|
||||
*/
|
||||
always@(negedge sysclk or posedge reset_hw) begin
|
||||
if (reset_hw)
|
||||
wr6_a <= 0;
|
||||
else if (wreg_a && rindex == 6)
|
||||
wr6_a <= wdata;
|
||||
end
|
||||
always@(negedge sysclk or posedge reset_hw) begin
|
||||
if (reset_hw)
|
||||
wr6_b <= 0;
|
||||
else if (wreg_b && rindex == 6)
|
||||
wr6_b <= wdata;
|
||||
end
|
||||
|
||||
/* WR7
|
||||
* Reset: Unchanged.
|
||||
*/
|
||||
always@(negedge sysclk or posedge reset_hw) begin
|
||||
if (reset_hw)
|
||||
wr7_a <= 0;
|
||||
else if (wreg_a && rindex == 7)
|
||||
wr7_a <= wdata;
|
||||
end
|
||||
always@(negedge sysclk or posedge reset_hw) begin
|
||||
if (reset_hw)
|
||||
wr7_b <= 0;
|
||||
else if (wreg_b && rindex == 7)
|
||||
wr7_b <= wdata;
|
||||
end
|
||||
|
||||
/* WR9. Special: top bits are reset, handled separately, bottom
|
||||
* bits are only reset by a hw reset
|
||||
*/
|
||||
always@(negedge sysclk or posedge reset_hw) begin
|
||||
always@(posedge clk or posedge reset_hw) begin
|
||||
if (reset_hw)
|
||||
wr9 <= 0;
|
||||
else if ((wreg_a || wreg_b) && rindex == 9)
|
||||
else if (cen && (wreg_a || wreg_b) && rindex == 9)
|
||||
wr9 <= wdata[5:0];
|
||||
end
|
||||
|
||||
/* WR10
|
||||
* Reset: all 0, except chanel reset retains 6 and 5
|
||||
*/
|
||||
always@(negedge sysclk or posedge reset) begin
|
||||
always@(posedge clk or posedge reset) begin
|
||||
if (reset)
|
||||
wr10_a <= 0;
|
||||
else begin
|
||||
else if(cen) begin
|
||||
if (reset_a)
|
||||
wr10_a <= { 1'b0, wr10_a[6:5], 5'b00000 };
|
||||
else if (wreg_a && rindex == 10)
|
||||
wr10_a <= wdata;
|
||||
end
|
||||
end
|
||||
always@(negedge sysclk or posedge reset) begin
|
||||
always@(posedge clk or posedge reset) begin
|
||||
if (reset)
|
||||
wr10_b <= 0;
|
||||
else begin
|
||||
else if(cen) begin
|
||||
if (reset_b)
|
||||
wr10_b <= { 1'b0, wr10_b[6:5], 5'b00000 };
|
||||
else if (wreg_b && rindex == 10)
|
||||
@@ -348,51 +256,35 @@ module scc(input sysclk,
|
||||
end
|
||||
end
|
||||
|
||||
/* WR11
|
||||
* Reset: On full reset only, not channel reset
|
||||
*/
|
||||
always@(negedge sysclk or posedge reset) begin
|
||||
if (reset)
|
||||
wr11_a <= 8'b00001000;
|
||||
else if (wreg_a && rindex == 11)
|
||||
wr11_a <= wdata;
|
||||
end
|
||||
always@(negedge sysclk or posedge reset) begin
|
||||
if (reset)
|
||||
wr11_b <= 8'b00001000;
|
||||
else if (wreg_b && rindex == 11)
|
||||
wr11_b <= wdata;
|
||||
end
|
||||
|
||||
/* WR12
|
||||
* Reset: Unchanged
|
||||
*/
|
||||
always@(negedge sysclk or posedge reset_hw) begin
|
||||
always@(posedge clk or posedge reset_hw) begin
|
||||
if (reset_hw)
|
||||
wr12_a <= 0;
|
||||
else if (wreg_a && rindex == 12)
|
||||
else if (cen && wreg_a && rindex == 12)
|
||||
wr12_a <= wdata;
|
||||
end
|
||||
always@(negedge sysclk or posedge reset_hw) begin
|
||||
always@(posedge clk or posedge reset_hw) begin
|
||||
if (reset_hw)
|
||||
wr12_b <= 0;
|
||||
else if (wreg_b && rindex == 12)
|
||||
else if (cen && wreg_b && rindex == 12)
|
||||
wr12_b <= wdata;
|
||||
end
|
||||
|
||||
/* WR13
|
||||
* Reset: Unchanged
|
||||
*/
|
||||
always@(negedge sysclk or posedge reset_hw) begin
|
||||
always@(posedge clk or posedge reset_hw) begin
|
||||
if (reset_hw)
|
||||
wr13_a <= 0;
|
||||
else if (wreg_a && rindex == 13)
|
||||
else if (cen && wreg_a && rindex == 13)
|
||||
wr13_a <= wdata;
|
||||
end
|
||||
always@(negedge sysclk or posedge reset_hw) begin
|
||||
always@(posedge clk or posedge reset_hw) begin
|
||||
if (reset_hw)
|
||||
wr13_b <= 0;
|
||||
else if (wreg_b && rindex == 13)
|
||||
else if (cen && wreg_b && rindex == 13)
|
||||
wr13_b <= wdata;
|
||||
end
|
||||
|
||||
@@ -401,10 +293,10 @@ module scc(input sysclk,
|
||||
* Chan reset also maitains bottom 2 bits, bit 4 also
|
||||
* reset to a different value
|
||||
*/
|
||||
always@(negedge sysclk or posedge reset_hw) begin
|
||||
always@(posedge clk or posedge reset_hw) begin
|
||||
if (reset_hw)
|
||||
wr14_a <= 0;
|
||||
else begin
|
||||
else if(cen) begin
|
||||
if (reset)
|
||||
wr14_a <= { wr14_a[7:6], 6'b110000 };
|
||||
else if (reset_a)
|
||||
@@ -413,10 +305,10 @@ module scc(input sysclk,
|
||||
wr14_a <= wdata;
|
||||
end
|
||||
end
|
||||
always@(negedge sysclk or posedge reset_hw) begin
|
||||
always@(posedge clk or posedge reset_hw) begin
|
||||
if (reset_hw)
|
||||
wr14_b <= 0;
|
||||
else begin
|
||||
else if(cen) begin
|
||||
if (reset)
|
||||
wr14_b <= { wr14_b[7:6], 6'b110000 };
|
||||
else if (reset_b)
|
||||
@@ -427,11 +319,11 @@ module scc(input sysclk,
|
||||
end
|
||||
|
||||
/* WR15 */
|
||||
always@(negedge sysclk or posedge reset) begin
|
||||
always@(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
wr15_a <= 8'b11111000;
|
||||
wr15_b <= 8'b11111000;
|
||||
end else if (rindex == 15) begin
|
||||
end else if (cen && rindex == 15) begin
|
||||
if(wreg_a) wr15_a <= wdata;
|
||||
if(wreg_b) wr15_b <= wdata;
|
||||
end
|
||||
@@ -622,38 +514,42 @@ module scc(input sysclk,
|
||||
assign do_latch_b = latch_open_b & (dcd_ip_b /* | cts... */);
|
||||
|
||||
/* "Master" interrupt, set when latch close & WR1[0] is set */
|
||||
always@(posedge sysclk or posedge reset) begin
|
||||
always@(posedge clk or posedge reset) begin
|
||||
if (reset)
|
||||
ex_irq_ip_a <= 0;
|
||||
else if (do_extreset_a)
|
||||
ex_irq_ip_a <= 0;
|
||||
else if (do_latch_a && wr1_a[0])
|
||||
ex_irq_ip_a <= 1;
|
||||
else if(cep) begin
|
||||
if (do_extreset_a)
|
||||
ex_irq_ip_a <= 0;
|
||||
else if (do_latch_a && wr1_a[0])
|
||||
ex_irq_ip_a <= 1;
|
||||
end
|
||||
end
|
||||
always@(posedge sysclk or posedge reset) begin
|
||||
always@(posedge clk or posedge reset) begin
|
||||
if (reset)
|
||||
ex_irq_ip_b <= 0;
|
||||
else if (do_extreset_b)
|
||||
ex_irq_ip_b <= 0;
|
||||
else if (do_latch_b && wr1_b[0])
|
||||
ex_irq_ip_b <= 1;
|
||||
else if(cep) begin
|
||||
if (do_extreset_b)
|
||||
ex_irq_ip_b <= 0;
|
||||
else if (do_latch_b && wr1_b[0])
|
||||
ex_irq_ip_b <= 1;
|
||||
end
|
||||
end
|
||||
|
||||
/* Latch open/close control */
|
||||
always@(posedge sysclk or posedge reset) begin
|
||||
always@(posedge clk or posedge reset) begin
|
||||
if (reset)
|
||||
latch_open_a <= 1;
|
||||
else begin
|
||||
else if(cep) begin
|
||||
if (do_extreset_a)
|
||||
latch_open_a <= 1;
|
||||
else if (do_latch_a)
|
||||
latch_open_a <= 0;
|
||||
end
|
||||
end
|
||||
always@(posedge sysclk or posedge reset) begin
|
||||
always@(posedge clk or posedge reset) begin
|
||||
if (reset)
|
||||
latch_open_b <= 1;
|
||||
else begin
|
||||
else if(cep) begin
|
||||
if (do_extreset_b)
|
||||
latch_open_b <= 1;
|
||||
else if (do_latch_b)
|
||||
@@ -662,27 +558,27 @@ module scc(input sysclk,
|
||||
end
|
||||
|
||||
/* Latches proper */
|
||||
always@(posedge sysclk or posedge reset) begin
|
||||
always@(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
dcd_latch_a <= 0;
|
||||
/* cts ... */
|
||||
end else begin
|
||||
end else if(cep) begin
|
||||
if (do_latch_a)
|
||||
dcd_latch_a <= dcd_a;
|
||||
/* cts ... */
|
||||
end
|
||||
end
|
||||
always@(posedge sysclk or posedge reset) begin
|
||||
always@(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
dcd_latch_b <= 0;
|
||||
/* cts ... */
|
||||
end else begin
|
||||
end else if(cep) begin
|
||||
if (do_latch_b)
|
||||
dcd_latch_b <= dcd_b;
|
||||
/* cts ... */
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/* NYI */
|
||||
assign txd = 1;
|
||||
assign rts = 1;
|
||||
|
||||
@@ -1,390 +1,348 @@
|
||||
/* verilator lint_off UNUSED */
|
||||
/* verilator lint_off SYNCASYNCNET */
|
||||
|
||||
// scsi.v
|
||||
// implements a target only scsi device
|
||||
|
||||
module scsi(input sysclk,
|
||||
|
||||
// scsi interface
|
||||
input rst, // bus reset from initiator
|
||||
input sel,
|
||||
input atn, // initiator requests to send a message
|
||||
output bsy, // target holds bus
|
||||
|
||||
output msg,
|
||||
output cd,
|
||||
output io,
|
||||
|
||||
output req,
|
||||
input ack, // initiator acknowledges a request
|
||||
|
||||
input [7:0] din, // data from initiator to target
|
||||
output [7:0] dout, // data from target to initiator
|
||||
|
||||
// interface to io controller
|
||||
output [31:0] io_lba,
|
||||
output reg io_rd,
|
||||
output reg io_wr,
|
||||
input io_ack,
|
||||
|
||||
// data sent to io controller
|
||||
output reg [7:0] io_dout,
|
||||
input io_dout_strobe,
|
||||
|
||||
// data coming in from io controller
|
||||
input [7:0] io_din,
|
||||
input io_din_strobe
|
||||
|
||||
);
|
||||
|
||||
|
||||
// SCSI device id
|
||||
parameter ID = 0;
|
||||
|
||||
`define PHASE_IDLE 3'd0
|
||||
`define PHASE_CMD_IN 3'd1
|
||||
`define PHASE_DATA_OUT 3'd2
|
||||
`define PHASE_DATA_IN 3'd3
|
||||
`define PHASE_STATUS_OUT 3'd4
|
||||
`define PHASE_MESSAGE_OUT 3'd5
|
||||
reg [2:0] phase;
|
||||
|
||||
reg cmd_in;
|
||||
always @(posedge sysclk)
|
||||
cmd_in <= (phase == `PHASE_CMD_IN);
|
||||
|
||||
// ---------------- buffer read engine -----------------------
|
||||
// the buffer itself. Can hold one sector
|
||||
reg [7:0] buffer_out [511:0];
|
||||
reg [8:0] buffer_out_rptr;
|
||||
reg buffer_out_read_strobe;
|
||||
|
||||
always @(posedge io_dout_strobe or posedge cmd_cpl_strobe) begin
|
||||
if(cmd_cpl_strobe) buffer_out_rptr <= 9'd0;
|
||||
else begin
|
||||
io_dout <= buffer_out[buffer_out_rptr];
|
||||
buffer_out_rptr <= buffer_out_rptr + 9'd1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// ---------------- buffer write engine -----------------------
|
||||
// the buffer itself. Can hold one sector
|
||||
reg [7:0] buffer_in [511:0];
|
||||
reg [8:0] buffer_in_wptr;
|
||||
reg buffer_in_write_strobe;
|
||||
|
||||
always @(posedge io_din_strobe)
|
||||
buffer_in[buffer_in_wptr] <= io_din;
|
||||
|
||||
wire cmd_cpl_strobe = cmd_in && cmd_cpl;
|
||||
always @(negedge io_din_strobe or posedge cmd_cpl_strobe) begin
|
||||
if(cmd_cpl_strobe) buffer_in_wptr <= 9'd0;
|
||||
else buffer_in_wptr <= buffer_in_wptr + 9'd1;
|
||||
end
|
||||
|
||||
// status replies
|
||||
reg [7:0] status;
|
||||
`define STATUS_OK 8'h00
|
||||
`define STATUS_CHECK_CONDITION 8'h02
|
||||
|
||||
// message codes
|
||||
`define MSG_CMD_COMPLETE 8'h00
|
||||
|
||||
// drive scsi signals according to phase
|
||||
assign msg = (phase == `PHASE_MESSAGE_OUT);
|
||||
assign cd = (phase == `PHASE_CMD_IN) || (phase == `PHASE_STATUS_OUT) || (phase == `PHASE_MESSAGE_OUT);
|
||||
assign io = (phase == `PHASE_DATA_OUT) || (phase == `PHASE_STATUS_OUT) || (phase == `PHASE_MESSAGE_OUT);
|
||||
assign req = (phase != `PHASE_IDLE) && !ack && !io_rd && !io_wr;
|
||||
assign bsy = (phase != `PHASE_IDLE);
|
||||
|
||||
assign dout = (phase == `PHASE_STATUS_OUT)?status:
|
||||
(phase == `PHASE_MESSAGE_OUT)?`MSG_CMD_COMPLETE:
|
||||
(phase == `PHASE_DATA_OUT)?cmd_dout:
|
||||
8'h00;
|
||||
|
||||
// de-multiplex different data sources
|
||||
wire [7:0] cmd_dout =
|
||||
cmd_read?buffer_dout:
|
||||
cmd_inquiry?inquiry_dout:
|
||||
cmd_read_capacity?read_capacity_dout:
|
||||
cmd_mode_sense?mode_sense_dout:
|
||||
8'h00;
|
||||
|
||||
// output of inquiry command, identify as "SEAGATE ST225N"
|
||||
wire [7:0] inquiry_dout =
|
||||
(data_cnt == 32'd4 )?8'd32: // length
|
||||
|
||||
(data_cnt == 32'd8 )?" ":(data_cnt == 32'd9 )?"S":
|
||||
(data_cnt == 32'd10)?"E":(data_cnt == 32'd11)?"A":
|
||||
(data_cnt == 32'd12)?"G":(data_cnt == 32'd13)?"A":
|
||||
(data_cnt == 32'd14)?"T":(data_cnt == 32'd15)?"E":
|
||||
(data_cnt == 32'd16)?" ":(data_cnt == 32'd17)?" ":
|
||||
(data_cnt == 32'd18)?" ":(data_cnt == 32'd19)?" ":
|
||||
(data_cnt == 32'd20)?" ":(data_cnt == 32'd21)?" ":
|
||||
(data_cnt == 32'd22)?" ":(data_cnt == 32'd23)?" ":
|
||||
(data_cnt == 32'd24)?" ":(data_cnt == 32'd25)?" ":
|
||||
|
||||
(data_cnt == 32'd26)?"S":(data_cnt == 32'd27)?"T":
|
||||
(data_cnt == 32'd28)?"2":(data_cnt == 32'd29)?"2":
|
||||
(data_cnt == 32'd30)?"5":(data_cnt == 32'd31)?"N":
|
||||
8'h00;
|
||||
|
||||
// output of read capacity command
|
||||
wire [31:0] capacity = 32'd41056; // 40960 + 96 blocks = 20MB
|
||||
wire [31:0] capacity_m1 = capacity - 32'd1;
|
||||
wire [7:0] read_capacity_dout =
|
||||
(data_cnt == 32'd0 )?capacity_m1[31:24]:
|
||||
(data_cnt == 32'd1 )?capacity_m1[23:16]:
|
||||
(data_cnt == 32'd2 )?capacity_m1[15:8]:
|
||||
(data_cnt == 32'd3 )?capacity_m1[7:0]:
|
||||
(data_cnt == 32'd6 )?8'd2: // 512 bytes per sector
|
||||
8'h00;
|
||||
|
||||
wire [7:0] mode_sense_dout =
|
||||
(data_cnt == 32'd3 )?8'd8:
|
||||
(data_cnt == 32'd5 )?capacity[23:16]:
|
||||
(data_cnt == 32'd6 )?capacity[15:8]:
|
||||
(data_cnt == 32'd7 )?capacity[7:0]:
|
||||
(data_cnt == 32'd10 )?8'd2:
|
||||
8'h00;
|
||||
|
||||
// clock data out of buffer to allow for embedded ram
|
||||
reg [7:0] buffer_dout;
|
||||
wire buffer_out_clk = req && !io_rd;
|
||||
always @(posedge sysclk) // buffer_out_clk)
|
||||
buffer_dout <= buffer_in[data_cnt];
|
||||
|
||||
// debug signals
|
||||
reg [7:0] dbg_cmds /* synthesis noprune */;
|
||||
always @(posedge cmd_cpl or posedge rst) begin
|
||||
if(rst) dbg_cmds <= 8'd0;
|
||||
else dbg_cmds <= dbg_cmds + 8'd1;
|
||||
end
|
||||
|
||||
// buffer to store incoming commands
|
||||
reg [3:0] cmd_cnt;
|
||||
reg [7:0] cmd [9:0];
|
||||
|
||||
/* ----------------------- request data from/to io controller ----------------------- */
|
||||
|
||||
// base address of current block. Subtract one when writing since the writing happens
|
||||
// after a block has been transferred and data_cnt has thus already been increased by 512
|
||||
assign io_lba = lba + { 9'd0, data_cnt[31:9] } -
|
||||
(cmd_write ? 32'd1 : 32'd0);
|
||||
|
||||
reg req_io_rd, req_io_wr;
|
||||
always @(posedge sysclk) begin
|
||||
// generate an io_rd signal whenever the first byte of a 512 byte block is required and io_wr whenever
|
||||
// the last byte of a 512 byte block has been revceived
|
||||
req_io_rd <= (phase == `PHASE_DATA_OUT) && cmd_read && (data_cnt[8:0] == 0) && !data_complete;
|
||||
// generate an io_wr signal whenever a 512 byte block has been received or when the status
|
||||
// phase of a write command has been reached
|
||||
req_io_wr <= (((phase == `PHASE_DATA_IN) && (data_cnt[8:0] == 0) && (data_cnt != 0)) ||
|
||||
(phase == `PHASE_STATUS_OUT)) && cmd_write;
|
||||
end
|
||||
|
||||
always @(posedge req_io_rd or posedge io_ack) begin
|
||||
if(io_ack) io_rd <= 1'b0;
|
||||
else io_rd <= 1'b1;
|
||||
end
|
||||
|
||||
always @(posedge req_io_wr or posedge io_ack) begin
|
||||
if(io_ack) io_wr <= 1'b0;
|
||||
else io_wr <= 1'b1;
|
||||
end
|
||||
|
||||
// store incoming command in buffer
|
||||
reg cmd_idle;
|
||||
always @(posedge sysclk)
|
||||
cmd_idle <= (phase == `PHASE_IDLE);
|
||||
|
||||
// store data on rising edge of ack, ...
|
||||
always @(posedge ack) begin
|
||||
if(phase == `PHASE_CMD_IN)
|
||||
cmd[cmd_cnt] <= din;
|
||||
if(phase == `PHASE_DATA_IN)
|
||||
buffer_out[data_cnt] <= din;
|
||||
end
|
||||
|
||||
// ... advance counter on falling edge
|
||||
always @(negedge ack or posedge cmd_idle) begin
|
||||
if(cmd_idle) cmd_cnt <= 4'd0;
|
||||
else if(cmd_cnt != 15) cmd_cnt <= cmd_cnt + 4'd1;
|
||||
end
|
||||
|
||||
// count data bytes. don't increase counter while we are waiting for data from
|
||||
// the io controller
|
||||
reg [31:0] data_cnt;
|
||||
reg data_complete;
|
||||
|
||||
reg data_io;
|
||||
always @(posedge sysclk)
|
||||
data_io <= (phase == `PHASE_DATA_OUT) || (phase == `PHASE_DATA_IN) ||
|
||||
(phase == `PHASE_STATUS_OUT) || (phase == `PHASE_MESSAGE_OUT);
|
||||
|
||||
// For block transfers tlen contains the number of 512 bytes blocks to transfer.
|
||||
// Most other commands have the bytes length stored in the transfer length field.
|
||||
// And some have a fixed length idependent from any header field.
|
||||
// The data transfer has finished once the data counter reaches this
|
||||
// number.
|
||||
wire [31:0] data_len =
|
||||
cmd_read_capacity?32'd8:
|
||||
cmd_read?{ 7'd0, tlen, 9'd0 }: // read command length is in 512 bytes blocks
|
||||
cmd_write?{ 7'd0, tlen, 9'd0 }: // write command length is in 512 bytes blocks
|
||||
{ 16'd0, tlen }; // inquiry etc have length in bytes
|
||||
|
||||
always @(negedge ack or negedge data_io) begin
|
||||
if(!data_io) begin
|
||||
data_cnt <= 32'd0;
|
||||
data_complete <= 1'b0;
|
||||
end else begin
|
||||
data_cnt <= data_cnt + 32'd1;
|
||||
data_complete <= (data_len - 32'd1) == data_cnt;
|
||||
end
|
||||
end
|
||||
|
||||
// check whether status byte has been sent
|
||||
wire status_out = (phase == `PHASE_STATUS_OUT);
|
||||
reg status_sent;
|
||||
always @(negedge ack or negedge status_out) begin
|
||||
if(!status_out) status_sent <= 1'b0;
|
||||
else status_sent <= 1'b1;
|
||||
end
|
||||
|
||||
// check whether message byte has been sent
|
||||
reg message_sent;
|
||||
wire message_out = (phase == `PHASE_MESSAGE_OUT);
|
||||
always @(negedge ack or negedge message_out) begin
|
||||
if(!message_out) message_sent <= 1'b0;
|
||||
else message_sent <= 1'b1;
|
||||
end
|
||||
|
||||
/* ----------------------- command decoding ------------------------------- */
|
||||
|
||||
wire cmd_wr_x = cmd_cpl && cmd_write && (tlen > 1);
|
||||
|
||||
|
||||
// parse commands
|
||||
wire [7:0] op_code = cmd[0];
|
||||
wire [2:0] cmd_group = op_code[7:5];
|
||||
wire [4:0] cmd_code = op_code[4:0];
|
||||
|
||||
wire cmd_unknown = cmd_cpl && !cmd_ok;
|
||||
|
||||
// check if a complete command has been received
|
||||
wire cmd_cpl = cmd6_cpl || cmd10_cpl;
|
||||
wire cmd6_cpl = (cmd_group == 3'b000) && (cmd_cnt == 6);
|
||||
wire cmd10_cpl = ((cmd_group == 3'b010) || (cmd_group == 3'b001)) && (cmd_cnt == 10);
|
||||
|
||||
// https://en.wikipedia.org/wiki/SCSI_command
|
||||
wire cmd_read = cmd_read6 || cmd_read10;
|
||||
wire cmd_read6 = (op_code == 8'h08);
|
||||
wire cmd_read10 = (op_code == 8'h28);
|
||||
wire cmd_write = cmd_write6 || cmd_write10;
|
||||
wire cmd_write6 = (op_code == 8'h0a);
|
||||
wire cmd_write10 = (op_code == 8'h2a);
|
||||
wire cmd_inquiry = (op_code == 8'h12);
|
||||
wire cmd_format = (op_code == 8'h04);
|
||||
wire cmd_mode_select = (op_code == 8'h15);
|
||||
wire cmd_mode_sense = (op_code == 8'h1a);
|
||||
wire cmd_test_unit_ready = (op_code == 8'h00);
|
||||
wire cmd_read_capacity = (op_code == 8'h25);
|
||||
|
||||
// valid command in buffer? TODO: check for valid command parameters
|
||||
wire cmd_ok = cmd_read || cmd_write || cmd_inquiry || cmd_test_unit_ready ||
|
||||
cmd_read_capacity || cmd_mode_select || cmd_format || cmd_mode_sense;
|
||||
|
||||
// latch parameters once command is complete
|
||||
reg [31:0] lba;
|
||||
reg [15:0] tlen;
|
||||
reg [2:0] lun;
|
||||
|
||||
always @(posedge sysclk) begin
|
||||
if(cmd_cpl && (phase == `PHASE_CMD_IN)) begin
|
||||
lba <= cmd6_cpl?{11'd0, lba6}:lba10;
|
||||
tlen <= cmd6_cpl?{7'd0, tlen6}:tlen10;
|
||||
lun <= cmd6_cpl?lun6:3'd0;
|
||||
end
|
||||
end
|
||||
|
||||
// logical block address
|
||||
wire [7:0] cmd1 = cmd[1];
|
||||
wire [2:0] lun6 = cmd1[7:5];
|
||||
wire [20:0] lba6 = { cmd1[4:0], cmd[2], cmd[3] };
|
||||
wire [31:0] lba10 = { cmd[2], cmd[3], cmd[4], cmd[5] };
|
||||
|
||||
// transfer length
|
||||
wire [8:0] tlen6 = (cmd[4] == 0)?9'd256:{1'b0,cmd[4]};
|
||||
wire [15:0] tlen10 = { cmd[7], cmd[8] };
|
||||
|
||||
|
||||
// the 5380 changes phase in the falling edge, thus we monitor it
|
||||
// on the rising edge
|
||||
always @(posedge sysclk) begin
|
||||
if(rst) begin
|
||||
phase <= `PHASE_IDLE;
|
||||
end else begin
|
||||
// case(phase)
|
||||
if(phase == `PHASE_IDLE) begin
|
||||
if(sel && din[ID]) // own id on bus during selection?
|
||||
phase <= `PHASE_CMD_IN;
|
||||
end
|
||||
|
||||
else if(phase == `PHASE_CMD_IN) begin
|
||||
// check if a full command is in the buffer
|
||||
if(cmd_cpl) begin
|
||||
// is this a supported and valid command?
|
||||
if(cmd_ok) begin
|
||||
// yes, continue
|
||||
status <= `STATUS_OK;
|
||||
|
||||
// continue according to command
|
||||
|
||||
// these commands return data
|
||||
if(cmd_read || cmd_inquiry || cmd_read_capacity || cmd_mode_sense)
|
||||
phase <= `PHASE_DATA_OUT;
|
||||
// these commands receive dataa
|
||||
else if(cmd_write || cmd_mode_select)
|
||||
phase <= `PHASE_DATA_IN;
|
||||
// and all other valid commands are just "ok"
|
||||
else
|
||||
phase <= `PHASE_STATUS_OUT;
|
||||
end else begin
|
||||
// no, report failure
|
||||
status <= `STATUS_CHECK_CONDITION;
|
||||
phase <= `PHASE_STATUS_OUT;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
else if(phase == `PHASE_DATA_OUT) begin
|
||||
if(data_complete)
|
||||
phase <= `PHASE_STATUS_OUT;
|
||||
end
|
||||
|
||||
else if(phase == `PHASE_DATA_IN) begin
|
||||
if(data_complete)
|
||||
phase <= `PHASE_STATUS_OUT;
|
||||
end
|
||||
|
||||
else if(phase == `PHASE_STATUS_OUT) begin
|
||||
if(status_sent)
|
||||
phase <= `PHASE_MESSAGE_OUT;
|
||||
end
|
||||
|
||||
else if(phase == `PHASE_MESSAGE_OUT) begin
|
||||
if(message_sent)
|
||||
phase <= `PHASE_IDLE;
|
||||
end
|
||||
|
||||
else
|
||||
phase <= `PHASE_IDLE; // should never happen
|
||||
|
||||
// endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
/* verilator lint_off UNUSED */
|
||||
/* verilator lint_off SYNCASYNCNET */
|
||||
|
||||
// scsi.v
|
||||
// implements a target only scsi device
|
||||
|
||||
module scsi
|
||||
(
|
||||
input clk,
|
||||
|
||||
// scsi interface
|
||||
input rst, // bus reset from initiator
|
||||
input sel,
|
||||
input atn, // initiator requests to send a message
|
||||
output bsy, // target holds bus
|
||||
|
||||
output msg,
|
||||
output cd,
|
||||
output io,
|
||||
|
||||
output req,
|
||||
input ack, // initiator acknowledges a request
|
||||
|
||||
input [7:0] din, // data from initiator to target
|
||||
output [7:0] dout, // data from target to initiator
|
||||
|
||||
// interface to io controller
|
||||
input img_mounted,
|
||||
input [23:0] img_blocks,
|
||||
output [31:0] io_lba,
|
||||
output reg io_rd,
|
||||
output reg io_wr,
|
||||
input io_ack,
|
||||
|
||||
input [8:0] sd_buff_addr,
|
||||
input [7:0] sd_buff_dout,
|
||||
output reg [7:0] sd_buff_din,
|
||||
input sd_buff_wr
|
||||
);
|
||||
|
||||
|
||||
// SCSI device id
|
||||
parameter [7:0] ID = 0;
|
||||
|
||||
`define PHASE_IDLE 3'd0
|
||||
`define PHASE_CMD_IN 3'd1
|
||||
`define PHASE_DATA_OUT 3'd2
|
||||
`define PHASE_DATA_IN 3'd3
|
||||
`define PHASE_STATUS_OUT 3'd4
|
||||
`define PHASE_MESSAGE_OUT 3'd5
|
||||
reg [2:0] phase;
|
||||
|
||||
// ---------------- buffer read engine -----------------------
|
||||
// the buffer itself. Can hold one sector
|
||||
reg [7:0] buffer_out [512];
|
||||
always @(posedge clk) sd_buff_din <= buffer_out[sd_buff_addr];
|
||||
|
||||
// ---------------- buffer write engine ----------------------
|
||||
// the buffer itself. Can hold one sector
|
||||
reg [7:0] buffer_in [512];
|
||||
always @(posedge clk) if(sd_buff_wr) buffer_in[sd_buff_addr] <= sd_buff_dout;
|
||||
|
||||
// -----------------------------------------------------------
|
||||
|
||||
// status replies
|
||||
reg [7:0] status;
|
||||
`define STATUS_OK 8'h00
|
||||
`define STATUS_CHECK_CONDITION 8'h02
|
||||
|
||||
// message codes
|
||||
`define MSG_CMD_COMPLETE 8'h00
|
||||
|
||||
// drive scsi signals according to phase
|
||||
assign msg = (phase == `PHASE_MESSAGE_OUT);
|
||||
assign cd = (phase == `PHASE_CMD_IN) || (phase == `PHASE_STATUS_OUT) || (phase == `PHASE_MESSAGE_OUT);
|
||||
assign io = (phase == `PHASE_DATA_OUT) || (phase == `PHASE_STATUS_OUT) || (phase == `PHASE_MESSAGE_OUT);
|
||||
assign req = (phase != `PHASE_IDLE) && !ack && !io_rd && !io_wr && !io_ack;
|
||||
assign bsy = (phase != `PHASE_IDLE);
|
||||
|
||||
assign dout = (phase == `PHASE_STATUS_OUT)?status:
|
||||
(phase == `PHASE_MESSAGE_OUT)?`MSG_CMD_COMPLETE:
|
||||
(phase == `PHASE_DATA_OUT)?cmd_dout:
|
||||
8'h00;
|
||||
|
||||
// de-multiplex different data sources
|
||||
wire [7:0] cmd_dout =
|
||||
cmd_read?buffer_dout:
|
||||
cmd_inquiry?inquiry_dout:
|
||||
cmd_read_capacity?read_capacity_dout:
|
||||
cmd_mode_sense?mode_sense_dout:
|
||||
8'h00;
|
||||
|
||||
// output of inquiry command, identify as "SEAGATE ST225N"
|
||||
wire [7:0] inquiry_dout =
|
||||
(data_cnt == 32'd4 )?8'd32: // length
|
||||
|
||||
(data_cnt == 32'd8 )?" ":(data_cnt == 32'd9 )?"S":
|
||||
(data_cnt == 32'd10)?"E":(data_cnt == 32'd11)?"A":
|
||||
(data_cnt == 32'd12)?"G":(data_cnt == 32'd13)?"A":
|
||||
(data_cnt == 32'd14)?"T":(data_cnt == 32'd15)?"E":
|
||||
(data_cnt == 32'd16)?" ":(data_cnt == 32'd17)?" ":
|
||||
(data_cnt == 32'd18)?" ":(data_cnt == 32'd19)?" ":
|
||||
(data_cnt == 32'd20)?" ":(data_cnt == 32'd21)?" ":
|
||||
(data_cnt == 32'd22)?" ":(data_cnt == 32'd23)?" ":
|
||||
(data_cnt == 32'd24)?" ":(data_cnt == 32'd25)?" ":
|
||||
|
||||
(data_cnt == 32'd26)?"S":(data_cnt == 32'd27)?"T":
|
||||
(data_cnt == 32'd28)?"2":(data_cnt == 32'd29)?"2":
|
||||
(data_cnt == 32'd30)?"5":(data_cnt == 32'd31)?"N" + ID: // TESTING. ElectronAsh.
|
||||
8'h00;
|
||||
|
||||
// output of read capacity command
|
||||
//wire [31:0] capacity = 32'd41056; // 40960 + 96 blocks = 20MB
|
||||
//wire [31:0] capacity = 32'd1024096; // 1024000 + 96 blocks = 500MB
|
||||
reg [31:0] capacity;
|
||||
always @(posedge clk) begin
|
||||
if (img_mounted) capacity <= img_blocks + 8'd96;
|
||||
end
|
||||
|
||||
wire [31:0] capacity_m1 = capacity - 32'd1;
|
||||
wire [7:0] read_capacity_dout =
|
||||
(data_cnt == 32'd0 )?capacity_m1[31:24]:
|
||||
(data_cnt == 32'd1 )?capacity_m1[23:16]:
|
||||
(data_cnt == 32'd2 )?capacity_m1[15:8]:
|
||||
(data_cnt == 32'd3 )?capacity_m1[7:0]:
|
||||
(data_cnt == 32'd6 )?8'd2: // 512 bytes per sector
|
||||
8'h00;
|
||||
|
||||
wire [7:0] mode_sense_dout =
|
||||
(data_cnt == 32'd3 )?8'd8:
|
||||
(data_cnt == 32'd5 )?capacity[23:16]:
|
||||
(data_cnt == 32'd6 )?capacity[15:8]:
|
||||
(data_cnt == 32'd7 )?capacity[7:0]:
|
||||
(data_cnt == 32'd10 )?8'd2:
|
||||
8'h00;
|
||||
|
||||
// clock data out of buffer to allow for embedded ram
|
||||
reg [7:0] buffer_dout;
|
||||
always @(posedge clk) buffer_dout <= buffer_in[data_cnt];
|
||||
|
||||
// buffer to store incoming commands
|
||||
reg [3:0] cmd_cnt;
|
||||
reg [7:0] cmd [9:0];
|
||||
|
||||
/* ----------------------- request data from/to io controller ----------------------- */
|
||||
|
||||
// base address of current block. Subtract one when writing since the writing happens
|
||||
// after a block has been transferred and data_cnt has thus already been increased by 512
|
||||
assign io_lba = lba + { 9'd0, data_cnt[31:9] } -
|
||||
(cmd_write ? 32'd1 : 32'd0);
|
||||
|
||||
wire req_rd = ((phase == `PHASE_DATA_OUT) && cmd_read && (data_cnt[8:0] == 0) && !data_complete);
|
||||
wire req_wr = ((((phase == `PHASE_DATA_IN) && (data_cnt[8:0] == 0) && (data_cnt != 0)) || (phase == `PHASE_STATUS_OUT)) && cmd_write);
|
||||
always @(posedge clk) begin
|
||||
reg old_rd, old_wr;
|
||||
|
||||
old_rd <= req_rd;
|
||||
old_wr <= req_wr;
|
||||
|
||||
if(io_ack) begin
|
||||
io_rd <= 1'b0;
|
||||
io_wr <= 1'b0;
|
||||
end else begin
|
||||
// generate an io_rd signal whenever the first byte of a 512 byte block is required and io_wr whenever
|
||||
// the last byte of a 512 byte block has been revceived
|
||||
if(~old_rd & req_rd) io_rd <= 1;
|
||||
|
||||
// generate an io_wr signal whenever a 512 byte block has been received or when the status
|
||||
// phase of a write command has been reached
|
||||
if(~old_wr & req_wr) io_wr <= 1;
|
||||
end
|
||||
end
|
||||
|
||||
reg stb_ack;
|
||||
reg stb_adv;
|
||||
always @(posedge clk) begin
|
||||
reg old_ack;
|
||||
|
||||
old_ack <= ack;
|
||||
stb_ack <= (~old_ack & ack);
|
||||
stb_adv <= stb_ack;
|
||||
end
|
||||
|
||||
// store data on rising edge of ack, ...
|
||||
always @(posedge clk) begin
|
||||
if(stb_ack) begin
|
||||
if(phase == `PHASE_CMD_IN) cmd[cmd_cnt] <= din;
|
||||
if(phase == `PHASE_DATA_IN) buffer_out[data_cnt] <= din;
|
||||
end
|
||||
end
|
||||
|
||||
// ... advance counter on falling edge
|
||||
always @(posedge clk) begin
|
||||
if(phase == `PHASE_IDLE) cmd_cnt <= 4'd0;
|
||||
else if(stb_adv && (phase == `PHASE_CMD_IN) && (cmd_cnt != 15)) cmd_cnt <= cmd_cnt + 4'd1;
|
||||
end
|
||||
|
||||
// count data bytes. don't increase counter while we are waiting for data from
|
||||
// the io controller
|
||||
reg [31:0] data_cnt;
|
||||
reg data_complete;
|
||||
|
||||
// For block transfers tlen contains the number of 512 bytes blocks to transfer.
|
||||
// Most other commands have the bytes length stored in the transfer length field.
|
||||
// And some have a fixed length idependent from any header field.
|
||||
// The data transfer has finished once the data counter reaches this
|
||||
// number.
|
||||
wire [31:0] data_len =
|
||||
cmd_read_capacity?32'd8:
|
||||
cmd_read?{ 7'd0, tlen, 9'd0 }: // read command length is in 512 bytes blocks
|
||||
cmd_write?{ 7'd0, tlen, 9'd0 }: // write command length is in 512 bytes blocks
|
||||
{ 16'd0, tlen }; // inquiry etc have length in bytes
|
||||
|
||||
always @(posedge clk) begin
|
||||
if((phase != `PHASE_DATA_OUT) && (phase != `PHASE_DATA_IN) && (phase != `PHASE_STATUS_OUT) && (phase != `PHASE_MESSAGE_OUT)) begin
|
||||
data_cnt <= 0;
|
||||
data_complete <= 0;
|
||||
end else begin
|
||||
if(stb_adv)begin
|
||||
if(!data_complete) data_cnt <= data_cnt + 1'd1;
|
||||
data_complete <= (data_len - 1'd1) == data_cnt;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// check whether status byte has been sent
|
||||
reg status_sent;
|
||||
always @(posedge clk) begin
|
||||
if(phase != `PHASE_STATUS_OUT) status_sent <= 0;
|
||||
else if(stb_adv) status_sent <= 1;
|
||||
end
|
||||
|
||||
// check whether message byte has been sent
|
||||
reg message_sent;
|
||||
always @(posedge clk) begin
|
||||
if(phase != `PHASE_MESSAGE_OUT) message_sent <= 0;
|
||||
else if(stb_adv) message_sent <= 1;
|
||||
end
|
||||
|
||||
/* ----------------------- command decoding ------------------------------- */
|
||||
|
||||
|
||||
// parse commands
|
||||
wire [7:0] op_code = cmd[0];
|
||||
wire [2:0] cmd_group = op_code[7:5];
|
||||
|
||||
// check if a complete command has been received
|
||||
wire cmd_cpl = cmd6_cpl || cmd10_cpl;
|
||||
wire cmd6_cpl = (cmd_group == 3'b000) && (cmd_cnt == 6);
|
||||
wire cmd10_cpl = ((cmd_group == 3'b010) || (cmd_group == 3'b001)) && (cmd_cnt == 10);
|
||||
|
||||
// https://en.wikipedia.org/wiki/SCSI_command
|
||||
wire cmd_read = cmd_read6 || cmd_read10;
|
||||
wire cmd_read6 = (op_code == 8'h08);
|
||||
wire cmd_read10 = (op_code == 8'h28);
|
||||
wire cmd_write = cmd_write6 || cmd_write10;
|
||||
wire cmd_write6 = (op_code == 8'h0a);
|
||||
wire cmd_write10 = (op_code == 8'h2a);
|
||||
wire cmd_inquiry = (op_code == 8'h12);
|
||||
wire cmd_format = (op_code == 8'h04);
|
||||
wire cmd_mode_select = (op_code == 8'h15);
|
||||
wire cmd_mode_sense = (op_code == 8'h1a);
|
||||
wire cmd_test_unit_ready = (op_code == 8'h00);
|
||||
wire cmd_read_capacity = (op_code == 8'h25);
|
||||
|
||||
// valid command in buffer? TODO: check for valid command parameters
|
||||
wire cmd_ok = cmd_read || cmd_write || cmd_inquiry || cmd_test_unit_ready ||
|
||||
cmd_read_capacity || cmd_mode_select || cmd_format || cmd_mode_sense;
|
||||
|
||||
// latch parameters once command is complete
|
||||
reg [31:0] lba;
|
||||
reg [15:0] tlen;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(cmd_cpl && (phase == `PHASE_CMD_IN)) begin
|
||||
lba <= cmd6_cpl?{11'd0, lba6}:lba10;
|
||||
tlen <= cmd6_cpl?{7'd0, tlen6}:tlen10;
|
||||
end
|
||||
end
|
||||
|
||||
// logical block address
|
||||
wire [7:0] cmd1 = cmd[1];
|
||||
wire [20:0] lba6 = { cmd1[4:0], cmd[2], cmd[3] };
|
||||
wire [31:0] lba10 = { cmd[2], cmd[3], cmd[4], cmd[5] };
|
||||
|
||||
// transfer length
|
||||
wire [8:0] tlen6 = (cmd[4] == 0)?9'd256:{1'b0,cmd[4]};
|
||||
wire [15:0] tlen10 = { cmd[7], cmd[8] };
|
||||
|
||||
|
||||
// the 5380 changes phase in the falling edge, thus we monitor it
|
||||
// on the rising edge
|
||||
always @(posedge clk) begin
|
||||
if(rst) begin
|
||||
phase <= `PHASE_IDLE;
|
||||
end else begin
|
||||
if(phase == `PHASE_IDLE) begin
|
||||
if(sel && din[ID]) // own id on bus during selection?
|
||||
phase <= `PHASE_CMD_IN;
|
||||
end
|
||||
|
||||
else if(phase == `PHASE_CMD_IN) begin
|
||||
// check if a full command is in the buffer
|
||||
if(cmd_cpl) begin
|
||||
// is this a supported and valid command?
|
||||
if(cmd_ok) begin
|
||||
// yes, continue
|
||||
status <= `STATUS_OK;
|
||||
|
||||
// continue according to command
|
||||
|
||||
// these commands return data
|
||||
if(cmd_read || cmd_inquiry || cmd_read_capacity || cmd_mode_sense) phase <= `PHASE_DATA_OUT;
|
||||
// these commands receive dataa
|
||||
else if(cmd_write || cmd_mode_select) phase <= `PHASE_DATA_IN;
|
||||
// and all other valid commands are just "ok"
|
||||
else phase <= `PHASE_STATUS_OUT;
|
||||
end else begin
|
||||
// no, report failure
|
||||
status <= `STATUS_CHECK_CONDITION;
|
||||
phase <= `PHASE_STATUS_OUT;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
else if(phase == `PHASE_DATA_OUT) begin
|
||||
if(data_complete) phase <= `PHASE_STATUS_OUT;
|
||||
end
|
||||
|
||||
else if(phase == `PHASE_DATA_IN) begin
|
||||
if(data_complete) phase <= `PHASE_STATUS_OUT;
|
||||
end
|
||||
|
||||
else if(phase == `PHASE_STATUS_OUT) begin
|
||||
if(status_sent) phase <= `PHASE_MESSAGE_OUT;
|
||||
end
|
||||
|
||||
else if(phase == `PHASE_MESSAGE_OUT) begin
|
||||
if(message_sent) phase <= `PHASE_IDLE;
|
||||
end
|
||||
|
||||
else
|
||||
phase <= `PHASE_IDLE; // should never happen
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -22,26 +22,26 @@
|
||||
module sdram (
|
||||
|
||||
// interface to the MT48LC16M16 chip
|
||||
inout [15:0] sd_data, // 16 bit bidirectional data bus
|
||||
output reg [12:0] sd_addr, // 13 bit multiplexed address bus
|
||||
output reg [1:0] sd_dqm, // two byte masks
|
||||
output reg [1:0] sd_ba, // two banks
|
||||
output sd_cs, // a single chip select
|
||||
output sd_we, // write enable
|
||||
output sd_ras, // row address select
|
||||
output sd_cas, // columns address select
|
||||
inout reg [15:0] sd_data, // 16 bit bidirectional data bus
|
||||
output reg [12:0] sd_addr, // 13 bit multiplexed address bus
|
||||
output reg [1:0] sd_dqm, // two byte masks
|
||||
output reg [1:0] sd_ba, // two banks
|
||||
output sd_cs, // a single chip select
|
||||
output sd_we, // write enable
|
||||
output sd_ras, // row address select
|
||||
output sd_cas, // columns address select
|
||||
|
||||
// cpu/chipset interface
|
||||
input init, // init signal after FPGA config to initialize RAM
|
||||
input clk_64, // sdram is accessed at 64MHz
|
||||
input clk_8, // 8MHz chipset clock to which sdram state machine is synchonized
|
||||
|
||||
input [15:0] din, // data input from chipset/cpu
|
||||
output [15:0] dout, // data output to chipset/cpu
|
||||
input [23:0] addr, // 24 bit word address
|
||||
input [1:0] ds, // upper/lower data strobe
|
||||
input oe, // cpu/chipset requests read
|
||||
input we // cpu/chipset requests write
|
||||
input init, // init signal after FPGA config to initialize RAM
|
||||
input clk_64, // sdram is accessed at 64MHz
|
||||
input clk_8, // 8MHz chipset clock to which sdram state machine is synchonized
|
||||
|
||||
input [15:0] din, // data input from chipset/cpu
|
||||
output [15:0] dout, // data output to chipset/cpu
|
||||
input [23:0] addr, // 24 bit word address
|
||||
input [1:0] ds, // upper/lower data strobe
|
||||
input oe, // cpu/chipset requests read
|
||||
input we // cpu/chipset requests write
|
||||
);
|
||||
|
||||
localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 3 cycles@128MHz
|
||||
@@ -113,12 +113,11 @@ assign sd_ras = sd_cmd[2];
|
||||
assign sd_cas = sd_cmd[1];
|
||||
assign sd_we = sd_cmd[0];
|
||||
|
||||
// drive ram data lines when writing, set them as inputs otherwise
|
||||
assign sd_data = we?din:16'bZZZZZZZZZZZZZZZZ;
|
||||
assign dout = sd_data;
|
||||
|
||||
always @(posedge clk_64) begin
|
||||
sd_cmd <= CMD_INHIBIT; // default: idle
|
||||
sd_data <= 16'bZZZZZZZZZZZZZZZZ;
|
||||
|
||||
if(reset != 0) begin
|
||||
// initialization takes place at the end of the reset phase
|
||||
@@ -128,38 +127,42 @@ always @(posedge clk_64) begin
|
||||
sd_cmd <= CMD_PRECHARGE;
|
||||
sd_addr[10] <= 1'b1; // precharge all banks
|
||||
end
|
||||
|
||||
|
||||
if(reset == 2) begin
|
||||
sd_cmd <= CMD_LOAD_MODE;
|
||||
sd_addr <= MODE;
|
||||
end
|
||||
|
||||
|
||||
end
|
||||
end else begin
|
||||
// normal operation
|
||||
|
||||
|
||||
// ------------------- cpu/chipset read/write ----------------------
|
||||
if(we || oe) begin
|
||||
|
||||
|
||||
// RAS phase
|
||||
if(t == STATE_CMD_START) begin
|
||||
sd_cmd <= CMD_ACTIVE;
|
||||
sd_addr <= { 1'b0, addr[19:8] };
|
||||
sd_ba <= addr[21:20];
|
||||
|
||||
|
||||
// always return both bytes in a read. The cpu may not
|
||||
// need it, but the caches need to be able to store everything
|
||||
if(!we) sd_dqm <= 2'b00;
|
||||
else sd_dqm <= ~ds;
|
||||
end
|
||||
|
||||
|
||||
// CAS phase
|
||||
if(t == STATE_CMD_CONT) begin
|
||||
sd_cmd <= we?CMD_WRITE:CMD_READ;
|
||||
if (we) sd_data <= din;
|
||||
sd_addr <= { 4'b0010, addr[22], addr[7:0] }; // auto precharge
|
||||
end
|
||||
|
||||
// Data ready
|
||||
//if (t == STATE_READ && !we) dout <= sd_data;
|
||||
end
|
||||
|
||||
|
||||
// ------------------------ no access --------------------------
|
||||
else begin
|
||||
if(t == STATE_CMD_START)
|
||||
@@ -168,6 +171,4 @@ always @(posedge clk_64) begin
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -1,410 +0,0 @@
|
||||
//
|
||||
// user_io.v
|
||||
//
|
||||
// user_io for the MiST board
|
||||
// http://code.google.com/p/mist-board/
|
||||
//
|
||||
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
|
||||
//
|
||||
// This source file is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published
|
||||
// by the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This source file is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
|
||||
// parameter STRLEN and the actual length of conf_str have to match
|
||||
|
||||
module user_io #(parameter STRLEN=0) (
|
||||
input [(8*STRLEN)-1:0] conf_str,
|
||||
|
||||
input SPI_CLK,
|
||||
input SPI_SS_IO,
|
||||
output reg SPI_MISO,
|
||||
input SPI_MOSI,
|
||||
|
||||
output reg [7:0] joystick_0,
|
||||
output reg [7:0] joystick_1,
|
||||
output reg [15:0] joystick_analog_0,
|
||||
output reg [15:0] joystick_analog_1,
|
||||
output [1:0] buttons,
|
||||
output [1:0] switches,
|
||||
|
||||
output reg [7:0] status,
|
||||
|
||||
// connection to sd card emulation
|
||||
input [31:0] sd_lba,
|
||||
input sd_rd,
|
||||
input sd_wr,
|
||||
output reg sd_ack,
|
||||
input sd_conf,
|
||||
input sd_sdhc,
|
||||
output [7:0] sd_dout, // valid on rising edge of sd_dout_strobe
|
||||
output reg sd_dout_strobe,
|
||||
input [7:0] sd_din,
|
||||
output reg sd_din_strobe,
|
||||
|
||||
|
||||
// ps2 keyboard emulation
|
||||
input ps2_clk, // 12-16khz provided by core
|
||||
output ps2_kbd_clk,
|
||||
output reg ps2_kbd_data,
|
||||
output ps2_mouse_clk,
|
||||
output reg ps2_mouse_data,
|
||||
|
||||
// serial com port
|
||||
input [7:0] serial_data,
|
||||
input serial_strobe
|
||||
);
|
||||
|
||||
reg [6:0] sbuf;
|
||||
reg [7:0] cmd;
|
||||
reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
|
||||
reg [9:0] byte_cnt; // counts bytes
|
||||
reg [5:0] joystick0;
|
||||
reg [5:0] joystick1;
|
||||
reg [3:0] but_sw;
|
||||
reg [2:0] stick_idx;
|
||||
|
||||
assign buttons = but_sw[1:0];
|
||||
assign switches = but_sw[3:2];
|
||||
assign sd_dout = { sbuf, SPI_MOSI};
|
||||
|
||||
// this variant of user_io is for 8 bit cores (type == a4) only
|
||||
wire [7:0] core_type = 8'ha4;
|
||||
|
||||
// command byte read by the io controller
|
||||
wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd };
|
||||
|
||||
// filter spi clock. the 8 bit gate delay is ~2.5ns in total
|
||||
wire [7:0] spi_sck_D = { spi_sck_D[6:0], SPI_CLK } /* synthesis keep */;
|
||||
wire spi_sck = (spi_sck && spi_sck_D != 8'h00) || (!spi_sck && spi_sck_D == 8'hff);
|
||||
|
||||
// drive MISO only when transmitting core id
|
||||
always@(negedge spi_sck or posedge SPI_SS_IO) begin
|
||||
if(SPI_SS_IO == 1) begin
|
||||
SPI_MISO <= 1'bZ;
|
||||
end else begin
|
||||
|
||||
// first byte returned is always core type, further bytes are
|
||||
// command dependent
|
||||
if(byte_cnt == 0) begin
|
||||
SPI_MISO <= core_type[~bit_cnt];
|
||||
|
||||
end else begin
|
||||
// reading serial fifo
|
||||
if(cmd == 8'h1b) begin
|
||||
// send alternating flag byte and data
|
||||
if(byte_cnt[0]) SPI_MISO <= serial_out_status[~bit_cnt];
|
||||
else SPI_MISO <= serial_out_byte[~bit_cnt];
|
||||
end
|
||||
|
||||
// reading config string
|
||||
else if(cmd == 8'h14) begin
|
||||
// returning a byte from string
|
||||
if(byte_cnt < STRLEN + 1)
|
||||
SPI_MISO <= conf_str[{STRLEN - byte_cnt,~bit_cnt}];
|
||||
else
|
||||
SPI_MISO <= 1'b0;
|
||||
end
|
||||
|
||||
// reading sd card status
|
||||
else if(cmd == 8'h16) begin
|
||||
if(byte_cnt == 1)
|
||||
SPI_MISO <= sd_cmd[~bit_cnt];
|
||||
else if((byte_cnt >= 2) && (byte_cnt < 6))
|
||||
SPI_MISO <= sd_lba[{5-byte_cnt, ~bit_cnt}];
|
||||
else
|
||||
SPI_MISO <= 1'b0;
|
||||
end
|
||||
|
||||
// reading sd card write data
|
||||
else if(cmd == 8'h18)
|
||||
SPI_MISO <= sd_din[~bit_cnt];
|
||||
|
||||
else
|
||||
SPI_MISO <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// ---------------- PS2 ---------------------
|
||||
|
||||
// 8 byte fifos to store ps2 bytes
|
||||
localparam PS2_FIFO_BITS = 3;
|
||||
|
||||
// keyboard
|
||||
reg [7:0] ps2_kbd_fifo [(2**PS2_FIFO_BITS)-1:0];
|
||||
reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
|
||||
reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
|
||||
|
||||
// ps2 transmitter state machine
|
||||
reg [3:0] ps2_kbd_tx_state;
|
||||
reg [7:0] ps2_kbd_tx_byte;
|
||||
reg ps2_kbd_parity;
|
||||
|
||||
assign ps2_kbd_clk = ps2_clk || (ps2_kbd_tx_state == 0);
|
||||
|
||||
// ps2 transmitter
|
||||
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
|
||||
reg ps2_kbd_r_inc;
|
||||
always@(posedge ps2_clk) begin
|
||||
ps2_kbd_r_inc <= 1'b0;
|
||||
|
||||
if(ps2_kbd_r_inc)
|
||||
ps2_kbd_rptr <= ps2_kbd_rptr + 1;
|
||||
|
||||
// transmitter is idle?
|
||||
if(ps2_kbd_tx_state == 0) begin
|
||||
// data in fifo present?
|
||||
if(ps2_kbd_wptr != ps2_kbd_rptr) begin
|
||||
// load tx register from fifo
|
||||
ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
|
||||
ps2_kbd_r_inc <= 1'b1;
|
||||
|
||||
// reset parity
|
||||
ps2_kbd_parity <= 1'b1;
|
||||
|
||||
// start transmitter
|
||||
ps2_kbd_tx_state <= 4'd1;
|
||||
|
||||
// put start bit on data line
|
||||
ps2_kbd_data <= 1'b0; // start bit is 0
|
||||
end
|
||||
end else begin
|
||||
|
||||
// transmission of 8 data bits
|
||||
if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
|
||||
ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits
|
||||
ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
|
||||
if(ps2_kbd_tx_byte[0])
|
||||
ps2_kbd_parity <= !ps2_kbd_parity;
|
||||
end
|
||||
|
||||
// transmission of parity
|
||||
if(ps2_kbd_tx_state == 9)
|
||||
ps2_kbd_data <= ps2_kbd_parity;
|
||||
|
||||
// transmission of stop bit
|
||||
if(ps2_kbd_tx_state == 10)
|
||||
ps2_kbd_data <= 1'b1; // stop bit is 1
|
||||
|
||||
// advance state machine
|
||||
if(ps2_kbd_tx_state < 11)
|
||||
ps2_kbd_tx_state <= ps2_kbd_tx_state + 4'd1;
|
||||
else
|
||||
ps2_kbd_tx_state <= 4'd0;
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
// mouse
|
||||
reg [7:0] ps2_mouse_fifo [(2**PS2_FIFO_BITS)-1:0];
|
||||
reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
|
||||
reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
|
||||
|
||||
// ps2 transmitter state machine
|
||||
reg [3:0] ps2_mouse_tx_state;
|
||||
reg [7:0] ps2_mouse_tx_byte;
|
||||
reg ps2_mouse_parity;
|
||||
|
||||
assign ps2_mouse_clk = ps2_clk || (ps2_mouse_tx_state == 0);
|
||||
|
||||
// ps2 transmitter
|
||||
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
|
||||
reg ps2_mouse_r_inc;
|
||||
always@(posedge ps2_clk) begin
|
||||
ps2_mouse_r_inc <= 1'b0;
|
||||
|
||||
if(ps2_mouse_r_inc)
|
||||
ps2_mouse_rptr <= ps2_mouse_rptr + 1;
|
||||
|
||||
// transmitter is idle?
|
||||
if(ps2_mouse_tx_state == 0) begin
|
||||
// data in fifo present?
|
||||
if(ps2_mouse_wptr != ps2_mouse_rptr) begin
|
||||
// load tx register from fifo
|
||||
ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
|
||||
ps2_mouse_r_inc <= 1'b1;
|
||||
|
||||
// reset parity
|
||||
ps2_mouse_parity <= 1'b1;
|
||||
|
||||
// start transmitter
|
||||
ps2_mouse_tx_state <= 4'd1;
|
||||
|
||||
// put start bit on data line
|
||||
ps2_mouse_data <= 1'b0; // start bit is 0
|
||||
end
|
||||
end else begin
|
||||
|
||||
// transmission of 8 data bits
|
||||
if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
|
||||
ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits
|
||||
ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
|
||||
if(ps2_mouse_tx_byte[0])
|
||||
ps2_mouse_parity <= !ps2_mouse_parity;
|
||||
end
|
||||
|
||||
// transmission of parity
|
||||
if(ps2_mouse_tx_state == 9)
|
||||
ps2_mouse_data <= ps2_mouse_parity;
|
||||
|
||||
// transmission of stop bit
|
||||
if(ps2_mouse_tx_state == 10)
|
||||
ps2_mouse_data <= 1'b1; // stop bit is 1
|
||||
|
||||
// advance state machine
|
||||
if(ps2_mouse_tx_state < 11)
|
||||
ps2_mouse_tx_state <= ps2_mouse_tx_state + 4'd1;
|
||||
else
|
||||
ps2_mouse_tx_state <= 4'd0;
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
// fifo to receive serial data from core to be forwarded to io controller
|
||||
|
||||
// 16 byte fifo to store serial bytes
|
||||
localparam SERIAL_OUT_FIFO_BITS = 6;
|
||||
reg [7:0] serial_out_fifo [(2**SERIAL_OUT_FIFO_BITS)-1:0];
|
||||
reg [SERIAL_OUT_FIFO_BITS-1:0] serial_out_wptr;
|
||||
reg [SERIAL_OUT_FIFO_BITS-1:0] serial_out_rptr;
|
||||
|
||||
wire serial_out_data_available = serial_out_wptr != serial_out_rptr;
|
||||
wire [7:0] serial_out_byte = serial_out_fifo[serial_out_rptr] /* synthesis keep */;
|
||||
wire [7:0] serial_out_status = { 7'b1000000, serial_out_data_available};
|
||||
|
||||
// status[0] is reset signal from io controller and is thus used to flush
|
||||
// the fifo
|
||||
always @(posedge serial_strobe or posedge status[0]) begin
|
||||
if(status[0] == 1) begin
|
||||
serial_out_wptr <= 0;
|
||||
end else begin
|
||||
serial_out_fifo[serial_out_wptr] <= serial_data;
|
||||
serial_out_wptr <= serial_out_wptr + 1;
|
||||
end
|
||||
end
|
||||
|
||||
always@(negedge spi_sck or posedge status[0]) begin
|
||||
if(status[0] == 1) begin
|
||||
serial_out_rptr <= 0;
|
||||
end else begin
|
||||
if((byte_cnt != 0) && (cmd == 8'h1b)) begin
|
||||
// read last bit -> advance read pointer
|
||||
if((bit_cnt == 7) && !byte_cnt[0] && serial_out_data_available)
|
||||
serial_out_rptr <= serial_out_rptr + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// SPI receiver
|
||||
always@(posedge spi_sck or posedge SPI_SS_IO) begin
|
||||
|
||||
if(SPI_SS_IO == 1) begin
|
||||
bit_cnt <= 3'd0;
|
||||
byte_cnt <= 10'd0;
|
||||
sd_ack <= 1'b0;
|
||||
sd_dout_strobe <= 1'b0;
|
||||
sd_din_strobe <= 1'b0;
|
||||
end else begin
|
||||
sd_dout_strobe <= 1'b0;
|
||||
sd_din_strobe <= 1'b0;
|
||||
|
||||
if(bit_cnt != 7)
|
||||
sbuf[6:0] <= { sbuf[5:0], SPI_MOSI };
|
||||
|
||||
bit_cnt <= bit_cnt + 3'd1;
|
||||
if((bit_cnt == 7)&&(byte_cnt != 10'd1023))
|
||||
byte_cnt <= byte_cnt + 10'd1;
|
||||
|
||||
// finished reading command byte
|
||||
if(bit_cnt == 7) begin
|
||||
if(byte_cnt == 0) begin
|
||||
cmd <= { sbuf, SPI_MOSI};
|
||||
|
||||
// fetch first byte when sectore FPGA->IO command has been seen
|
||||
if({ sbuf, SPI_MOSI} == 8'h18)
|
||||
sd_din_strobe <= 1'b1;
|
||||
|
||||
if(({ sbuf, SPI_MOSI} == 8'h17) || ({ sbuf, SPI_MOSI} == 8'h18))
|
||||
sd_ack <= 1'b1;
|
||||
|
||||
end else begin
|
||||
|
||||
// buttons and switches
|
||||
if(cmd == 8'h01)
|
||||
but_sw <= { sbuf[2:0], SPI_MOSI };
|
||||
|
||||
if(cmd == 8'h02)
|
||||
joystick_0 <= { sbuf, SPI_MOSI };
|
||||
|
||||
if(cmd == 8'h03)
|
||||
joystick_1 <= { sbuf, SPI_MOSI };
|
||||
|
||||
if(cmd == 8'h04) begin
|
||||
// store incoming ps2 mouse bytes
|
||||
ps2_mouse_fifo[ps2_mouse_wptr] <= { sbuf, SPI_MOSI };
|
||||
ps2_mouse_wptr <= ps2_mouse_wptr + 1;
|
||||
end
|
||||
|
||||
if(cmd == 8'h05) begin
|
||||
// store incoming ps2 keyboard bytes
|
||||
ps2_kbd_fifo[ps2_kbd_wptr] <= { sbuf, SPI_MOSI };
|
||||
ps2_kbd_wptr <= ps2_kbd_wptr + 1;
|
||||
end
|
||||
|
||||
if(cmd == 8'h15)
|
||||
status <= { sbuf[6:0], SPI_MOSI };
|
||||
|
||||
// send sector IO -> FPGA
|
||||
if(cmd == 8'h17) begin
|
||||
// flag that download begins
|
||||
sd_dout_strobe <= 1'b1;
|
||||
end
|
||||
|
||||
// send sector FPGA -> IO
|
||||
if((cmd == 8'h18) && (byte_cnt < 512))
|
||||
sd_din_strobe <= 1'b1;
|
||||
|
||||
// send SD config IO -> FPGA
|
||||
if(cmd == 8'h19) begin
|
||||
// flag that download begins
|
||||
// sd card knows data is config if sd_dout_strobe is asserted
|
||||
// with sd_ack still being inactive (low)
|
||||
sd_dout_strobe <= 1'b1;
|
||||
end
|
||||
|
||||
// joystick analog
|
||||
if(cmd == 8'h1a) begin
|
||||
// first byte is joystick indes
|
||||
if(byte_cnt == 1)
|
||||
stick_idx <= { sbuf[1:0], SPI_MOSI };
|
||||
else if(byte_cnt == 2) begin
|
||||
// second byte is x axis
|
||||
if(stick_idx == 0)
|
||||
joystick_analog_0[15:8] <= { sbuf, SPI_MOSI };
|
||||
else if(stick_idx == 1)
|
||||
joystick_analog_1[15:8] <= { sbuf, SPI_MOSI };
|
||||
end else if(byte_cnt == 3) begin
|
||||
// third byte is y axis
|
||||
if(stick_idx == 0)
|
||||
joystick_analog_0[7:0] <= { sbuf, SPI_MOSI };
|
||||
else if(stick_idx == 1)
|
||||
joystick_analog_1[7:0] <= { sbuf, SPI_MOSI };
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -100,7 +100,9 @@
|
||||
`define INT_T1 6
|
||||
|
||||
module via(
|
||||
input clk8,
|
||||
input clk32,
|
||||
input clk8_en_p,
|
||||
input clk8_en_n,
|
||||
input _reset,
|
||||
input selectVIA,
|
||||
input _cpuRW,
|
||||
@@ -150,10 +152,10 @@ module via(
|
||||
// shift register can be written by CPU and by external source
|
||||
/* Write to SR (including external input) */
|
||||
assign kbd_out_data = viaSR;
|
||||
always @(negedge clk8 or negedge _reset) begin
|
||||
always @(posedge clk32 or negedge _reset) begin
|
||||
if (_reset == 1'b0)
|
||||
viaSR <= 8'b0;
|
||||
else begin
|
||||
else if (clk8_en_n) begin
|
||||
if((selectVIA == 1'b1) && (_cpuUDS == 1'b0) &&
|
||||
(_cpuRW == 1'b0) && (cpuAddrRegHi == 4'hA))
|
||||
viaSR <= dataInHi;
|
||||
@@ -164,10 +166,10 @@ module via(
|
||||
end
|
||||
|
||||
/* Generate sr_out_strobe */
|
||||
always @(negedge clk8 or negedge _reset) begin
|
||||
always @(posedge clk32 or negedge _reset) begin
|
||||
if (_reset == 1'b0)
|
||||
kbd_out_strobe <= 1'b0;
|
||||
else begin
|
||||
else if (clk8_en_n) begin
|
||||
if((selectVIA == 1'b1) && (_cpuUDS == 1'b0) &&
|
||||
(_cpuRW == 1'b0) && (cpuAddrRegHi == 4'hA) &&
|
||||
(viaACR[4:2] == 3'b111))
|
||||
@@ -179,29 +181,33 @@ module via(
|
||||
|
||||
// divide by 10 clock divider for the VIA timers: 0.78336 MHz
|
||||
reg [3:0] clkDiv;
|
||||
always @(posedge clk8) begin
|
||||
if (clkDiv == 4'h9)
|
||||
clkDiv <= 0;
|
||||
else
|
||||
clkDiv <= clkDiv + 1'b1;
|
||||
always @(posedge clk32) begin
|
||||
if (clk8_en_p) begin
|
||||
if (clkDiv == 4'h9)
|
||||
clkDiv <= 0;
|
||||
else
|
||||
clkDiv <= clkDiv + 1'b1;
|
||||
end
|
||||
end
|
||||
wire timerStrobe = (clkDiv == 0);
|
||||
|
||||
// store previous vblank value, for edge detection
|
||||
reg _lastVblank;
|
||||
always @(negedge clk8) begin
|
||||
_lastVblank <= _vblank;
|
||||
always @(posedge clk32) begin
|
||||
if (clk8_en_n) _lastVblank <= _vblank;
|
||||
end
|
||||
|
||||
// count vblanks, and set 1 second interrupt after 60 vblanks
|
||||
reg [5:0] vblankCount;
|
||||
always @(negedge clk8) begin
|
||||
if (_vblank == 1'b0 && _lastVblank == 1'b1) begin
|
||||
if (vblankCount != 59) begin
|
||||
vblankCount <= vblankCount + 1'b1;
|
||||
end
|
||||
else begin
|
||||
vblankCount <= 6'h0;
|
||||
always @(posedge clk32) begin
|
||||
if (clk8_en_n) begin
|
||||
if (_vblank == 1'b0 && _lastVblank == 1'b1) begin
|
||||
if (vblankCount != 59) begin
|
||||
vblankCount <= vblankCount + 1'b1;
|
||||
end
|
||||
else begin
|
||||
vblankCount <= 6'h0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
@@ -209,7 +215,7 @@ module via(
|
||||
|
||||
// register write
|
||||
wire loadT2 = selectVIA == 1'b1 && _cpuUDS == 1'b0 && _cpuRW == 1'b0 && cpuAddrRegHi == 4'h9;
|
||||
always @(negedge clk8 or negedge _reset) begin
|
||||
always @(posedge clk32 or negedge _reset) begin
|
||||
if (_reset == 1'b0) begin
|
||||
viaB0DDR <= 1'b1;
|
||||
viaADataOut <= 8'b01111111;
|
||||
@@ -223,7 +229,7 @@ module via(
|
||||
viaTimer2LatchLow <= 8'h00;
|
||||
viaTimer2Armed <= 0;
|
||||
end
|
||||
else begin
|
||||
else if (clk8_en_n) begin
|
||||
if (selectVIA == 1'b1 && _cpuUDS == 1'b0) begin
|
||||
if (_cpuRW == 1'b0) begin
|
||||
// normal register writes
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
module videoShifter(
|
||||
input clk32,
|
||||
input [1:0] clkPhase,
|
||||
input [15:0] dataIn,
|
||||
input loadPixels,
|
||||
output pixelOut
|
||||
input clk32,
|
||||
input [1:0] clkPhase,
|
||||
input [15:0] dataIn,
|
||||
input loadPixels,
|
||||
output pixelOut
|
||||
);
|
||||
|
||||
reg [15:0] shiftRegister;
|
||||
@@ -22,5 +22,5 @@ module videoShifter(
|
||||
shiftRegister <= { shiftRegister[14:0], 1'b1 };
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -1,13 +1,14 @@
|
||||
// generates 1024x768 (actually 512x768) @ 60Hz, from a 32.5MHz input clock
|
||||
module videoTimer(
|
||||
input clk8,
|
||||
input [1:0] busCycle,
|
||||
output [21:0] videoAddr,
|
||||
output reg hsync,
|
||||
output reg vsync,
|
||||
output _hblank,
|
||||
output _vblank,
|
||||
output loadPixels
|
||||
input clk,
|
||||
input clk_en,
|
||||
input [1:0] busCycle,
|
||||
output [21:0] videoAddr,
|
||||
output reg hsync,
|
||||
output reg vsync,
|
||||
output _hblank,
|
||||
output _vblank,
|
||||
output loadPixels
|
||||
);
|
||||
|
||||
// timing data from http://tinyvga.com/vga-timing/1024x768@60Hz
|
||||
@@ -31,28 +32,34 @@ module videoTimer(
|
||||
|
||||
wire endline = (xpos == kTotalWidth-1);
|
||||
|
||||
always @(posedge clk8) begin
|
||||
if (endline)
|
||||
xpos <= 0;
|
||||
else if (xpos == 0 && busCycle != 0)
|
||||
// hold xpos at 0, until xpos and busCycle are in phase
|
||||
xpos <= 0;
|
||||
else
|
||||
xpos <= xpos + 1'b1;
|
||||
end
|
||||
|
||||
always @(posedge clk8) begin
|
||||
if (endline) begin
|
||||
if (ypos == kTotalHeight-1)
|
||||
ypos <= 0;
|
||||
always @(posedge clk) begin
|
||||
if (clk_en) begin
|
||||
if (endline)
|
||||
xpos <= 0;
|
||||
else if (xpos == 0 && busCycle != 0)
|
||||
// hold xpos at 0, until xpos and busCycle are in phase
|
||||
xpos <= 0;
|
||||
else
|
||||
ypos <= ypos + 1'b1;
|
||||
xpos <= xpos + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk8) begin
|
||||
hsync <= ~(xpos >= kHsyncStart+kPixelLatency && xpos <= kHsyncEnd+kPixelLatency);
|
||||
vsync <= ~(ypos >= kVsyncStart && ypos <= kVsyncEnd);
|
||||
always @(posedge clk) begin
|
||||
if (clk_en) begin
|
||||
if (endline) begin
|
||||
if (ypos == kTotalHeight-1)
|
||||
ypos <= 0;
|
||||
else
|
||||
ypos <= ypos + 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (clk_en) begin
|
||||
hsync <= ~(xpos >= kHsyncStart+kPixelLatency && xpos <= kHsyncEnd+kPixelLatency);
|
||||
vsync <= ~(ypos >= kVsyncStart && ypos <= kVsyncEnd);
|
||||
end
|
||||
end
|
||||
|
||||
assign _hblank = ~(xpos >= kVisibleWidth);
|
||||
|
||||
Reference in New Issue
Block a user