[C64] Change SDRAM clocking

- feed it from PLL's dedicated output - don't invert it
2026-02-06 08:04:41 +00:00 · 2019-03-18 14:41:36 +01:00
parent 24be854cda
commit ba165fefed
6 changed files with 73 additions and 69 deletions
--- a/cores/c64/C64_mist.qsf
+++ b/cores/c64/C64_mist.qsf
@@ -385,4 +385,5 @@ set_global_assignment -name QIP_FILE rtl/mist/rom_reconfig_ntsc.qip
 set_global_assignment -name SIGNALTAP_FILE output_files/pll.stp
 set_location_assignment PIN_46 -to UART_TX
 set_location_assignment PIN_31 -to UART_RX
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_location_assignment PLL_1 -to pll|altpll_component|auto_generated|pll
--- a/cores/c64/C64_mist.sdc
+++ b/cores/c64/C64_mist.sdc
@@ -43,11 +43,14 @@ set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|cl
 set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -min -5 [get_ports {VGA_*}]

 # SDRAM delays
-set_input_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -max 6.4 [get_ports SDRAM_DQ[*]]
-set_input_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -min 3.2 [get_ports SDRAM_DQ[*]]
+set_input_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -max 6.4 [get_ports SDRAM_DQ[*]]
+set_input_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -min 3.2 [get_ports SDRAM_DQ[*]]

-set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
-set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+
+set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.5 [get_ports {SDRAM_CLK}]
+set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -min -0.8 [get_ports {SDRAM_CLK}]

 set_multicycle_path -from {video_mixer:vmixer|scandoubler:scandoubler|Hq2x:Hq2x|*} -to {VGA_*[*]} -setup 4
 set_multicycle_path -from {video_mixer:vmixer|scandoubler:scandoubler|Hq2x:Hq2x|*} -to {VGA_*[*]} -hold 3
--- a/cores/c64/rtl/mist/c64_mist.vhd
+++ b/cores/c64/rtl/mist/c64_mist.vhd
@@ -448,8 +448,8 @@ end component cartridge;
 	signal c64_data_in16: std_logic_vector(15 downto 0);
 	alias  c64_data_out_int   : unsigned is unsigned(c64_data_out);

-	signal c64_clk : std_logic;	-- 31.527mhz (PAL), 32.727mhz(NTSC) clock source
-	signal clk_ram : std_logic; -- 2 x c64_clk
+	signal clk_c64 : std_logic;	-- 31.527mhz (PAL), 32.727mhz(NTSC) clock source
+	signal clk_ram : std_logic; -- 2 x clk_c64
 	signal clk32   : std_logic; -- 32mhz
 	signal ce_8  : std_logic;
 	signal ce_4  : std_logic;
@@ -502,7 +502,7 @@ begin
 	user_io_d : user_io
 	generic map (STRLEN => CONF_STR'length)
 	port map (
-		clk_sys => c64_clk,
+		clk_sys => clk_c64,
 		clk_sd  => clk32,

 		SPI_CLK => SPI_SCK,
@@ -540,7 +540,7 @@ begin

 	data_io_d: data_io
 	port map (
-		clk_sys => c64_clk,
+		clk_sys => clk_c64,
 		SPI_SCK => SPI_SCK,
 		SPI_SS2 => SPI_SS2,
 		SPI_DI => SPI_DI,
@@ -567,7 +567,7 @@ begin
 		mem_ce => not ram_ce,
 		mem_ce_out => mem_ce,

-		clk32 => c64_clk,
+		clk32 => clk_c64,
 		reset => reset_n,
 		reset_out => reset_crt,
 		
@@ -616,9 +616,9 @@ begin
 	sdram_ce <= mem_ce when iec_cycle='0' else ioctl_iec_cycle_used;
 	sdram_we <= not ram_we when iec_cycle='0' else ioctl_iec_cycle_used;

-	process(c64_clk)
+	process(clk_c64)
 	begin
-		if falling_edge(c64_clk) then
+		if falling_edge(clk_c64) then

 			old_download <= ioctl_download;
 			iec_cycleD <= iec_cycle;
@@ -735,9 +735,9 @@ begin
 	c64rom_addr <= ioctl_addr(13 downto 0) when ioctl_index = 0 else '1' & ioctl_addr(12 downto 0);
 	c1541rom_wr <= ioctl_wr when (ioctl_index = 0) and (ioctl_addr(14) = '1') and (ioctl_download = '1') else '0';

-	process(c64_clk)
+	process(clk_c64)
 	begin
-		if rising_edge(c64_clk) then
+		if rising_edge(clk_c64) then
 			clkdiv <= std_logic_vector(unsigned(clkdiv)+1);
 			if(clkdiv(1 downto 0) = "00") then
 				ce_8 <= '1';
@@ -839,8 +839,8 @@ begin
 	pll : entity work.pll_c64
 	port map(
 		inclk0 => CLOCK_27,
-		c0 => c64_clk,
-		c1 => clk_ram,
+		c0 => clk_ram,
+		c1 => clk_c64,
 		areset => pll_areset,
 		scanclk => pll_scanclk,
 		scandata => pll_scandata,
@@ -849,7 +849,7 @@ begin
 		scandataout => pll_scandataout,
 		scandone => pll_scandone
 	);
-	SDRAM_CLK <= not clk_ram;
+	SDRAM_CLK <= clk_ram;

 	-- clock for 1541
 	pll_2 : entity work.pll
@@ -859,9 +859,9 @@ begin
 		locked => pll_locked
 	);

-	process(c64_clk)
+	process(clk_c64)
 	begin
-		if rising_edge(c64_clk) then
+		if rising_edge(clk_c64) then
 			-- Reset by:
 			-- Button at device, IO controller reboot, OSD or FPGA startup
 			if status(0)='1' or pll_locked = '0' then
@@ -916,7 +916,7 @@ begin

 	dac : sigma_delta_dac
 	port map (
-		clk => c64_clk,
+		clk => clk_c64,
 		ldatasum => audio_data_l(17 downto 3),
 		rdatasum => audio_data_r(17 downto 3),
 		aleft => AUDIO_L,
@@ -926,7 +926,7 @@ begin

 	fpga64 : entity work.fpga64_sid_iec
 	port map(
-		clk32 => c64_clk,
+		clk32 => clk_c64,
 		reset_n => reset_n,
 		c64gs => status(11),-- not enough BRAM
 		kbd_clk => not ps2_clk,
@@ -1042,12 +1042,12 @@ begin
 	c1541_iec_data_i <= c64_iec_data_o;
 	c1541_iec_clk_i  <= c64_iec_clk_o;

-	process(c64_clk, reset_n)
+	process(clk_c64, reset_n)
 		variable reset_cnt : integer range 0 to 32000000;
 	begin
 		if reset_n = '0' then
 			reset_cnt := 100000;
-		elsif rising_edge(c64_clk) then
+		elsif rising_edge(clk_c64) then
 			if reset_cnt /= 0 then
 				reset_cnt := reset_cnt - 1;
 			end if;
@@ -1066,7 +1066,7 @@ begin
 		clk32 => clk32,
 		reset => c1541_reset,

-		c1541rom_clk => c64_clk,
+		c1541rom_clk => clk_c64,
 		c1541rom_addr => ioctl_addr(13 downto 0),
 		c1541rom_data => ioctl_data,
 		c1541rom_wr => c1541rom_wr,
@@ -1097,7 +1097,7 @@ begin

 	comp_sync : entity work.composite_sync
 	port map(
-		clk32 => c64_clk,
+		clk32 => clk_c64,
 		hsync => hsync,
 		vsync => vsync,
 		ntsc  => ntsc_init_mode,
@@ -1114,9 +1114,9 @@ begin
 	hq2x <= status(9) xor status(8);
 	ce_pix_actual <= ce_4 when hq2x160='1' else ce_8;
 	
-	process(c64_clk)
+	process(clk_c64)
 	begin
-		if rising_edge(c64_clk) then
+		if rising_edge(clk_c64) then
 			if((old_vsync = '0') and (vsync_out = '1')) then
 				if(status(10 downto 8)="010") then
 					hq2x160 <= '1';
--- a/cores/c64/rtl/mist/pll_c64.vhd
+++ b/cores/c64/rtl/mist/pll_c64.vhd
@@ -165,11 +165,11 @@ BEGIN
 	altpll_component : altpll
 	GENERIC MAP (
 		bandwidth_type => "AUTO",
-		clk0_divide_by => 6,
+		clk0_divide_by => 3,
 		clk0_duty_cycle => 50,
 		clk0_multiply_by => 7,
 		clk0_phase_shift => "0",
-		clk1_divide_by => 3,
+		clk1_divide_by => 6,
 		clk1_duty_cycle => 50,
 		clk1_multiply_by => 7,
 		clk1_phase_shift => "0",
@@ -261,12 +261,12 @@ END SYN;
 -- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
 -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
 -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "6"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "6"
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "31.500000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "63.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "63.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "31.500000"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -294,8 +294,8 @@ END SYN;
 -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "7"
 -- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "7"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "31.52000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "63.04000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "63.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "32.72700000"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
@@ -341,11 +341,11 @@ END SYN;
 -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "6"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3"
 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
 -- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "7"
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "6"
 -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
 -- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "7"
 -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
--- a/cores/c64/rtl/mist/pll_c64_ntsc.mif
+++ b/cores/c64/rtl/mist/pll_c64_ntsc.mif
@@ -17,8 +17,8 @@
 --    Device Part: -
 --    Device Speed Grade: 8
 --    PLL Scan Chain: Fast PLL (144 bits)
--    File Name: /home/gyuri/git/mist-board/cores/c64/rtl/mist/pll_c64_ntsc.mif
--    Generated: Sun Feb 10 18:12:08 2019
+--    File Name: /home/gyurco/git/mist-board/cores/c64/rtl/mist/pll_c64_ntsc.mif
+--    Generated: Mon Mar 18 13:52:51 2019

 WIDTH=1;
 DEPTH=144;
@@ -82,39 +82,39 @@ CONTENT BEGIN
 	52   :   0;
 	53   :   0;
 	54   :   0; -- clk0 counter: Bypass = 0 (1 bit(s))
-	55   :   0; -- clk0 counter: High Count = 8 (8 bit(s))
+	55   :   0; -- clk0 counter: High Count = 4 (8 bit(s))
 	56   :   0;
 	57   :   0;
 	58   :   0;
-	59   :   1;
-	60   :   0;
+	59   :   0;
+	60   :   1;
 	61   :   0;
 	62   :   0;
 	63   :   0; -- clk0 counter: Odd Division = 0 (1 bit(s))
-	64   :   0; -- clk0 counter: Low Count = 8 (8 bit(s))
+	64   :   0; -- clk0 counter: Low Count = 4 (8 bit(s))
 	65   :   0;
 	66   :   0;
 	67   :   0;
-	68   :   1;
-	69   :   0;
+	68   :   0;
+	69   :   1;
 	70   :   0;
 	71   :   0;
 	72   :   0; -- clk1 counter: Bypass = 0 (1 bit(s))
-	73   :   0; -- clk1 counter: High Count = 4 (8 bit(s))
+	73   :   0; -- clk1 counter: High Count = 8 (8 bit(s))
 	74   :   0;
 	75   :   0;
 	76   :   0;
-	77   :   0;
-	78   :   1;
+	77   :   1;
+	78   :   0;
 	79   :   0;
 	80   :   0;
 	81   :   0; -- clk1 counter: Odd Division = 0 (1 bit(s))
-	82   :   0; -- clk1 counter: Low Count = 4 (8 bit(s))
+	82   :   0; -- clk1 counter: Low Count = 8 (8 bit(s))
 	83   :   0;
 	84   :   0;
 	85   :   0;
-	86   :   0;
-	87   :   1;
+	86   :   1;
+	87   :   0;
 	88   :   0;
 	89   :   0;
 	90   :   1; -- clk2 counter: Bypass = 1 (1 bit(s))
--- a/cores/c64/rtl/mist/pll_c64_pal.mif
+++ b/cores/c64/rtl/mist/pll_c64_pal.mif
@@ -17,8 +17,8 @@
 --    Device Part: -
 --    Device Speed Grade: 8
 --    PLL Scan Chain: Fast PLL (144 bits)
--    File Name: /home/gyuri/git/mist-board/cores/c64/rtl/mist/pll_c64_pal.mif
--    Generated: Sun Feb 10 22:52:34 2019
+--    File Name: /home/gyurco/git/mist-board/cores/c64/rtl/mist/pll_c64_pal.mif
+--    Generated: Mon Mar 18 13:55:59 2019

 WIDTH=1;
 DEPTH=144;
@@ -82,41 +82,41 @@ CONTENT BEGIN
 	52   :   1;
 	53   :   0;
 	54   :   0; -- clk0 counter: Bypass = 0 (1 bit(s))
-	55   :   0; -- clk0 counter: High Count = 9 (8 bit(s))
+	55   :   0; -- clk0 counter: High Count = 5 (8 bit(s))
 	56   :   0;
 	57   :   0;
 	58   :   0;
-	59   :   1;
-	60   :   0;
+	59   :   0;
+	60   :   1;
 	61   :   0;
 	62   :   1;
-	63   :   0; -- clk0 counter: Odd Division = 0 (1 bit(s))
-	64   :   0; -- clk0 counter: Low Count = 9 (8 bit(s))
+	63   :   1; -- clk0 counter: Odd Division = 1 (1 bit(s))
+	64   :   0; -- clk0 counter: Low Count = 4 (8 bit(s))
 	65   :   0;
 	66   :   0;
 	67   :   0;
-	68   :   1;
-	69   :   0;
+	68   :   0;
+	69   :   1;
 	70   :   0;
-	71   :   1;
+	71   :   0;
 	72   :   0; -- clk1 counter: Bypass = 0 (1 bit(s))
-	73   :   0; -- clk1 counter: High Count = 5 (8 bit(s))
+	73   :   0; -- clk1 counter: High Count = 9 (8 bit(s))
 	74   :   0;
 	75   :   0;
 	76   :   0;
-	77   :   0;
-	78   :   1;
+	77   :   1;
+	78   :   0;
 	79   :   0;
 	80   :   1;
-	81   :   1; -- clk1 counter: Odd Division = 1 (1 bit(s))
-	82   :   0; -- clk1 counter: Low Count = 4 (8 bit(s))
+	81   :   0; -- clk1 counter: Odd Division = 0 (1 bit(s))
+	82   :   0; -- clk1 counter: Low Count = 9 (8 bit(s))
 	83   :   0;
 	84   :   0;
 	85   :   0;
-	86   :   0;
-	87   :   1;
+	86   :   1;
+	87   :   0;
 	88   :   0;
-	89   :   0;
+	89   :   1;
 	90   :   1; -- clk2 counter: Bypass = 1 (1 bit(s))
 	91   :   0; -- clk2 counter: High Count = 0 (8 bit(s))
 	92   :   0;