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Merge pull request #83 from gyurco/archie

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[Archie] Synchronize reset signals in VIDC
This commit is contained in:
gyurco
2019-02-24 03:19:02 +01:00
committed by GitHub
parent fcde675609 99d8c93590
commit bbb910045e
2 changed files with 13 additions and 5 deletions
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7
cores/archie/rtl/vidc_dmachannel.v
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@@ -93,10 +93,11 @@ vidc_fifo #(.FIFO_SIZE(FIFO_SIZE)) VIDEO_FIFO(
// DMA interface control
// this is in the cpu clock domain.
always @(posedge clkcpu) begin
reg rstD, rstD2;
ak_r <= ak;
if (rst == 1'b1) begin
rstD <= rst;
rstD2 <= rstD;
if (rstD2 == 1'b1) begin
// do reset logic
dma_count <= 2'd0;

11
cores/archie/rtl/vidc_fifo.v
View File

@@ -75,11 +75,14 @@ end
reg [BYTE_WIDTH-1:0] rd_ptr_r;
always @(posedge wr_clk) begin
reg rstD, rstD2;
rd_ptr_r <= rd_ptr;
space <= {rd_ptr_r[BYTE_WIDTH-1:2]} - wr_ptr;
rstD <= rst;
rstD2 <= rstD;
if (rst) begin
if (rstD2) begin
wr_ptr <= 'd0;
full <= 1'b0;
@@ -108,8 +111,12 @@ wire [7:0] q;
always @(posedge rd_clk) begin
reg rstD, rstD2;
rstD <= rst;
rstD2 <= rstD;
if(rd_ce) begin
if (rst) begin
if (rstD2) begin
rd_ptr <= 'd0;
dout <= 8'd0;