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Archie: use 2 deterministic places for requesting new data in VIDC

This commit is contained in:
Gyorgy Szombathelyi
2019-10-22 19:55:27 +02:00
parent ef4be11a52
commit cb13fcef8d

View File

@@ -116,7 +116,7 @@ end
// TODO: use bits 4 and 5 of fifo control register for requesting new data to the video fifo.
// But the RAM timing is so different from the original machine that it won't be useful
assign fifo_can_load = ~stall && ((!FIFO4WORDS && wrusedw <= 4) || (FIFO4WORDS && wrusedw == 0));
assign fifo_can_load = ~stall && ((!FIFO4WORDS && wrusedw == 4) || wrusedw == 0);
assign busy = load;
endmodule