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Code Issues Releases Wiki Activity

[C16] Support for Function ROMs

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This commit is contained in:
Gyorgy Szombathelyi
2019-05-04 23:20:10 +02:00
parent 0a857fd788
commit f3b2572389
2 changed files with 35 additions and 5 deletions
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16
cores/c16/c16.v
View File

@@ -51,6 +51,9 @@ module C16 (
output wire CS0, // Select BASIC ROM (low active)
output wire CS1, // Select Kernal ROM (low active)
output wire [3:0] ROM_SEL, // 3:2 - Kernal, Cartridge1 HIGH, Function HIGH, Cartridge2 HIGH
// 1:0 - BASIC, Cartridge2 LOW, Function LOW, Cartridge2 LOW
output wire [13:0] ROM_ADDR,
input [4:0] JOY0,
@@ -120,6 +123,19 @@ assign kbus[6] = kbus_kbd[6] & joy0_sel[4];
assign kbus[7] = kbus_kbd[7] & joy1_sel[4];
assign ROM_ADDR = c16_addr[13:0];
reg [3:0] rom_sel_reg;
wire kern = c16_addr[15:8] == 8'hFC; // FCXX is always kernal
assign ROM_SEL = { rom_sel_reg[3:2] & { ~kern, ~kern }, rom_sel_reg[1:0] };
always @(posedge CLK28) begin
if (sreset)
rom_sel_reg <= 0;
else begin
// FDD0-FDDF is ROM banking address
if (c16_addr[15:4] == 12'hFDD && ~RW) rom_sel_reg <= c16_addr[3:0];
end
end
// 8501 CPU
mos8501 cpu (
.clk(CLK28),

24
cores/c16/c16_mist.v
View File

@@ -129,13 +129,26 @@ assign SDRAM_CKE = 1'b1;
// ram access signals from c16
wire c16_rom_access = (~c16_basic_sel | ~c16_kernal_sel) && c16_rw;
wire [15:0] c16_sdram_addr = c16_rom_access ? { 1'b0, ~c16_basic_sel, c16_rom_addr } : { c16_a_hi, c16_a_low };
wire [7:0] c16_sdram_data = c16_dout;
wire c16_sdram_wr = !c16_cas && !c16_rw;
wire c16_sdram_oe = (!c16_cas && c16_rw) || c16_rom_access;
wire c16_basic_sel;
wire c16_kernal_sel;
wire [13:0] c16_rom_addr;
wire [3:0] c16_rom_sel;
reg [1:0] c16_rom_sel_mux;
always @(*) begin
casex ({ c16_basic_sel, c16_rom_sel })
'b1_00XX: c16_rom_sel_mux <= 2'b00; // Kernal
'b1_10XX: c16_rom_sel_mux <= 2'b11; // Function HIGH
'b0_XX00: c16_rom_sel_mux <= 2'b01; // BASIC
'b0_XX10: c16_rom_sel_mux <= 2'b10; // Function LOW
default : c16_rom_sel_mux <= 2'b00; // CARTRIDGE - not supported now
endcase
end
wire [15:0] c16_sdram_addr = c16_rom_access ? { c16_rom_sel_mux, c16_rom_addr } : { c16_a_hi, c16_a_low };
wire [7:0] c16_sdram_data = c16_dout;
wire c16_sdram_wr = !c16_cas && !c16_rw;
wire c16_sdram_oe = (!c16_cas && c16_rw) || c16_rom_access;
// ram access signals from io controller
// ioctl_sdram_write
@@ -160,7 +173,7 @@ always @(*) begin
'b0X01: sdram_addr = tap_play_addr[24:1];
'b0X1X: sdram_addr = { 9'd0, sdram_addr_c16ram };
'b10XX: sdram_addr = { 9'd0, sdram_addr_c16ram };
'b11XX: sdram_addr = { 8'd0,1'b1, 1'b0, ~c16_basic_sel, c16_rom_addr[13:1] };
'b11XX: sdram_addr = { 8'd0,1'b1, c16_rom_sel_mux, c16_rom_addr[13:1] };
endcase
end
@@ -665,6 +678,7 @@ C16 #(.INTERNAL_ROM(0)) c16 (
.CS0 ( c16_basic_sel ),
.CS1 ( c16_kernal_sel ),
.ROM_ADDR( c16_rom_addr ),
.ROM_SEL ( c16_rom_sel ),
.JOY0 ( jsB[4:0] ),
.JOY1 ( jsA[4:0] ),