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Merge pull request #68 from gyurco/c64

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C64 moving some files around + disk write protect switch
This commit is contained in:
gyurco
2018-12-14 15:23:58 +01:00
committed by GitHub
parent dca2a6d6c1 b0df597692
commit f5c8dd3e59
15 changed files with 348 additions and 305 deletions
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23
cores/c64/C64_mist.qsf
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@@ -143,7 +143,7 @@ set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
@@ -156,7 +156,7 @@ set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name FITTER_EFFORT "FAST FIT"
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
# Assembler Assignments
# =====================
@@ -320,7 +320,16 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to CONF_DATA0
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VHDL_FILE rtl/c64_mist.vhd
set_global_assignment -name VERILOG_FILE rtl/mist/sigma_delta_dac.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/mist/video_mixer.sv
set_global_assignment -name VERILOG_FILE rtl/mist/user_io.v
set_global_assignment -name VERILOG_FILE rtl/mist/sdram.v
set_global_assignment -name VERILOG_FILE rtl/mist/scandoubler.v
set_global_assignment -name VHDL_FILE rtl/mist/pll.vhd
set_global_assignment -name VERILOG_FILE rtl/mist/osd.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/mist/hq2x.sv
set_global_assignment -name VERILOG_FILE rtl/mist/data_io.v
set_global_assignment -name VHDL_FILE rtl/mist/c64_mist.vhd
set_global_assignment -name VHDL_FILE rtl/fpga64_sid_iec.vhd
set_global_assignment -name VHDL_FILE rtl/video_vicII_656x_e.vhd
set_global_assignment -name VHDL_FILE rtl/video_vicII_656x_a.vhd
@@ -334,15 +343,7 @@ set_global_assignment -name VERILOG_FILE rtl/cartridge.v
set_global_assignment -name VHDL_FILE rtl/rom_c64_chargen.vhd
set_global_assignment -name VHDL_FILE rtl/rom_C64.vhd
set_global_assignment -name VHDL_FILE rtl/rom_GS64.vhd
set_global_assignment -name VERILOG_FILE rtl/sigma_delta_dac.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
set_global_assignment -name VERILOG_FILE rtl/sdram.v
set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
set_global_assignment -name VHDL_FILE rtl/pll.vhd
set_global_assignment -name VERILOG_FILE rtl/osd.v
set_global_assignment -name VERILOG_FILE rtl/mist_io.v
set_global_assignment -name VHDL_FILE rtl/io_ps2_keyboard.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
set_global_assignment -name VHDL_FILE rtl/composite_sync.vhd
set_global_assignment -name VHDL_FILE rtl/sid/wave_map.vhd

3
cores/c64/rtl/c1541/c1541_sd.vhd
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@@ -33,6 +33,7 @@ port(
disk_num : in std_logic_vector(9 downto 0);
disk_change : in std_logic;
disk_readonly : in std_logic;
iec_atn_i : in std_logic;
iec_data_i : in std_logic;
@@ -171,7 +172,7 @@ begin
freq => freq, -- motor frequency
sync_n => sync_n, -- reading SYNC bytes
byte_n => byte_n, -- byte ready
wps_n => '1', -- write-protect sense (0 = protected)
wps_n => not disk_readonly, -- write-protect sense (0 = protected)
tr00_sense_n => '1', -- track 0 sense (unused?)
act => act, -- activity LED

8
cores/c64/rtl/fpga64_sid_iec.vhd
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@@ -581,8 +581,8 @@ div1m: process(clk32) -- this process devides 32 MHz to 1MHz (for the SID)
wdata => std_logic_vector(cpuDo),
rdata => sid_do6581,
potx => pot_x(0),
poty => pot_y(0),
potx => pot_x,
poty => pot_y,
comb_wave_l => '0',
comb_wave_r => '0',
@@ -804,8 +804,8 @@ div1m: process(clk32) -- this process devides 32 MHz to 1MHz (for the SID)
end if;
if rising_edge(clk32) then
if sysCycle = CYCLE_IEC1 then
cia2_pai(7) <= iec_data_i;
cia2_pai(6) <= iec_clk_i;
cia2_pai(7) <= not(iec_data_i or cia2_pao(5));
cia2_pai(6) <= not(iec_clk_i or cia2_pao(4));
end if;
end if;
end process;

115
cores/c64/rtl/c64_mist.vhd → cores/c64/rtl/mist/c64_mist.vhd
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@@ -128,14 +128,14 @@ constant CONF_STR : string :=
"F,CRT,Load Cartridge;" &--3
-- "F,TAP,Load File;"&--4
-- "F,T64,Load File;"&--5
"OE,Disk Write,Enable,Disable;"&
"O2,Video standard,PAL,NTSC;"&
"O8A,Scandoubler Fx,None,HQ2x-320,HQ2x-160,CRT 25%,CRT 50%;"&
"OD,SID,6581,8580;"&
"O3,Joysticks,normal,swapped;"&
"O6,Audio filter,On,Off;"&
-- "OB,BIOS,C64,C64GS;" &
"T5,Reset & Detach Cartridge;"&
"V0,v0.35.00";
"T5,Reset & Detach Cartridge;";
-- convert string to std_logic_vector to be given to user_io
function to_slv(s: string) return std_logic_vector is
@@ -152,29 +152,25 @@ begin
return rval;
end function;
component mist_io generic(STRLEN : integer := 0 ); port
component user_io generic(STRLEN : integer := 0 ); port
(
clk_sys : in std_logic;
clk_sd : in std_logic;
SPI_SCK : in std_logic;
CONF_DATA0 : in std_logic;
SPI_SS2 : in std_logic;
SPI_DI : in std_logic;
SPI_DO : out std_logic;
conf_str : in std_logic_vector(8*STRLEN-1 downto 0);
switches : out std_logic_vector(1 downto 0);
buttons : out std_logic_vector(1 downto 0);
scandoubler_disable : out std_logic;
ypbpr : out std_logic;
joystick_0 : out std_logic_vector(7 downto 0);
joystick_1 : out std_logic_vector(7 downto 0);
clk_sys : in std_logic;
clk_sd : in std_logic;
SPI_CLK, SPI_SS_IO, SPI_MOSI :in std_logic;
SPI_MISO : out std_logic;
conf_str : in std_logic_vector(8*STRLEN-1 downto 0);
joystick_0 : out std_logic_vector(31 downto 0);
joystick_1 : out std_logic_vector(31 downto 0);
joystick_2 : out std_logic_vector(31 downto 0);
joystick_3 : out std_logic_vector(31 downto 0);
joystick_4 : out std_logic_vector(31 downto 0);
joystick_analog_0 : out std_logic_vector(15 downto 0);
joystick_analog_1 : out std_logic_vector(15 downto 0);
status : out std_logic_vector(31 downto 0);
status: out std_logic_vector(31 downto 0);
switches : out std_logic_vector(1 downto 0);
buttons : out std_logic_vector(1 downto 0);
scandoubler_disable : out std_logic;
ypbpr : out std_logic;
sd_lba : in std_logic_vector(31 downto 0);
sd_rd : in std_logic;
@@ -186,16 +182,22 @@ component mist_io generic(STRLEN : integer := 0 ); port
img_mounted : out std_logic;
sd_buff_addr : out std_logic_vector(8 downto 0);
sd_buff_dout : out std_logic_vector(7 downto 0);
sd_buff_din : in std_logic_vector(7 downto 0);
sd_buff_wr : out std_logic;
sd_dout : out std_logic_vector(7 downto 0);
sd_din : in std_logic_vector(7 downto 0);
sd_dout_strobe : out std_logic;
ps2_kbd_clk : out std_logic;
ps2_kbd_data : out std_logic;
ps2_mouse_clk : out std_logic;
ps2_mouse_data : out std_logic;
ps2_mouse_data : out std_logic
);
end component user_io;
component data_io port
(
clk_sys : in std_logic;
SPI_SCK, SPI_SS2, SPI_DI :in std_logic;
ioctl_force_erase : in std_logic;
ioctl_download : out std_logic;
ioctl_erasing : out std_logic;
@@ -204,7 +206,7 @@ component mist_io generic(STRLEN : integer := 0 ); port
ioctl_addr : out std_logic_vector(24 downto 0);
ioctl_dout : out std_logic_vector(7 downto 0)
);
end component mist_io;
end component data_io;
component video_mixer
generic ( LINE_LENGTH : integer := 512; HALF_DEPTH : integer := 0 );
@@ -347,8 +349,8 @@ end component cartridge;
signal c1541rom_wr : std_logic;
signal c64rom_wr : std_logic;
signal joyA : std_logic_vector(7 downto 0);
signal joyB : std_logic_vector(7 downto 0);
signal joyA : std_logic_vector(31 downto 0);
signal joyB : std_logic_vector(31 downto 0);
signal joyA_int : std_logic_vector(6 downto 0);
signal joyB_int : std_logic_vector(6 downto 0);
signal joyA_c64 : std_logic_vector(6 downto 0);
@@ -454,21 +456,20 @@ begin
sd_sdhc <= '1';
-- User io
mist_io_d : mist_io
user_io_d : user_io
generic map (STRLEN => CONF_STR'length)
port map (
clk_sys => clk32,
clk_sd => clk32,
SPI_SCK => SPI_SCK,
CONF_DATA0 => CONF_DATA0,
SPI_SS2 => SPI_SS2,
SPI_DO => SPI_DO,
SPI_DI => SPI_DI,
SPI_CLK => SPI_SCK,
SPI_SS_IO => CONF_DATA0,
SPI_MISO => SPI_DO,
SPI_MOSI => SPI_DI,
joystick_0 => joyA,
joystick_1 => joyB,
conf_str => to_slv(CONF_STR),
status => status,
@@ -484,12 +485,21 @@ begin
sd_conf => sd_conf,
sd_sdhc => sd_sdhc,
sd_buff_addr => sd_buff_addr,
sd_buff_dout => sd_buff_dout,
sd_buff_din => sd_buff_din,
sd_buff_wr => sd_buff_wr,
sd_dout => sd_buff_dout,
sd_din => sd_buff_din,
sd_dout_strobe => sd_buff_wr,
img_mounted => sd_change,
ps2_kbd_clk => ps2_clk,
ps2_kbd_data => ps2_dat,
ps2_kbd_data => ps2_dat
);
data_io_d: data_io
port map (
clk_sys => clk32,
SPI_SCK => SPI_SCK,
SPI_SS2 => SPI_SS2,
SPI_DI => SPI_DI,
ioctl_download => ioctl_download,
ioctl_force_erase => ioctl_force_erase,
ioctl_erasing => ioctl_erasing,
@@ -497,8 +507,7 @@ begin
ioctl_wr => ioctl_wr,
ioctl_addr => ioctl_addr,
ioctl_dout => ioctl_data
);
);
cart_loading <= '1' when ioctl_download = '1' and ioctl_index = 3 else '0';
@@ -820,8 +829,8 @@ begin
iec_data_o => c64_iec_data_o,
iec_atn_o => c64_iec_atn_o,
iec_clk_o => c64_iec_clk_o,
iec_data_i => not c64_iec_data_i,
iec_clk_i => not c64_iec_clk_i,
iec_data_i => c64_iec_data_i,
iec_clk_i => c64_iec_clk_i,
-- iec_atn_i => not c64_iec_atn_i,
disk_num => open,
c64rom_addr => ioctl_addr(13 downto 0),
@@ -831,14 +840,14 @@ begin
reset_key => reset_key
);
disk_readonly <= status(14);
c64_iec_atn_i <= not ((not c64_iec_atn_o) and (not c1541_iec_atn_o) );
c64_iec_data_i <= not ((not c64_iec_data_o) and (not c1541_iec_data_o));
c64_iec_clk_i <= not ((not c64_iec_clk_o) and (not c1541_iec_clk_o) );
c64_iec_data_i <= c1541_iec_data_o;
c64_iec_clk_i <= c1541_iec_clk_o;
c1541_iec_atn_i <= c64_iec_atn_i;
c1541_iec_data_i <= c64_iec_data_i;
c1541_iec_clk_i <= c64_iec_clk_i;
c1541_iec_atn_i <= c64_iec_atn_o;
c1541_iec_data_i <= c64_iec_data_o;
c1541_iec_clk_i <= c64_iec_clk_o;
process(clk32, reset_n)
variable reset_cnt : integer range 0 to 32000000;
@@ -858,7 +867,7 @@ begin
end if;
end process;
c1541_sd : entity work.c1541_sd
c1541_sd_inst : entity work.c1541_sd
port map
(
clk32 => clk32,
@@ -871,13 +880,13 @@ begin
disk_change => sd_change,
disk_num => (others => '0'), -- always 0 on MiST, the image is selected by the OSD menu
-- disk_readonly => disk_readonly,
disk_readonly => disk_readonly,
iec_atn_i => c1541_iec_atn_i,
iec_data_i => c1541_iec_data_i,
iec_clk_i => c1541_iec_clk_i,
iec_atn_o => c1541_iec_atn_o,
--iec_atn_o => c1541_iec_atn_o,
iec_data_o => c1541_iec_data_o,
iec_clk_o => c1541_iec_clk_o,

148
cores/c64/rtl/mist/data_io.v Normal file
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@@ -0,0 +1,148 @@
//
// data_io.v
//
// data_io for the MiST board
// http://code.google.com/p/mist-board/
//
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
///////////////////////////////////////////////////////////////////////
module data_io
(
input clk_sys,
// Global SPI clock from ARM. 24MHz
input SPI_SCK,
input SPI_SS2,
input SPI_DI,
// ARM -> FPGA download
input ioctl_force_erase,
output reg ioctl_download = 0, // signal indicating an active download
output reg ioctl_erasing = 0, // signal indicating an active erase
output reg [7:0] ioctl_index, // menu index used to upload the file
output reg ioctl_wr = 0,
output reg [24:0] ioctl_addr,
output reg [7:0] ioctl_dout
);
/////////////////////////////// DOWNLOADING ///////////////////////////////
reg [7:0] data_w;
reg [24:0] addr_w;
reg rclk = 0;
localparam UIO_FILE_TX = 8'h53;
localparam UIO_FILE_TX_DAT = 8'h54;
localparam UIO_FILE_INDEX = 8'h55;
// data_io has its own SPI interface to the io controller
always@(posedge SPI_SCK, posedge SPI_SS2) begin
reg [6:0] sbuf;
reg [7:0] cmd;
reg [4:0] cnt;
reg [24:0] addr;
if(SPI_SS2) cnt <= 0;
else begin
rclk <= 0;
// don't shift in last bit. It is evaluated directly
// when writing to ram
if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
// increase target address after write
if(rclk) addr <= addr + 1'd1;
// count 0-7 8-15 8-15 ...
if(cnt < 15) cnt <= cnt + 1'd1;
else cnt <= 8;
// finished command byte
if(cnt == 7) cmd <= {sbuf, SPI_DI};
// prepare/end transmission
if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
// prepare
if(SPI_DI) begin
addr <= 0;
ioctl_download <= 1;
end else begin
addr_w <= addr;
ioctl_download <= 0;
end
end
// command 0x54: UIO_FILE_TX
if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
addr_w <= addr;
data_w <= {sbuf, SPI_DI};
rclk <= 1;
end
// expose file (menu) index
if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
end
end
reg [24:0] erase_mask;
wire [24:0] next_erase = (ioctl_addr + 1'd1) & erase_mask;
always@(posedge clk_sys) begin
reg rclkD, rclkD2;
reg old_force = 0;
reg [6:0] erase_clk_div;
reg [24:0] end_addr;
rclkD <= rclk;
rclkD2 <= rclkD;
ioctl_wr <= 0;
if(rclkD & ~rclkD2) begin
ioctl_dout <= data_w;
ioctl_addr <= addr_w;
ioctl_wr <= 1;
end
if(ioctl_download) begin
old_force <= 0;
ioctl_erasing <= 0;
end else begin
old_force <= ioctl_force_erase;
if(ioctl_force_erase & ~old_force) begin
ioctl_addr <= 'h1FFFF;
erase_mask <= 'h1FFFF;
end_addr <= 'h10002;
erase_clk_div <= 1;
ioctl_erasing <= 1;
end else if(ioctl_erasing) begin
erase_clk_div <= erase_clk_div + 1'd1;
if(!erase_clk_div) begin
if(next_erase == end_addr) ioctl_erasing <= 0;
else begin
ioctl_addr <= next_erase;
ioctl_dout <= 0;
ioctl_wr <= 1;
end
end
end
end
end
endmodule

0
cores/c64/rtl/hq2x.sv → cores/c64/rtl/mist/hq2x.sv
View File

0
cores/c64/rtl/osd.v → cores/c64/rtl/mist/osd.v
View File

0
cores/c64/rtl/pll.vhd → cores/c64/rtl/mist/pll.vhd
View File

0
cores/c64/rtl/scandoubler.v → cores/c64/rtl/mist/scandoubler.v
View File

0
cores/c64/rtl/sdram.v → cores/c64/rtl/mist/sdram.v
View File

0
cores/c64/rtl/sigma_delta_dac.v → cores/c64/rtl/mist/sigma_delta_dac.v
View File

331
cores/c64/rtl/mist_io.v → cores/c64/rtl/mist/user_io.v
View File

@@ -1,7 +1,7 @@
//
// mist_io.v
// user_io.v
//
// mist_io for the MiST board
// user_io for the MiST board
// http://code.google.com/p/mist-board/
//
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
@@ -19,90 +19,67 @@
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
///////////////////////////////////////////////////////////////////////
//
// Use buffer to access SD card. It's time-critical part.
// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
// (Sorgelig)
//
// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
// clk_ps2 = clk_sys/(PS2DIV*2)
//
module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
(
// parameter STRLEN and the actual length of conf_str have to match
// parameter STRLEN and the actual length of conf_str have to match
module user_io #(parameter STRLEN=0, parameter PS2DIV=100) (
input [(8*STRLEN)-1:0] conf_str,
// Global clock. It should be around 100MHz (higher is better).
input clk_sys,
input clk_sd,
input clk_sys, // clock for system-related messages (kbd, joy, etc...)
input clk_sd, // clock for SD-card related messages
// Global SPI clock from ARM. 24MHz
input SPI_SCK,
input SPI_CLK,
input SPI_SS_IO,
output reg SPI_MISO,
input SPI_MOSI,
input CONF_DATA0,
input SPI_SS2,
output SPI_DO,
input SPI_DI,
output reg [31:0] joystick_0,
output reg [31:0] joystick_1,
output reg [31:0] joystick_2,
output reg [31:0] joystick_3,
output reg [31:0] joystick_4,
output reg [15:0] joystick_analog_0,
output reg [15:0] joystick_analog_1,
output [1:0] buttons,
output [1:0] switches,
output scandoubler_disable,
output ypbpr,
output reg [31:0] status,
output reg [7:0] joystick_0,
output reg [7:0] joystick_1,
output reg [15:0] joystick_analog_0,
output reg [15:0] joystick_analog_1,
output [1:0] buttons,
output [1:0] switches,
output scandoubler_disable,
output ypbpr,
// connection to sd card emulation
input [31:0] sd_lba,
input sd_rd,
input sd_wr,
output reg sd_ack,
output reg sd_ack_conf,
input sd_conf,
input sd_sdhc,
output reg [7:0] sd_dout, // valid on rising edge of sd_dout_strobe
output reg sd_dout_strobe,
input [7:0] sd_din,
output reg sd_din_strobe,
output reg [8:0] sd_buff_addr,
output reg [31:0] status,
// SD config
input sd_conf,
input sd_sdhc,
output reg img_mounted, // signaling that new image has been mounted
output reg [31:0] img_size, // size of image in bytes
// SD block level access
input [31:0] sd_lba,
input sd_rd,
input sd_wr,
output reg sd_ack,
output reg sd_ack_conf,
// SD byte level access. Signals for 2-PORT altsyncram.
output reg [8:0] sd_buff_addr,
output reg [7:0] sd_buff_dout,
input [7:0] sd_buff_din,
output sd_buff_wr,
output reg img_mounted, //rising edge if a new image is mounted
output reg [31:0] img_size, // size of image in bytes
// ps2 keyboard emulation
output ps2_kbd_clk,
output reg ps2_kbd_data,
output ps2_mouse_clk,
output reg ps2_mouse_data,
input ps2_caps_led,
output ps2_kbd_clk,
output reg ps2_kbd_data,
output ps2_mouse_clk,
output reg ps2_mouse_data,
// ARM -> FPGA download
input ioctl_force_erase,
output reg ioctl_download = 0, // signal indicating an active download
output reg ioctl_erasing = 0, // signal indicating an active erase
output reg [7:0] ioctl_index, // menu index used to upload the file
output reg ioctl_wr = 0,
output reg [24:0] ioctl_addr,
output reg [7:0] ioctl_dout
// serial com port
input [7:0] serial_data,
input serial_strobe
);
reg [6:0] sbuf;
reg [7:0] cmd;
reg [6:0] sbuf;
reg [7:0] cmd;
reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
reg [7:0] byte_cnt; // counts bytes
reg [5:0] joystick0;
reg [5:0] joystick1;
reg [9:0] byte_cnt; // counts bytes
reg [7:0] but_sw;
reg [2:0] stick_idx;
reg [2:0] stick_idx;
assign buttons = but_sw[1:0];
assign switches = but_sw[3:2];
@@ -115,24 +92,20 @@ wire [7:0] core_type = 8'ha4;
// command byte read by the io controller
wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd };
wire spi_sck = SPI_SCK;
reg spi_do;
assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
wire spi_sck = SPI_CLK;
// ---------------- PS2 ---------------------
// 8 byte fifos to store ps2 bytes
localparam PS2_FIFO_BITS = 3;
reg ps2_clk;
always @(negedge clk_sys) begin
integer cnt;
cnt <= cnt + 1'd1;
if(cnt == PS2DIV) begin
ps2_clk <= ~ps2_clk;
cnt <= 0;
end
integer cnt;
cnt <= cnt + 1'd1;
if(cnt == PS2DIV) begin
ps2_clk <= ~ps2_clk;
cnt <= 0;
end
end
// keyboard
@@ -284,7 +257,7 @@ reg [SERIAL_OUT_FIFO_BITS-1:0] serial_out_rptr;
wire serial_out_data_available = serial_out_wptr != serial_out_rptr;
wire [7:0] serial_out_byte = serial_out_fifo[serial_out_rptr] /* synthesis keep */;
wire [7:0] serial_out_status = { 7'b1000000, serial_out_data_available};
/*
// status[0] is reset signal from io controller and is thus used to flush
// the fifo
always @(posedge serial_strobe or posedge status[0]) begin
@@ -307,15 +280,15 @@ always@(negedge spi_sck or posedge status[0]) begin
end
end
end
*/
// SPI bit and byte counters
always@(posedge spi_sck or posedge CONF_DATA0) begin
if(CONF_DATA0 == 1) begin
always@(posedge spi_sck or posedge SPI_SS_IO) begin
if(SPI_SS_IO == 1) begin
bit_cnt <= 0;
byte_cnt <= 0;
byte_cnt <= 0;
end else begin
if((bit_cnt == 7)&&(byte_cnt != 8'd255))
if((bit_cnt == 7)&&(~&byte_cnt))
byte_cnt <= byte_cnt + 8'd1;
bit_cnt <= bit_cnt + 1'd1;
@@ -325,38 +298,42 @@ end
// SPI transmitter FPGA -> IO
reg [7:0] spi_byte_out;
always@(negedge spi_sck or posedge CONF_DATA0) begin
spi_do <= spi_byte_out[~bit_cnt];
always@(negedge spi_sck or posedge SPI_SS_IO) begin
if(SPI_SS_IO == 1) begin
SPI_MISO <= 1'bZ;
end else begin
SPI_MISO <= spi_byte_out[~bit_cnt];
end
end
always@(posedge spi_sck or posedge CONF_DATA0) begin
always@(posedge spi_sck or posedge SPI_SS_IO) begin
reg [31:0] sd_lba_r;
if(CONF_DATA0 == 1) begin
if(SPI_SS_IO == 1) begin
spi_byte_out <= core_type;
end else begin
// read the command byte to choose the response
if(bit_cnt == 7) begin
if(!byte_cnt) cmd <= {sbuf, SPI_DI};
if(!byte_cnt) cmd <= {sbuf, SPI_MOSI};
spi_byte_out <= 0;
case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd})
// reading config string
8'h14: if(byte_cnt < STRLEN) spi_byte_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
spi_byte_out <= 0;
case({(!byte_cnt) ? {sbuf, SPI_MOSI} : cmd})
// reading config string
8'h14: if(byte_cnt < STRLEN) spi_byte_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
// reading sd card status
8'h16: if(byte_cnt == 0) begin
// reading sd card status
8'h16: if(byte_cnt == 0) begin
spi_byte_out <= sd_cmd;
sd_lba_r <= sd_lba;
end
else if(byte_cnt < 5) spi_byte_out <= sd_lba_r[(4-byte_cnt)<<3 +:8];
end
else if(byte_cnt < 5) spi_byte_out <= sd_lba_r[(4-byte_cnt)<<3 +:8];
// reading sd card write data
8'h18: spi_byte_out <= sd_buff_din;
8'h1b:
// send alternating flag byte and data
if(byte_cnt[0]) spi_byte_out <= serial_out_status;
else spi_byte_out <= serial_out_byte;
// reading sd card write data
8'h18: spi_byte_out <= sd_din;
8'h1b:
// send alternating flag byte and data
if(byte_cnt[0]) spi_byte_out <= serial_out_status;
else spi_byte_out <= serial_out_byte;
endcase
end
end
@@ -369,21 +346,21 @@ reg spi_transfer_end_r;
reg [7:0] spi_byte_in_r;
// Read at spi_sck clock domain, assemble bytes for transferring to clk_sys
always@(posedge spi_sck or posedge CONF_DATA0) begin
always@(posedge spi_sck or posedge SPI_SS_IO) begin
if(CONF_DATA0 == 1) begin
if(SPI_SS_IO == 1) begin
spi_receiver_strobe_r <= 0;
spi_transfer_end_r <= 1;
end else begin
spi_receiver_strobe_r <= 0;
if (bit_cnt) spi_receiver_strobe_r <= 0;
spi_transfer_end_r <= 0;
if(bit_cnt != 7)
sbuf[6:0] <= { sbuf[5:0], SPI_DI };
sbuf[6:0] <= { sbuf[5:0], SPI_MOSI };
// finished reading a byte, prepare to transfer to clk_sys
if(bit_cnt == 7) begin
spi_byte_in_r <= { sbuf, SPI_DI};
if(bit_cnt == 7) begin
spi_byte_in_r <= { sbuf, SPI_MOSI};
spi_receiver_strobe_r <= 1;
end
end
@@ -422,8 +399,11 @@ always @(posedge clk_sys) begin
case(acmd)
// buttons and switches
8'h01: but_sw <= spi_byte_in;
8'h02: joystick_0 <= spi_byte_in;
8'h03: joystick_1 <= spi_byte_in;
8'h60: if (abyte_cnt < 6) joystick_0[(abyte_cnt-2)<<3 +:8] <= spi_byte_in;
8'h61: if (abyte_cnt < 6) joystick_1[(abyte_cnt-2)<<3 +:8] <= spi_byte_in;
8'h62: if (abyte_cnt < 6) joystick_2[(abyte_cnt-2)<<3 +:8] <= spi_byte_in;
8'h63: if (abyte_cnt < 6) joystick_3[(abyte_cnt-2)<<3 +:8] <= spi_byte_in;
8'h64: if (abyte_cnt < 6) joystick_4[(abyte_cnt-2)<<3 +:8] <= spi_byte_in;
8'h04: begin
// store incoming ps2 mouse bytes
ps2_mouse_fifo[ps2_mouse_wptr] <= spi_byte_in;
@@ -465,10 +445,6 @@ always @(posedge clk_sys) begin
end
end
reg sd_din_strobe;
reg sd_dout_strobe;
assign sd_buff_wr = sd_dout_strobe;
// Process SD-card related bytes from SPI at the clk_sd domain
always @(posedge clk_sd) begin
@@ -530,7 +506,7 @@ always @(posedge clk_sd) begin
8'h17: begin
// flag that download begins
sd_dout_strobe <= 1'b1;
sd_buff_dout <= spi_byte_in;
sd_dout <= spi_byte_in;
end
// send sector FPGA -> IO
@@ -541,121 +517,16 @@ always @(posedge clk_sd) begin
// flag that download begins
sd_dout_strobe <= 1'b1;
sd_ack_conf <= 1'b1;
sd_buff_dout <= spi_byte_in;
sd_dout <= spi_byte_in;
end
8'h1c: img_mounted <= 1;
// send image info
8'h1d: if(abyte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_byte_in;
8'h1d: if(abyte_cnt<6) img_size[(abyte_cnt-2)<<3 +:8] <= spi_byte_in;
endcase
end
end
end
/////////////////////////////// DOWNLOADING ///////////////////////////////
reg [7:0] data_w;
reg [24:0] addr_w;
reg rclk = 0;
localparam UIO_FILE_TX = 8'h53;
localparam UIO_FILE_TX_DAT = 8'h54;
localparam UIO_FILE_INDEX = 8'h55;
// data_io has its own SPI interface to the io controller
always@(posedge SPI_SCK, posedge SPI_SS2) begin
reg [6:0] sbuf;
reg [7:0] cmd;
reg [4:0] cnt;
reg [24:0] addr;
if(SPI_SS2) cnt <= 0;
else begin
rclk <= 0;
// don't shift in last bit. It is evaluated directly
// when writing to ram
if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
// increase target address after write
if(rclk) addr <= addr + 1'd1;
// count 0-7 8-15 8-15 ...
if(cnt < 15) cnt <= cnt + 1'd1;
else cnt <= 8;
// finished command byte
if(cnt == 7) cmd <= {sbuf, SPI_DI};
// prepare/end transmission
if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
// prepare
if(SPI_DI) begin
addr <= 0;
ioctl_download <= 1;
end else begin
addr_w <= addr;
ioctl_download <= 0;
end
end
// command 0x54: UIO_FILE_TX
if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
addr_w <= addr;
data_w <= {sbuf, SPI_DI};
rclk <= 1;
end
// expose file (menu) index
if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
end
end
reg [24:0] erase_mask;
wire [24:0] next_erase = (ioctl_addr + 1'd1) & erase_mask;
always@(posedge clk_sys) begin
reg rclkD, rclkD2;
reg old_force = 0;
reg [6:0] erase_clk_div;
reg [24:0] end_addr;
rclkD <= rclk;
rclkD2 <= rclkD;
ioctl_wr <= 0;
if(rclkD & ~rclkD2) begin
ioctl_dout <= data_w;
ioctl_addr <= addr_w;
ioctl_wr <= 1;
end
if(ioctl_download) begin
old_force <= 0;
ioctl_erasing <= 0;
end else begin
old_force <= ioctl_force_erase;
if(ioctl_force_erase & ~old_force) begin
ioctl_addr <= 'h1FFFF;
erase_mask <= 'h1FFFF;
end_addr <= 'h10002;
erase_clk_div <= 1;
ioctl_erasing <= 1;
end else if(ioctl_erasing) begin
erase_clk_div <= erase_clk_div + 1'd1;
if(!erase_clk_div) begin
if(next_erase == end_addr) ioctl_erasing <= 0;
else begin
ioctl_addr <= next_erase;
ioctl_dout <= 0;
ioctl_wr <= 1;
end
end
end
end
end
endmodule
endmodule

0
cores/c64/rtl/video_mixer.sv → cores/c64/rtl/mist/video_mixer.sv
View File

19
cores/c64/rtl/sid/sid_regs.vhd
View File

@@ -23,8 +23,11 @@ port (
wren : in std_logic;
wdata : in std_logic_vector(7 downto 0);
rdata : out std_logic_vector(7 downto 0);
potx : in std_logic;
poty : in std_logic;---
potx : in std_logic_vector(7 downto 0);
poty : in std_logic_vector(7 downto 0);
---
comb_wave_l : in std_logic;
comb_wave_r : in std_logic;
---
@@ -202,14 +205,22 @@ begin
-- Readback (unmapped address)
case addr is
when "00011001" => rdata <= potx & potx & potx & potx & potx & potx & potx & potx;
when "00011010" => rdata <= poty & poty & poty & poty & poty & poty & poty & poty;
when "00011001" => rdata <= potx;
when "00011010" => rdata <= poty;
when "00011011" => rdata <= osc3;
when "00011100" => rdata <= env3;
when others => rdata <= (others => '0');
end case;
if reset='1' then
freq_lo <= (others => (others => '0'));
freq_hi <= (others => (others => '0'));
phase_lo <= (others => (others => '0'));
phase_hi <= (others => (others => '0'));
control <= (others => (others => '0'));
att_dec <= (others => (others => '0'));
sust_rel <= (others => (others => '0'));
filt_en_i <= (others => '0');
voice3_off_l <= '0';
voice3_off_r <= '0';

6
cores/c64/rtl/sid/sid_top.vhd
View File

@@ -28,8 +28,9 @@ port (
wren : in std_logic;
wdata : in std_logic_vector(7 downto 0);
rdata : out std_logic_vector(7 downto 0);
potx : in std_logic;
poty : in std_logic;
potx : in std_logic_vector(7 downto 0);
poty : in std_logic_vector(7 downto 0);
comb_wave_l : in std_logic := '0';
comb_wave_r : in std_logic := '0';
@@ -132,6 +133,7 @@ begin
wren => wren,
wdata => wdata,
rdata => rdata,
potx => potx,
poty => poty,