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esa11: fpga.c fix -> leave SPI lines in useable state for user_io.c

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and for xilinx load default bitstream X7A102T.BIN
This commit is contained in:
Emard
2016-10-18 01:53:16 +02:00
parent 1a43601f56
commit 9a71dfd28f
1 changed files with 3 additions and 3 deletions
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6
fpga.c
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@@ -155,7 +155,7 @@ RAMFUNC unsigned char ConfigureFpga(char *name)
if(!name)
// name = "CORE BIN";
name = "XESM38 BIN";
name = "X7A102T BIN";
// open bitstream file
if (FileOpen(&file, name) == 0)
@@ -209,8 +209,8 @@ RAMFUNC unsigned char ConfigureFpga(char *name)
}
while (t < n);
// disable outputs
*AT91C_PIOA_ODR = XILINX_CCLK | XILINX_DIN | XILINX_PROG_B;
// return outputs to a state suitable for user_io.c
*AT91C_PIOA_SODR = XILINX_CCLK | XILINX_DIN | XILINX_PROG_B;
iprintf("]\r");
iprintf("FPGA bitstream loaded\r");