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Reverse polarity of bufreg_hold signal
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75ee4954d0
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116e370589
@ -42,7 +42,7 @@ module serv_state
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output wire [1:0] o_mem_bytecnt,
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input wire i_mem_misalign,
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output reg o_cnt_done,
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output wire o_bufreg_hold);
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output wire o_bufreg_en);
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wire cnt4;
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@ -96,7 +96,7 @@ module serv_state
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assign o_rf_rd_en = i_rd_op & o_cnt_en & !o_init;
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//Shift operations require bufreg to hold for one cycle between INIT and RUN before shifting
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assign o_bufreg_hold = !o_cnt_en & (stage_two_req | ~i_shift_op);
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assign o_bufreg_en = o_cnt_en | (!stage_two_req & i_shift_op);
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initial if (RESET_STRATEGY == "NONE") o_cnt_r = 4'b0001;
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@ -102,7 +102,7 @@ module serv_top
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wire cnt_done;
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wire bufreg_hold;
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wire bufreg_en;
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wire bufreg_rs1_en;
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wire bufreg_imm_en;
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wire bufreg_loop;
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@ -176,7 +176,7 @@ module serv_top
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.o_cnt3 (cnt3),
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.o_cnt7 (cnt7),
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.o_cnt_done (cnt_done),
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.o_bufreg_hold (bufreg_hold),
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.o_bufreg_en (bufreg_en),
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.o_ctrl_pc_en (ctrl_pc_en),
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.o_ctrl_jump (jump),
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.o_ctrl_trap (trap),
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@ -281,7 +281,7 @@ module serv_top
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//State
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.i_cnt0 (cnt0),
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.i_cnt1 (cnt1),
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.i_en (!bufreg_hold),
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.i_en (bufreg_en),
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.i_init (init),
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.o_lsb (lsb),
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//Control
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