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Compliance update
Updated serv to support latest version of riscv-arch-test (v2.6.1)
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README.md
14
README.md
@ -76,23 +76,25 @@ Other applications can be tested by compiling and converting to bin and then hex
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## Run RISC-V compliance tests
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**Note:** The following instructions are valid for version 1.0 of the RISC-V compliance tests. The target-specific support for SERV has not yet been ported to newer versions.
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Build the verilator model (if not already done)
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fusesoc run --target=verilator_tb --build servant
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fusesoc run --target=verilator_tb --build servant --memsize=8388608
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To build the verilator model with MDU (for M extension compliance tests):
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fusesoc run --target=verilator_tb --flag=mdu --build servant --memsize=8388608
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Download the tests repo
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git clone https://github.com/riscv/riscv-compliance --branch 1.0
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git clone https://github.com/riscv-non-isa/riscv-arch-test.git
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To run the RISC-V compliance tests, we need to supply the SERV-specific support files and point the test suite to where it can find a target to run (i.e. the previously built Verilator model)
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Run the compliance tests
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cd riscv-compliance && make TARGETDIR=$SERV/riscv-target RISCV_TARGET=serv RISCV_DEVICE=rv32i RISCV_ISA=rv32i TARGET_SIM=$WORKSPACE/build/servant_1.1.0/verilator_tb-verilator/Vservant_sim
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cd riscv-arch-test && make TARGETDIR=$SERV/riscv-target RISCV_TARGET=serv RISCV_DEVICE=I TARGET_SIM=$WORKSPACE/build/servant_1.1.0/verilator_tb-verilator/Vservant_sim
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The above will run all tests in the rv32i test suite. Since SERV also implement the `rv32im`, `rv32Zicsr` and `rv32Zifencei` extensions, these can also be tested by choosing any of them instead of rv32i as the `RISCV_ISA` variable.
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The above will run all tests in the rv32i test suite. Since SERV also implement the `M`, `privilege` and `Zifencei` extensions, these can also be tested by choosing any of them instead of `I` as the `RISCV_DEVICE` variable.
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## Run on hardware
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@ -1,36 +0,0 @@
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// RISC-V Compliance IO Test Header File
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/*
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* Copyright (c) 2005-2018 Imperas Software Ltd., www.imperas.com
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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* either express or implied.
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*
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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*/
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#ifndef _COMPLIANCE_IO_H
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#define _COMPLIANCE_IO_H
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//-----------------------------------------------------------------------
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// RV IO Macros (Non functional)
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//-----------------------------------------------------------------------
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#define RVTEST_IO_INIT
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#define RVTEST_IO_WRITE_STR(_SP, _STR)
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#define RVTEST_IO_CHECK()
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#define RVTEST_IO_ASSERT_GPR_EQ(_SP, _R, _I)
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#define RVTEST_IO_ASSERT_SFPR_EQ(_F, _R, _I)
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#define RVTEST_IO_ASSERT_DFPR_EQ(_D, _R, _I)
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#endif // _COMPLIANCE_IO_H
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@ -1,67 +0,0 @@
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// RISC-V Compliance Test Header File
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// Copyright (c) 2017, Codasip Ltd. All Rights Reserved.
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// See LICENSE for license details.
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//
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// Description: Common header file for RV32I tests
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#ifndef _COMPLIANCE_TEST_H
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#define _COMPLIANCE_TEST_H
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//-----------------------------------------------------------------------
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// RV Compliance Macros
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//-----------------------------------------------------------------------
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#define RV_COMPLIANCE_HALT \
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la a0, data_begin; \
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la a1, data_end; \
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li a2, 0x80000000; \
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complience_halt_loop: \
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beq a0, a1, complience_halt_break; \
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addi a3, a0, 4; \
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complience_halt_loop2: \
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addi a3, a3, -1; \
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\
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lb a4, 0 (a3); \
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srai a5, a4, 4; \
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andi a5, a5, 0xF; \
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li a6, 10; \
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blt a5, a6, notLetter; \
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addi a5, a5, 39; \
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notLetter: \
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addi a5, a5, 0x30; \
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sw a5, 0 (a2); \
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\
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srai a5, a4, 0; \
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andi a5, a5, 0xF; \
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li a6, 10; \
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blt a5, a6, notLetter2; \
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addi a5, a5, 39; \
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notLetter2: \
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addi a5, a5, 0x30; \
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sw a5, 0 (a2); \
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bne a0, a3,complience_halt_loop2; \
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addi a0, a0, 4; \
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\
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li a4, '\n'; \
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sw a4, 0 (a2); \
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j complience_halt_loop; \
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j complience_halt_break; \
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complience_halt_break:; \
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lui a0,0x90000000>>12; \
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sw a3,0(a0);
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#define RV_COMPLIANCE_RV32M
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#define RV_COMPLIANCE_CODE_BEGIN \
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.section .text.init; \
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.align 4; \
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.globl _start; \
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_start: \
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#define RV_COMPLIANCE_CODE_END
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#define RV_COMPLIANCE_DATA_BEGIN .align 4; .global data_begin; data_begin:
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#define RV_COMPLIANCE_DATA_END .align 4; .global data_end; data_end:
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#endif
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@ -5,7 +5,7 @@ endif
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RUN_TARGET=\
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$(TARGET_SIM) \
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+timeout=100000000 \
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+timeout=100000000000 \
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+signature=$(*).signature.output \
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+firmware=$(<).hex 2> $@
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@ -23,4 +23,4 @@ COMPILE_TARGET=\
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-o $$@; \
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$$(RISCV_OBJCOPY) -O binary $$@ $$@.bin; \
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$$(RISCV_OBJDUMP) -D $$@ > $$@.objdump; \
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python3 $(TARGETDIR)/$(RISCV_TARGET)/makehex.py $$@.bin 2048 > $$@.hex;
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python3 $(TARGETDIR)/$(RISCV_TARGET)/makehex.py $$@.bin 524288 > $$@.hex;
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26
riscv-target/serv/device/rv32i_m/M/Makefile.include
Normal file
26
riscv-target/serv/device/rv32i_m/M/Makefile.include
Normal file
@ -0,0 +1,26 @@
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TARGET_SIM ?= server
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ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
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$(error Target simulator executable '$(TARGET_SIM)` not found)
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endif
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RUN_TARGET=\
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$(TARGET_SIM) \
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+timeout=100000000000 \
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+signature=$(*).signature.output \
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+firmware=$(<).hex 2> $@
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RISCV_PREFIX ?= riscv32-unknown-elf-
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RISCV_GCC ?= $(RISCV_PREFIX)gcc
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RISCV_OBJCOPY ?= $(RISCV_PREFIX)objcopy
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RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump
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RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
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COMPILE_TARGET=\
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$$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
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-I$(ROOTDIR)/riscv-test-env/ \
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-I$(TARGETDIR)/$(RISCV_TARGET)/ \
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-T$(TARGETDIR)/$(RISCV_TARGET)/link.ld $$< \
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-o $$@; \
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$$(RISCV_OBJCOPY) -O binary $$@ $$@.bin; \
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$$(RISCV_OBJDUMP) -D $$@ > $$@.objdump; \
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python3 $(TARGETDIR)/$(RISCV_TARGET)/makehex.py $$@.bin 524288 > $$@.hex;
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26
riscv-target/serv/device/rv32i_m/Zifencei/Makefile.include
Normal file
26
riscv-target/serv/device/rv32i_m/Zifencei/Makefile.include
Normal file
@ -0,0 +1,26 @@
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TARGET_SIM ?= server
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ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
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$(error Target simulator executable '$(TARGET_SIM)` not found)
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endif
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RUN_TARGET=\
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$(TARGET_SIM) \
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+timeout=100000000000 \
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+signature=$(*).signature.output \
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+firmware=$(<).hex 2> $@
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RISCV_PREFIX ?= riscv32-unknown-elf-
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RISCV_GCC ?= $(RISCV_PREFIX)gcc
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RISCV_OBJCOPY ?= $(RISCV_PREFIX)objcopy
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RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump
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RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
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COMPILE_TARGET=\
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$$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
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-I$(ROOTDIR)/riscv-test-env/ \
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-I$(TARGETDIR)/$(RISCV_TARGET)/ \
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-T$(TARGETDIR)/$(RISCV_TARGET)/link.ld $$< \
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-o $$@; \
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$$(RISCV_OBJCOPY) -O binary $$@ $$@.bin; \
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$$(RISCV_OBJDUMP) -D $$@ > $$@.objdump; \
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python3 $(TARGETDIR)/$(RISCV_TARGET)/makehex.py $$@.bin 524288 > $$@.hex;
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26
riscv-target/serv/device/rv32i_m/privilege/Makefile.include
Normal file
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riscv-target/serv/device/rv32i_m/privilege/Makefile.include
Normal file
@ -0,0 +1,26 @@
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TARGET_SIM ?= server
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ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
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$(error Target simulator executable '$(TARGET_SIM)` not found)
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endif
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RUN_TARGET=\
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$(TARGET_SIM) \
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+timeout=100000000000 \
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+signature=$(*).signature.output \
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+firmware=$(<).hex 2> $@
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RISCV_PREFIX ?= riscv32-unknown-elf-
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RISCV_GCC ?= $(RISCV_PREFIX)gcc
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RISCV_OBJCOPY ?= $(RISCV_PREFIX)objcopy
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RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump
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RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
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COMPILE_TARGET=\
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$$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
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-I$(ROOTDIR)/riscv-test-env/ \
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-I$(TARGETDIR)/$(RISCV_TARGET)/ \
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-T$(TARGETDIR)/$(RISCV_TARGET)/link.ld $$< \
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-o $$@; \
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$$(RISCV_OBJCOPY) -O binary $$@ $$@.bin; \
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$$(RISCV_OBJDUMP) -D $$@ > $$@.objdump; \
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python3 $(TARGETDIR)/$(RISCV_TARGET)/makehex.py $$@.bin 524288 > $$@.hex;
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71
riscv-target/serv/model_test.h
Normal file
71
riscv-target/serv/model_test.h
Normal file
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#ifndef _COMPLIANCE_MODEL_H
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#define _COMPLIANCE_MODEL_H
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#define RVMODEL_HALT \
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la a0, begin_signature; \
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la a1, end_signature; \
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li a2, 0x80000000; \
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complience_halt_loop: \
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beq a0, a1, complience_halt_break; \
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addi a3, a0, 4; \
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complience_halt_loop2: \
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addi a3, a3, -1; \
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\
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lb a4, 0 (a3); \
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srai a5, a4, 4; \
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andi a5, a5, 0xF; \
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li a6, 10; \
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blt a5, a6, notLetter; \
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addi a5, a5, 39; \
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notLetter: \
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addi a5, a5, 0x30; \
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sw a5, 0 (a2); \
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\
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srai a5, a4, 0; \
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andi a5, a5, 0xF; \
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li a6, 10; \
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blt a5, a6, notLetter2; \
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addi a5, a5, 39; \
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notLetter2: \
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addi a5, a5, 0x30; \
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sw a5, 0 (a2); \
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bne a0, a3,complience_halt_loop2; \
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addi a0, a0, 4; \
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\
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li a4, '\n'; \
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sw a4, 0 (a2); \
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j complience_halt_loop; \
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j complience_halt_break; \
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complience_halt_break:; \
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lui a0,0x90000000>>12; \
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sw a3,0(a0);
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#define RVMODEL_DATA_BEGIN \
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.align 4; .global begin_signature; begin_signature: \
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#define RVMODEL_DATA_END \
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.align 4; .global end_signature; end_signature: \
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#define RVMODEL_BOOT \
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.section .text.init; \
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.align 4; \
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.globl _start; \
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_start:
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#define LOCAL_IO_WRITE_STR(_STR) RVMODEL_IO_WRITE_STR(x31, _STR)
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#define RVMODEL_IO_WRITE_STR(_SP, _STR)
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#define LOCAL_IO_PUSH(_SP)
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#define LOCAL_IO_POP(_SP)
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#define RVMODEL_IO_ASSERT_GPR_EQ(_SP, _R, _I)
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#define RVMODEL_IO_ASSERT_SFPR_EQ(_F, _R, _I)
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#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I)
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#define RVMODEL_SET_MSW_INT
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#define RVMODEL_CLEAR_MSW_INT
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#define RVMODEL_CLEAR_MTIMER_INT
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#define RVMODEL_CLEAR_MEXT_INT
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#endif // _COMPLIANCE_MODEL_H
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