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Optimize alu eq_r and lt_r

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Olof Kindgren
2019-12-03 10:28:27 +01:00
parent 8b82c85fb6
commit 3179cfb107
1 changed files with 3 additions and 5 deletions
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8
rtl/serv_alu.v
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@@ -93,7 +93,7 @@ module serv_alu
.i_clk (clk),
.i_a (i_rs1),
.i_b (i_op_b),
.i_clr (!i_init),
.i_clr (!i_en),
.i_sign (i_cnt_done & !i_cmp_uns),
.o_q (result_lt));
@@ -112,12 +112,10 @@ module serv_alu
reg eq_r;
always @(posedge clk) begin
if (i_init) begin
if (i_en) begin
result_lt_r <= result_lt;
eq_r <= result_eq;
end else begin
eq_r <= 1'b1;
end
eq_r <= result_eq | ~i_en;
en_r <= i_en;
end