github.com/olofk.serv
1
0
Fork 0
mirror of https://github.com/olofk/serv.git synced 2026-03-01 17:25:51 +00:00
Code Issues Releases Wiki Activity

Declare trap_pending before use

Browse Source
This commit is contained in:
Olof Kindgren
2025-10-17 17:38:00 +02:00
parent 7d9cde4e6c
commit 61ef8eaef9
1 changed files with 5 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
rtl/serv_state.v
View File

@@ -100,6 +100,11 @@ module serv_state
//valid signal for mdu
assign o_mdu_valid = MDU & !o_cnt_en & init_done & i_mdu_op;
//trap_pending is only guaranteed to have correct value during the
// last cycle of the init stage
wire trap_pending = WITH_CSR & ((take_branch & i_ctrl_misalign & !ALIGN) |
(i_dbus_en & i_mem_misalign));
//Prepare RF for writes when everything is ready to enter stage two
// and the first stage didn't cause a misalign exception
//Left shifts, SLT & Branch ops. First cycle after init
@@ -218,11 +223,6 @@ module serv_state
assign o_ctrl_trap = WITH_CSR & (i_e_op | i_new_irq | misalign_trap_sync);
//trap_pending is only guaranteed to have correct value during the
// last cycle of the init stage
wire trap_pending = WITH_CSR & ((take_branch & i_ctrl_misalign & !ALIGN) |
(i_dbus_en & i_mem_misalign));
generate
if (WITH_CSR) begin : gen_csr
reg misalign_trap_sync_r;