github.com/olofk.serv
1
0
Fork 0
mirror of https://github.com/olofk/serv.git synced 2026-01-13 23:25:57 +00:00
Code Issues Releases Wiki Activity

Kill of mem_init and mem_en

Browse Source
This commit is contained in:
Olof Kindgren 2019-09-13 23:03:58 +02:00
parent e20e0eef8f
commit 8dc137fb07
3 changed files with 14 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
rtl/serv_decode.v
View File

@ -41,9 +41,8 @@ module serv_decode
input wire i_alu_sh_done,
output reg [1:0] o_alu_rd_sel,
output wire o_dbus_cyc,
output wire o_mem_en,
output wire o_mem_op,
output wire o_mem_cmd,
output wire o_mem_init,
output wire [1:0] o_mem_bytecnt,
input wire i_mem_misalign,
output wire o_rd_csr_en,
@ -94,6 +93,7 @@ module serv_decode
assign o_cnt_done = cnt_done;
assign mem_op = !opcode[4] & !opcode[2] & !opcode[0];
assign o_mem_op = mem_op;
wire op_or_opimm = (!opcode[4] & opcode[2] & !opcode[0]);
@ -195,10 +195,8 @@ module serv_decode
assign o_alu_sh_signed = imm30;
assign o_alu_sh_right = o_funct3[2];
assign o_mem_en = mem_op & cnt_en;
assign o_mem_cmd = opcode[3];
assign o_mem_init = mem_op & (state == INIT);
assign o_mem_bytecnt = o_cnt[4:3];
assign o_alu_bool_op = o_funct3[1:0];
@ -280,9 +278,11 @@ module serv_decode
assign o_ctrl_trap = (state == TRAP);
wire mem_misalign = mem_op & i_mem_misalign;
always @(posedge clk) begin
o_csr_mcause[3:0] <= 4'd0;
if (i_mem_misalign)
if (mem_misalign)
o_csr_mcause[3:0] <= {2'b01, o_mem_cmd, 1'b0};
if (e_op)
o_csr_mcause <= {!op20,3'b011};
@ -299,7 +299,7 @@ module serv_decode
assign o_rf_rs_en = two_stage_op ? (state == INIT) : o_ctrl_pc_en;
assign o_dbus_cyc = (state == IDLE) & stage_one_done & mem_op & !i_mem_misalign;
assign o_dbus_cyc = (state == IDLE) & stage_one_done & mem_op & !mem_misalign;
always @(posedge clk) begin
if (state == INIT)
@ -329,7 +329,7 @@ module serv_decode
stage_one_done <= 1'b1;
if (cnt_done)
if (i_mem_misalign | (take_branch & i_ctrl_misalign))
if (mem_misalign | (take_branch & i_ctrl_misalign))
state <= TRAP;
else if (mem_op | shift_op ) begin
state <= IDLE;

2
rtl/serv_mem_if.v
View File

@ -91,7 +91,7 @@ module serv_mem_if
if (wb_en)
{dat3,dat2,dat1,dat0} <= i_wb_rdt;
o_misalign <= i_en & ((bytepos[0] & !is_byte) | (bytepos[1] & is_word));
o_misalign <= (bytepos[0] & !is_byte) | (bytepos[1] & is_word);
if (dat_valid)
signbit <= dat_cur;

14
rtl/serv_top.v
View File

@ -99,12 +99,11 @@ module serv_top
wire op_b_source;
wire op_b;
wire mem_en;
wire mem_op;
wire mem_cmd;
wire [1:0] mem_bytecnt;
wire mem_init;
wire mem_misalign;
wire bad_pc;
@ -130,6 +129,7 @@ module serv_top
(
.clk (clk),
.i_rst (i_rst),
.o_mem_op (mem_op),
.i_new_irq (new_irq),
.i_wb_rdt (i_ibus_rdt),
.i_wb_en (o_ibus_cyc & i_ibus_ack),
@ -169,9 +169,7 @@ module serv_top
.o_rf_rs1_addr (rs1_addr),
.o_rf_rs2_addr (rs2_addr),
.o_dbus_cyc (o_dbus_cyc),
.o_mem_en (mem_en),
.o_mem_cmd (mem_cmd),
.o_mem_init (mem_init),
.o_mem_bytecnt (mem_bytecnt),
.i_mem_misalign (mem_misalign),
.o_rd_csr_en (rd_csr_en),
@ -200,7 +198,7 @@ module serv_top
.i_cnt (cnt[4:2]),
.i_cnt_r (cnt_r[1:0]),
.i_en (!(bufreg_hold | o_dbus_cyc)),
.i_clr (!(mem_en | (jal_or_jalr & alu_init))), //FIXME
.i_clr (!((alu_en & mem_op) | (jal_or_jalr & alu_init))), //FIXME
.i_loop (bufreg_loop),
.i_rs1 (rs1),
.i_rs1_en (bufreg_rs1_en),
@ -291,7 +289,7 @@ module serv_top
//Trap interface
.i_trap (trap),
.i_mepc (o_ibus_adr[0]),
.i_mtval (mem_misalign ? bufreg_q : bad_pc),
.i_mtval ((mem_misalign & mem_op) ? bufreg_q : bad_pc),
.o_csr_pc (csr_pc),
//CSR write port
.i_csr_en (csr_en),
@ -317,8 +315,8 @@ module serv_top
(
.i_clk (clk),
.i_rst (i_rst),
.i_en (mem_en),
.i_init (mem_init),
.i_en (alu_en),
.i_init (alu_init),
.i_cnt_done (cnt_done),
.i_cmd (mem_cmd),
.i_bytecnt (mem_bytecnt),