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Decouple ibus_cyc and ibus_ack

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Olof Kindgren
2020-11-30 23:13:11 +01:00
parent 90ce4ff1af
commit bbe3e56ab2
2 changed files with 3 additions and 3 deletions
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2
rtl/serv_ctrl.v
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@@ -74,7 +74,7 @@ module serv_ctrl
pc_plus_4_cy_r <= i_pc_en & pc_plus_4_cy;
pc_plus_offset_cy_r <= i_pc_en & pc_plus_offset_cy;
if (o_ibus_cyc & i_ibus_ack | i_pc_en | i_rst)
if (i_ibus_ack | i_pc_en | i_rst)
en_pc_r <= i_pc_en | i_rst;
if (RESET_STRATEGY == "NONE") begin

4
rtl/serv_top.v
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@@ -209,7 +209,7 @@ module serv_top
.clk (clk),
//Input
.i_wb_rdt (i_ibus_rdt[31:2]),
.i_wb_en (o_ibus_cyc & i_ibus_ack),
.i_wb_en (i_ibus_ack),
//To state
.o_bne_or_bge (bne_or_bge),
.o_cond_branch (cond_branch),
@@ -265,7 +265,7 @@ module serv_top
.i_csr_imm_en (csr_imm_en),
.o_csr_imm (csr_imm),
.i_wb_rdt (i_ibus_rdt[31:2]),
.i_wb_en (o_ibus_cyc & i_ibus_ack),
.i_wb_en (i_ibus_ack),
.i_ctrl (immdec_ctrl),
.i_cnt_done (cnt_done),
//To RF