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Pass rf_rreq through serv_state
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@ -4,6 +4,8 @@ module serv_state
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input wire i_rst,
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input wire i_new_irq,
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input wire i_dbus_ack,
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input wire i_ibus_ack,
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output wire o_rf_rreq,
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input wire i_rf_ready,
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input wire i_take_branch,
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input wire i_branch_op,
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@ -84,6 +86,8 @@ module serv_state
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assign o_dbus_cyc = (state == IDLE) & stage_two_pending & i_mem_op & !mem_misalign;
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assign o_rf_rreq = i_ibus_ack;
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always @(posedge i_clk) begin
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if (state == INIT)
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o_ctrl_jump <= i_take_branch;
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@ -98,6 +98,7 @@ module serv_top
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wire alu_sh_done;
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wire [1:0] alu_rd_sel;
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wire rf_rreq;
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wire rf_ready;
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wire rs1;
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wire rs2;
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@ -141,6 +142,8 @@ module serv_top
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.i_rst (i_rst),
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.i_new_irq (new_irq),
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.i_dbus_ack (i_dbus_ack),
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.i_ibus_ack (i_ibus_ack),
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.o_rf_rreq (rf_rreq),
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.i_rf_ready (rf_ready),
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.i_take_branch (take_branch),
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.i_branch_op (branch_op),
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@ -341,7 +344,7 @@ module serv_top
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.i_rd_waddr (rd_addr),
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.i_rd (rd),
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.i_rreq (i_ibus_ack),
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.i_rreq (rf_rreq),
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.o_rgnt (rf_ready),
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//RS1 read port
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.i_rs1_raddr (rs1_addr),
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