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Code Issues Releases Wiki Activity

Pass rf_rreq through serv_state

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Olof Kindgren
2019-09-16 20:54:26 +02:00
parent 3d6eb3feca
commit ca2beaf786
2 changed files with 8 additions and 1 deletions
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4
rtl/serv_state.v
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@@ -4,6 +4,8 @@ module serv_state
input wire i_rst, input wire i_rst,
input wire i_new_irq, input wire i_new_irq,
input wire i_dbus_ack, input wire i_dbus_ack,
input wire i_ibus_ack,
output wire o_rf_rreq,
input wire i_rf_ready, input wire i_rf_ready,
input wire i_take_branch, input wire i_take_branch,
input wire i_branch_op, input wire i_branch_op,
@@ -84,6 +86,8 @@ module serv_state
assign o_dbus_cyc = (state == IDLE) & stage_two_pending & i_mem_op & !mem_misalign; assign o_dbus_cyc = (state == IDLE) & stage_two_pending & i_mem_op & !mem_misalign;
assign o_rf_rreq = i_ibus_ack;
always @(posedge i_clk) begin always @(posedge i_clk) begin
if (state == INIT) if (state == INIT)
o_ctrl_jump <= i_take_branch; o_ctrl_jump <= i_take_branch;

5
rtl/serv_top.v
View File

@@ -98,6 +98,7 @@ module serv_top
wire alu_sh_done; wire alu_sh_done;
wire [1:0] alu_rd_sel; wire [1:0] alu_rd_sel;
wire rf_rreq;
wire rf_ready; wire rf_ready;
wire rs1; wire rs1;
wire rs2; wire rs2;
@@ -141,6 +142,8 @@ module serv_top
.i_rst (i_rst), .i_rst (i_rst),
.i_new_irq (new_irq), .i_new_irq (new_irq),
.i_dbus_ack (i_dbus_ack), .i_dbus_ack (i_dbus_ack),
.i_ibus_ack (i_ibus_ack),
.o_rf_rreq (rf_rreq),
.i_rf_ready (rf_ready), .i_rf_ready (rf_ready),
.i_take_branch (take_branch), .i_take_branch (take_branch),
.i_branch_op (branch_op), .i_branch_op (branch_op),
@@ -341,7 +344,7 @@ module serv_top
.i_rd_waddr (rd_addr), .i_rd_waddr (rd_addr),
.i_rd (rd), .i_rd (rd),
.i_rreq (i_ibus_ack), .i_rreq (rf_rreq),
.o_rgnt (rf_ready), .o_rgnt (rf_ready),
//RS1 read port //RS1 read port
.i_rs1_raddr (rs1_addr), .i_rs1_raddr (rs1_addr),