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Olof Kindgren 2019-09-16 16:57:56 +02:00
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@ -41,19 +41,19 @@ Running test software
Build and run the single threaded zephyr hello world example with verilator
cd $SERV/workspace
fusesoc run --target=verilator_tb serv --uart_baudrate=57600 --firmware=../serv/sw/zephyr_hello.hex
fusesoc run --target=verilator_tb servant --uart_baudrate=57600 --firmware=../serv/sw/zephyr_hello.hex
..or... the multithreaded version
fusesoc run --target=verilator_tb serv --uart_baudrate=57600 --firmware=../serv/sw/zephyr_hello_mt.hex --memsize=16384
fusesoc run --target=verilator_tb servant --uart_baudrate=57600 --firmware=../serv/sw/zephyr_hello_mt.hex --memsize=16384
...or... the philosophers example
fusesoc run --target=verilator_tb serv --uart_baudrate=57600 --firmware=../serv/sw/zephyr_phil.hex --memsize=32768
fusesoc run --target=verilator_tb servant --uart_baudrate=57600 --firmware=../serv/sw/zephyr_phil.hex --memsize=32768
...or... the synchronization example
fusesoc run --target=verilator_tb serv --uart_baudrate=57600 --firmware=../serv/sw/zephyr_sync.hex --memsize=16384
fusesoc run --target=verilator_tb servant --uart_baudrate=57600 --firmware=../serv/sw/zephyr_sync.hex --memsize=16384
Other applications can be tested by compiling and converting to bin and then hex e.g. with makehex.py found in $SERV/serv/riscv-target/serv
@ -62,7 +62,7 @@ Run the compliance tests
Build the verilator model (if not already done)
`cd $SERV/workspace && fusesoc run --target=verilator_tb --setup --build serv`
`cd $SERV/workspace && fusesoc run --target=verilator_tb --setup --build servant`
Download the tests repo
@ -82,7 +82,7 @@ TinyFPGA BX
Pin A6 is used for UART output with 115200 baud rate.
cd $SERV/workspace
fusesoc run --target=tinyfpga_bx serv
fusesoc run --target=tinyfpga_bx servant
tinyprog --program build/serv_0/tinyfpga_bx-icestorm/serv_0.bin
Icebreaker
@ -90,10 +90,31 @@ Icebreaker
Pin 9 is used for UART output with 57600 baud rate.
cd $SERV/workspace
fusesoc run --target=icebreaker serv
fusesoc run --target=icebreaker servant
Run with `--firmware=../serv/sw/blinky.hex` as the last argument to run the LED blink example instead
Other targets
-------------
The above targets are run on the servant SoC, but there are some targets defined for the CPU itself. Verilator can be run in lint mode to check for design problems by running
fusesoc run --target=lint serv
It's also possible to just synthesise for different targets to check resource usage and such. To do that for the iCE40 devices, run
fusesoc run --tool=icestorm serv --pnr=none
...or to synthesize with vivado for Xilinx targets, run
fusesoc run --tool=vivado serv --pnr=none
This will synthesize for the default Vivado part. To synthesise for a specific device, run e.g.
fusesoc run --tool=vivado serv --pnr=none --part=xc7a100tcsg324-1
At the time of writing, only the icestorm and vivado backends support running synthesis only.
Good to know
------------