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Author SHA1 Message Date
Olof Kindgren
344940c655 Update to latest checkout GH action 2024-06-16 09:45:26 +02:00
Olof Kindgren
783e92b576 Add missing descriptions to core description files 2024-06-16 09:45:26 +02:00
Olof Kindgren
472f89d532 servant: Add default program to sim target 2024-06-16 09:45:26 +02:00
Greg Steiert
4d95bd0f21
added support for MAX10 10M08 Evaluation Kit 2024-06-16 09:44:13 +02:00
Olof Kindgren
bbd3920ce8 Add missing Servant ports to doc 2024-06-15 15:30:19 +02:00
Chandler Jearls
8381bcdc4b Adding support for DE1 SoC revF board for servant 2024-06-15 15:15:08 +02:00
Olof Kindgren
3ef80ce4e0 Make servile_mux more simulator-friendly 2024-06-15 15:05:51 +02:00
Nazar Kazakov
d577062672 Add ECP5 evaluation board target 
Done by analogy with ulx3s target
 2024-06-15 13:04:53 +00:00
BradWalker
3b9331b3b5 Add Servant support for Alchitry Au platform. 
fusesoc core show servant
CORE INFO
Name:        ::servant:1.2.1
Description: <No description>
Core root:   fusesoc_libraries/serv
Core file:   servant.core
Targets:
alchitry_au         : Open-hardware Alchitry AU FPGA board

Creating bitstream...
Writing bitstream ./servix.bit...
Writing bitstream ./servix.bin...

Bitstream generation completed
INFO: [Common 17-206] Exiting Vivado at Fri Jun 14 16:49:54 2024...

Resources used
fusesoc run --target=alchitry_au servant --uart_baudrate=57600 --memfile ./fusesoc_libraries/serv/sw/zephyr_hello.hex

+----------------------------+------+-------+------------+-----------+-------+
|          Site Type         | Used | Fixed | Prohibited | Available | Util% |
+----------------------------+------+-------+------------+-----------+-------+
| Slice LUTs                 |  244 |     0 |          0 |     20800 |  1.17 |
|   LUT as Logic             |  243 |     0 |          0 |     20800 |  1.17 |
|   LUT as Memory            |    1 |     0 |          0 |      9600 |  0.01 |
|     LUT as Distributed RAM |    0 |     0 |            |           |       |
|     LUT as Shift Register  |    1 |     0 |            |           |       |
| Slice Registers            |  238 |     0 |          0 |     41600 |  0.57 |
|   Register as Flip Flop    |  238 |     0 |          0 |     41600 |  0.57 |
|   Register as Latch        |    0 |     0 |          0 |     41600 |  0.00 |
| F7 Muxes                   |    3 |     0 |          0 |     16300 |  0.02 |
| F8 Muxes                   |    0 |     0 |          0 |      8150 |  0.00 |
+----------------------------+------+-------+------------+-----------+-------+
 2024-06-15 13:03:53 +00:00
Anton Kuzmin
1000ee3495 Add support for GMM-7550 module (Cologne Chip GateMate FPGA) 2024-06-15 12:55:42 +00:00
BradWalker
086090046c Allow the serv software Makefile to use a different compiler prefix if defined. 2024-05-26 06:29:49 +00:00
Nazar Kazakov
a26c2965c0 Fix typos 2024-04-06 16:35:45 +02:00
Olof Kindgren
bebc875353 Make serv_state more simulator-friendly 
Refactor the counter generation code to avoid using combinatorial
always statements that rely on an event happening at time 0. This
make serv work with Icarus again.
 2024-03-19 12:40:50 +01:00
Olof Kindgren
4537abb965 bufreg refactoring in preparation of qerv integration 2024-03-06 20:22:23 +01:00
Olof Kindgren
b937ef61aa Add width-agnostic serv_rf_ram_if 2024-02-23 14:35:38 +01:00
Olof Kindgren
907db143ea Support w=4 in serv_rf_if 2024-02-22 13:27:04 +01:00
Olof Kindgren
f68a0889aa Support w=4 in serv_ctrl 2024-02-22 13:12:07 +01:00
Olof Kindgren
6659811160 Add width-agnostic serv_csr 2024-02-22 12:29:20 +01:00
Olof Kindgren
923b53ce0b Add hello world ASM example 2024-02-20 09:48:34 +01:00
Olof Kindgren
a92965b359 Add cycle counter to servant testbench 2024-02-20 09:43:33 +01:00
Olof Kindgren
086fff75b6 servile_mux: Only catch writes to sim_sig_adr when signature file is open 2024-02-15 21:39:25 +01:00
Olof Kindgren
88a4711593 Use servile as base for serving 2024-02-14 22:06:57 +01:00
Olof Kindgren
970c6fddca Use Servile as a base for servant 2024-02-14 22:06:57 +01:00
Olof Kindgren
8d91e2d288 Add Servile convenience wrapper 
Servile is a new convenience wrapper that implements common common configuration
for SERV-based systems so that they don't have to be repeated in every design.
 2024-02-14 22:06:57 +01:00
Olof Kindgren
1dc37d9fd4 Fix path to GDS file in openlane CI runner 2024-02-14 22:06:57 +01:00
Olof Kindgren
51c7833fa8 Refactor docs 2024-02-14 22:06:57 +01:00
Busted Wing
c469c3174b Update README.md to add blinky to pre-built test software examples 2024-02-05 12:41:04 +00:00
inc
c0320fded4 add support for machdyne kolibri 2024-01-26 22:42:02 +00:00
Liam Beguin
40a9e99f77 add PolarFire Splash Kit support 
Signed-off-by: Liam Beguin <liambeguin@gmail.com>
 2023-12-29 22:39:11 +01:00
Liam Beguin
9d4ebaa358 servant: parameters: specify frequency is to be in MHz 
Signed-off-by: Liam Beguin <liambeguin@gmail.com>
 2023-12-29 22:39:11 +01:00
Liam Beguin
6e9a6601f3 servant: ice: rename service clock gen source 
Make it more explicit that this clock generator is for the ICE FPGA
family.

Signed-off-by: Liam Beguin <liambeguin@gmail.com>
 2023-12-29 22:39:11 +01:00
Markus
b2b1110e95
Port to Zephyr v3.5.0 + Fix System Timer (#111) 
zephyr: Port to Zephyr v3.5.0
 2023-12-11 08:49:08 +00:00
Olof Kindgren
adb3f4d5a4 Delete trailing whitespace from RTL 2023-12-03 18:21:01 +01:00
Olof Kindgren
7cc00c8627 Add build.tools to RTD config 2023-11-17 13:53:31 +01:00
Jani Alinikula
bc984f6639 Change timer wraparound behavior to be more useful 2023-11-17 09:27:52 +01:00
Olof Kindgren
bc74a9a1d7 Used named generate statements 
Unnamed generate statements are not recommended and some tools throw
warnings or errors for these.
 2023-11-16 21:38:10 +01:00
Katherine Watson
7a6d5d3fc9 Make serv_alu.v synthesizable with Vivado 2023-11-16 14:41:46 +01:00
Olof Kindgren
c7fc57213c Avoid releasing trap signal too early 
The trap signal is used my the mux in serv_rf_if to decide which
registers to write to. If the trap signal is dropped too early,
the destination address changes while the register is still being
written to.
 2023-10-31 22:21:12 +01:00
uhit332
46a820ee42 support for W=4 2023-10-31 15:53:36 +01:00
uhit332
f9d6b23543 support for W=4 2023-10-31 13:23:17 +01:00
Olof Kindgren
a8fbf688c5 Fix RTD CI action failures 2023-10-31 12:45:31 +01:00
uhit332
2e23b5313a alu with support for W=4 2023-10-31 12:42:52 +01:00
Olof Kindgren
ed4b8198ac Skip disassembly of test cases in riscof plugin 
Disassembly takes a lot of time with some toolchains, so leave that
to the user instead.
 2023-07-21 12:25:25 +02:00
Olof Kindgren
4567214721 Refactor counter in serv_state 2023-07-13 10:29:19 +02:00
Olof Kindgren
f0f2dba67f Add PC tracing capability 
This adds the --trace_pc option to dump the PC after each instruction to a file
called trace.bin
 2023-07-12 22:00:36 +02:00
Olof Kindgren
9bb2f95bf4 Tidy up GH Actions naming 2023-07-10 15:07:38 +02:00
Olof Kindgren
c6e5053c78 Clean up RISCOF support structure 
The RISCOF regression test suite can now be run from a workspace instead
of having to be run from inside the repo. Also removes the need for a
submodule.
 2023-07-10 15:06:13 +02:00
Olof Kindgren
cd3b587364 Add linting for servant and serving to Github actions 2023-06-22 15:49:04 +02:00
Olof Kindgren
8edd456b5d Rewrite serv_rf_ram_if 
This adds some optimizations to serv_rf_ram_if. It also adds a read enable
signal and delays writes one cycle which has the added bonus that no reads
or writes happen in the same cycle for RF_WIDTH > 2. This allows SERV to be
used with single-port RAMs in most cases.
 2023-06-22 15:48:25 +02:00
Olof Kindgren
a6e4d82a30 Enable support for tickless timer driver 2023-06-21 23:19:26 +02:00