Olof Kindgren
7bd89deb41
Simplify mret/csr address generation
2019-09-26 23:09:22 +02:00
Olof Kindgren
126937f16a
Rewrite RF and state machine
...
Big patch, but would take more work to split it up
2019-09-26 23:09:22 +02:00
Florian Zaruba
27621a285e
rtl: Make compatible to Synopsys Design Compiler
...
Synopysis DC has problems with forward references and initial
statements. Fixed that for better compatibility.
2019-09-26 22:57:40 +02:00
Olof Kindgren
1248043a39
Separate state and decode from CSR signals
2019-09-14 22:18:03 +02:00
Olof Kindgren
8cd9742b53
Use two write ports for RF/CSR RAM
2019-09-13 23:30:46 +02:00
Olof Kindgren
a0ba84096a
Simplify csr stuff
2019-09-13 23:30:46 +02:00
Olof Kindgren
16c93a58ee
Move mepc and mtval into RF memory
2019-07-08 07:49:58 +02:00
Olof Kindgren
fe9d2677ba
Add SERV_CLEAR_RAM parameter
2019-06-24 13:18:34 +02:00
Olof Kindgren
bad78b0bd7
Declare wires before use
2019-06-24 13:18:34 +02:00
Olof Kindgren
42ac1e5e4d
Store CSR in RF RAM
...
Since FPGA uses fixed-size RAM, it's better in most cases to store
the CSR in unused memory positions in that RAM.
Since the decoding is made more complex, the old register file
implementation is kept around since that is more efficient when we
don't want CSR and potentially when the FPGA support hardware
shift registers.
2019-06-07 19:39:18 +02:00
