Olof Kindgren 8edd456b5d Rewrite serv_rf_ram_if ...

This adds some optimizations to serv_rf_ram_if. It also adds a read enable
signal and delays writes one cycle which has the added bonus that no reads
or writes happen in the same cycle for RF_WIDTH > 2. This allows SERV to be
used with single-port RAMs in most cases.

2023-06-22 15:48:25 +02:00

..

serv_aligner.v

Compressed Extension for SERV

2022-06-01 13:38:24 +02:00

serv_alu.v

Rewrite logic expression of alu bool operations

2021-05-15 23:07:55 +02:00

serv_bufreg2.v

Move dbus_dat/rs2/shamt storage to bufreg2

2022-01-02 22:10:33 +01:00

serv_bufreg.v

Simplify optional MDU logic

2021-10-03 23:28:45 +02:00

serv_compdec.v

Compressed Extension for SERV

2022-06-01 13:38:24 +02:00

serv_csr.v

Add reset for mie_mtie

2022-02-09 18:15:08 +01:00

serv_ctrl.v

Expose with_csr in servant

2022-07-26 00:28:53 +02:00

serv_decode.v

Compressed Extension for SERV

2022-06-01 13:38:24 +02:00

serv_immdec.v

updated vars declaration for modelsim (#63)

2021-10-03 23:15:54 +02:00

serv_mem_if.v

Move dbus_dat/rs2/shamt storage to bufreg2

2022-01-02 22:10:33 +01:00

serv_rf_if.v

Expose with_csr in servant

2022-07-26 00:28:53 +02:00

serv_rf_ram_if.v

Rewrite serv_rf_ram_if

2023-06-22 15:48:25 +02:00

serv_rf_ram.v

Rewrite serv_rf_ram_if

2023-06-22 15:48:25 +02:00

serv_rf_top.v

Rewrite serv_rf_ram_if

2023-06-22 15:48:25 +02:00

serv_state.v

privilege tests fixed for rv32i

2022-07-26 00:28:53 +02:00

serv_synth_wrapper.v

Remove RVFI interface from synth wrapper

2022-12-25 20:05:52 +01:00

serv_top.v

Set align parameter to the value of compressed by default

2022-12-25 21:34:48 +01:00