Olof Kindgren c7fc57213c Avoid releasing trap signal too early ...

The trap signal is used my the mux in serv_rf_if to decide which
registers to write to. If the trap signal is dropped too early,
the destination address changes while the register is still being
written to.

2023-10-31 22:21:12 +01:00

..

serv_aligner.v

Compressed Extension for SERV

2022-06-01 13:38:24 +02:00

serv_alu.v

alu with support for W=4

2023-10-31 12:42:52 +01:00

serv_bufreg2.v

Move dbus_dat/rs2/shamt storage to bufreg2

2022-01-02 22:10:33 +01:00

serv_bufreg.v

Simplify optional MDU logic

2021-10-03 23:28:45 +02:00

serv_compdec.v

Compressed Extension for SERV

2022-06-01 13:38:24 +02:00

serv_csr.v

Avoid releasing trap signal too early

2023-10-31 22:21:12 +01:00

serv_ctrl.v

Expose with_csr in servant

2022-07-26 00:28:53 +02:00

serv_decode.v

Compressed Extension for SERV

2022-06-01 13:38:24 +02:00

serv_immdec.v

updated vars declaration for modelsim (#63)

2021-10-03 23:15:54 +02:00

serv_mem_if.v

support for W=4

2023-10-31 13:23:17 +01:00

serv_rf_if.v

Expose with_csr in servant

2022-07-26 00:28:53 +02:00

serv_rf_ram_if.v

Rewrite serv_rf_ram_if

2023-06-22 15:48:25 +02:00

serv_rf_ram.v

Rewrite serv_rf_ram_if

2023-06-22 15:48:25 +02:00

serv_rf_top.v

Rewrite serv_rf_ram_if

2023-06-22 15:48:25 +02:00

serv_state.v

Avoid releasing trap signal too early

2023-10-31 22:21:12 +01:00

serv_synth_wrapper.v

Remove RVFI interface from synth wrapper

2022-12-25 20:05:52 +01:00

serv_top.v

Avoid releasing trap signal too early

2023-10-31 22:21:12 +01:00