mirror of
https://github.com/olofk/serv.git
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42ac1e5e4d
Since FPGA uses fixed-size RAM, it's better in most cases to store the CSR in unused memory positions in that RAM. Since the decoding is made more complex, the old register file implementation is kept around since that is more efficient when we don't want CSR and potentially when the FPGA support hardware shift registers.
105 lines
2.4 KiB
Verilog
105 lines
2.4 KiB
Verilog
`default_nettype none
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module serv_csr
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(
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input wire i_clk,
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input wire [4:0] i_cnt,
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input wire [3:0] i_cnt_r,
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//From mpram
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input wire i_rf_csr_out,
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//to mpram
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output wire o_csr_in,
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//Stuff
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input wire i_mtip,
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output wire o_timer_irq_en,
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input wire i_mstatus_en,
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input wire i_mie_en,
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input wire i_mip_en,
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input wire i_mepc_en,
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input wire i_mcause_en,
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input wire i_mtval_en,
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input wire [1:0] i_csr_source,
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input wire i_trap,
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input wire i_pc,
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input wire i_mtval,
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input wire [3:0] i_mcause,
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input wire i_d,
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output wire o_q);
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`include "serv_params.vh"
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/*
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300 mstatus RWSC
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304 mie SCWi
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305 mtvec RW
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344 mip CWi
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340 mscratch
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341 mepc RW
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342 mcause R
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343 mtval
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*/
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reg mstatus;
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reg mstatus_mie;
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reg mie_mtie;
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reg [31:0] mepc;
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reg mcause31;
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reg [3:0] mcause3_0;
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wire mcause;
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reg [31:0] mtval;
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wire csr_in;
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wire csr_out;
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assign csr_in = (i_csr_source == CSR_SOURCE_EXT) ? i_d :
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(i_csr_source == CSR_SOURCE_SET) ? csr_out | i_d :
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(i_csr_source == CSR_SOURCE_CLR) ? csr_out & ~i_d :
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(i_csr_source == CSR_SOURCE_CSR) ? csr_out :
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1'bx;
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assign csr_out = (i_mstatus_en & mstatus) |
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i_rf_csr_out |
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(i_mepc_en & mepc[0]) |
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(i_mcause_en & mcause) |
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(i_mtval_en & mtval[0]);
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assign o_q = csr_out;
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assign o_timer_irq_en = mstatus_mie & mie_mtie;
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assign mcause = (i_cnt[4:2] == 3'd0) ? mcause3_0[0] : //[3:0]
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((i_cnt[4:2] == 3'd7) & i_cnt_r[3]) ? mcause31 //[31]
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: 1'b0;
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assign o_csr_in = csr_in;
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always @(posedge i_clk) begin
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if (i_mstatus_en & (i_cnt[4:2] == 3'd0) & i_cnt_r[3])
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mstatus_mie <= csr_in;
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if (i_mie_en & (i_cnt[4:2] == 3'd1) & i_cnt_r[3])
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mie_mtie <= csr_in;
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mstatus <= (i_cnt[4:2] == 0) & i_cnt_r[2] & mstatus_mie;
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if (i_trap) begin
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mcause31 <= i_mtip & o_timer_irq_en;
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mcause3_0 <= (i_mtip & o_timer_irq_en) ? 4'd7 : i_mcause[3:0];
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end
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if (i_mepc_en | i_trap)
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mepc <= {i_trap ? i_pc : csr_in, mepc[31:1]};
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if (i_mcause_en) begin
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if (i_cnt[4:2] == 3'd0)
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mcause3_0 <= {csr_in, mcause3_0[3:1]};
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if ((i_cnt[4:2] == 3'd7) & i_cnt_r[3])
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mcause31 <= csr_in;
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end
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if (i_mtval_en | i_trap)
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mtval <= {i_trap ? i_mtval : csr_in, mtval[31:1]};
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end
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endmodule
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