Olof Kindgren fe9d2677ba Add SERV_CLEAR_RAM parameter

2019-06-24 13:18:34 +02:00

..

ser_add.v

Use custom interconnect. Runs on hw

2018-11-21 13:15:33 +01:00

ser_lt.v

Fix bugs and missing resets to pass formal

2018-12-11 22:05:32 +01:00

ser_shift.v

Fix width mismatches to make code verilator clean

2019-03-25 20:57:13 +01:00

serv_alu.v

Fix width mismatches to make code verilator clean

2019-03-25 20:57:13 +01:00

serv_bufreg.v

Fix width mismatches to make code verilator clean

2019-03-25 20:57:13 +01:00

serv_csr.v

Store CSR in RF RAM

2019-06-07 19:39:18 +02:00

serv_ctrl.v

Declare wires before use

2019-06-24 13:18:34 +02:00

serv_decode.v

Declare wires before use

2019-06-24 13:18:34 +02:00

serv_mem_if.v

Declare wires before use

2019-06-24 13:18:34 +02:00

serv_mpram.v

Add SERV_CLEAR_RAM parameter

2019-06-24 13:18:34 +02:00

serv_params.vh

Rewrite CSR selection

2019-01-10 18:15:20 +01:00

serv_regfile.v

Add SERV_CLEAR_RAM parameter

2019-06-24 13:18:34 +02:00

serv_top.v

Store CSR in RF RAM

2019-06-07 19:39:18 +02:00

shift_reg.v

Fix bugs and missing resets to pass formal

2018-12-11 22:05:32 +01:00