mirror of
https://github.com/open-simh/simtools.git
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Some floating point fixes.
- Fixed immediate source operand of LDEXP, LD[IL][FD] which is an integer, unlike several other FPP instructions. - Renamed floating point instruction formats so they match the instruction descriptions in the architecture handbook better.
This commit is contained in:
Olaf Seibert
parent
b9b61a4659
commit
22fdaedded
2
CHANGES
2
CHANGES
@ -1,5 +1,7 @@
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xx.xx.20xx: Rhialto
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version 0.8:
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- Fixed immediate source operand of LDEXP, LD[IL][FD]
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which is an integer, unlike several other FPP instructions.
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19.03.2021: Rhialto
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version 0.7:
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22
assemble.c
22
assemble.c
@ -1626,7 +1626,7 @@ static int assemble(
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* Handbook describes it as a destination, and MACRO11 V05.05 doesn't
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* allow a FP literal argument.
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*/
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case OC_FPPSRC:
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case OC_FPP_FSRC:
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/* One fp immediate or a general addressing mode */ {
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ADDR_MODE mode;
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unsigned word;
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@ -1644,16 +1644,24 @@ static int assemble(
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return CHECK_EOL;
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#endif
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case OC_FPPGENAC:
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case OC_FPP_SRCAC:
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case OC_FPP_FSRCAC:
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/* One gen and one reg 0-3 */ {
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ADDR_MODE mode;
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EX_TREE *value;
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unsigned reg;
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unsigned word;
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if (!get_fp_src_mode(cp, &cp, &mode)) {
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report(stack->top, "Invalid addressing mode (1st operand)\n");
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return 0;
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if ((op->flags & OC_MASK) == OC_FPP_FSRCAC) {
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if (!get_fp_src_mode(cp, &cp, &mode)) {
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report(stack->top, "Invalid addressing mode (1st operand, fsrc)\n");
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return 0;
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}
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} else {
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if (!get_mode(cp, &cp, &mode)) {
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report(stack->top, "Invalid addressing mode (1st operand)\n");
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return 0;
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}
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}
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cp = skipwhite(cp);
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@ -1684,8 +1692,8 @@ static int assemble(
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}
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return CHECK_EOL;
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case OC_FPPACGEN:
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/* One reg 0-3 and one gen */ {
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case OC_FPP_ACFDST:
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/* One reg 0-3 and one fdst */ {
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ADDR_MODE mode;
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EX_TREE *value;
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unsigned reg;
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76
symbols.c
76
symbols.c
@ -418,54 +418,54 @@ void add_symbols(
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add_sym("WRTLCK", I_WRTLCK, OC_1GEN, &instruction_section, &system_st);
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/* FPP instructions */
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add_sym("ABSD", I_ABSD, OC_FPPDST, &instruction_section, &system_st);
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add_sym("ABSF", I_ABSF, OC_FPPDST, &instruction_section, &system_st);
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add_sym("ADDD", I_ADDD, OC_FPPGENAC, &instruction_section, &system_st);
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add_sym("ADDF", I_ADDF, OC_FPPGENAC, &instruction_section, &system_st);
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add_sym("ABSD", I_ABSD, OC_FPP_FDST, &instruction_section, &system_st);
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add_sym("ABSF", I_ABSF, OC_FPP_FDST, &instruction_section, &system_st);
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add_sym("ADDD", I_ADDD, OC_FPP_FSRCAC, &instruction_section, &system_st);
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add_sym("ADDF", I_ADDF, OC_FPP_FSRCAC, &instruction_section, &system_st);
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add_sym("CFCC", I_CFCC, OC_NONE, &instruction_section, &system_st);
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add_sym("CLRD", I_CLRD, OC_FPPDST, &instruction_section, &system_st);
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add_sym("CLRF", I_CLRF, OC_FPPDST, &instruction_section, &system_st);
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add_sym("CMPD", I_CMPD, OC_FPPGENAC, &instruction_section, &system_st);
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add_sym("CMPF", I_CMPF, OC_FPPGENAC, &instruction_section, &system_st);
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add_sym("DIVD", I_DIVD, OC_FPPGENAC, &instruction_section, &system_st);
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add_sym("DIVF", I_DIVF, OC_FPPGENAC, &instruction_section, &system_st);
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add_sym("LDCDF", I_LDCDF, OC_FPPGENAC, &instruction_section, &system_st);
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add_sym("LDCFD", I_LDCFD, OC_FPPGENAC, &instruction_section, &system_st);
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add_sym("LDCID", I_LDCID, OC_FPPGENAC, &instruction_section, &system_st);
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add_sym("LDCIF", I_LDCIF, OC_FPPGENAC, &instruction_section, &system_st);
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add_sym("LDCLD", I_LDCLD, OC_FPPGENAC, &instruction_section, &system_st);
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add_sym("LDCLF", I_LDCLF, OC_FPPGENAC, &instruction_section, &system_st);
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add_sym("LDD", I_LDD, OC_FPPGENAC, &instruction_section, &system_st);
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add_sym("LDEXP", I_LDEXP, OC_FPPGENAC, &instruction_section, &system_st);
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add_sym("LDF", I_LDF, OC_FPPGENAC, &instruction_section, &system_st);
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add_sym("CLRD", I_CLRD, OC_FPP_FDST, &instruction_section, &system_st);
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add_sym("CLRF", I_CLRF, OC_FPP_FDST, &instruction_section, &system_st);
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add_sym("CMPD", I_CMPD, OC_FPP_FSRCAC, &instruction_section, &system_st);
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add_sym("CMPF", I_CMPF, OC_FPP_FSRCAC, &instruction_section, &system_st);
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add_sym("DIVD", I_DIVD, OC_FPP_FSRCAC, &instruction_section, &system_st);
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add_sym("DIVF", I_DIVF, OC_FPP_FSRCAC, &instruction_section, &system_st);
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add_sym("LDCDF", I_LDCDF, OC_FPP_FSRCAC, &instruction_section, &system_st);
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add_sym("LDCFD", I_LDCFD, OC_FPP_FSRCAC, &instruction_section, &system_st);
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add_sym("LDCID", I_LDCID, OC_FPP_SRCAC, &instruction_section, &system_st);
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add_sym("LDCIF", I_LDCIF, OC_FPP_SRCAC, &instruction_section, &system_st);
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add_sym("LDCLD", I_LDCLD, OC_FPP_SRCAC, &instruction_section, &system_st);
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add_sym("LDCLF", I_LDCLF, OC_FPP_SRCAC, &instruction_section, &system_st);
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add_sym("LDD", I_LDD, OC_FPP_FSRCAC, &instruction_section, &system_st);
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add_sym("LDEXP", I_LDEXP, OC_FPP_SRCAC, &instruction_section, &system_st);
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add_sym("LDF", I_LDF, OC_FPP_FSRCAC, &instruction_section, &system_st);
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add_sym("LDFPS", I_LDFPS, OC_1GEN, &instruction_section, &system_st);
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add_sym("MODD", I_MODD, OC_FPPGENAC, &instruction_section, &system_st);
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add_sym("MODF", I_MODF, OC_FPPGENAC, &instruction_section, &system_st);
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add_sym("MULD", I_MULD, OC_FPPGENAC, &instruction_section, &system_st);
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add_sym("MULF", I_MULF, OC_FPPGENAC, &instruction_section, &system_st);
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add_sym("NEGD", I_NEGD, OC_FPPDST, &instruction_section, &system_st);
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add_sym("NEGF", I_NEGF, OC_FPPDST, &instruction_section, &system_st);
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add_sym("MODD", I_MODD, OC_FPP_FSRCAC, &instruction_section, &system_st);
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add_sym("MODF", I_MODF, OC_FPP_FSRCAC, &instruction_section, &system_st);
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add_sym("MULD", I_MULD, OC_FPP_FSRCAC, &instruction_section, &system_st);
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add_sym("MULF", I_MULF, OC_FPP_FSRCAC, &instruction_section, &system_st);
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add_sym("NEGD", I_NEGD, OC_FPP_FDST, &instruction_section, &system_st);
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add_sym("NEGF", I_NEGF, OC_FPP_FDST, &instruction_section, &system_st);
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add_sym("SETD", I_SETD, OC_NONE, &instruction_section, &system_st);
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add_sym("SETF", I_SETF, OC_NONE, &instruction_section, &system_st);
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add_sym("SETI", I_SETI, OC_NONE, &instruction_section, &system_st);
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add_sym("SETL", I_SETL, OC_NONE, &instruction_section, &system_st);
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add_sym("STA0", I_STA0, OC_NONE, &instruction_section, &system_st);
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add_sym("STB0", I_STB0, OC_NONE, &instruction_section, &system_st);
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add_sym("STCDF", I_STCDF, OC_FPPACGEN, &instruction_section, &system_st);
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add_sym("STCDI", I_STCDI, OC_FPPACGEN, &instruction_section, &system_st);
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add_sym("STCDL", I_STCDL, OC_FPPACGEN, &instruction_section, &system_st);
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add_sym("STCFD", I_STCFD, OC_FPPACGEN, &instruction_section, &system_st);
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add_sym("STCFI", I_STCFI, OC_FPPACGEN, &instruction_section, &system_st);
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add_sym("STCFL", I_STCFL, OC_FPPACGEN, &instruction_section, &system_st);
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add_sym("STD", I_STD, OC_FPPACGEN, &instruction_section, &system_st);
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add_sym("STEXP", I_STEXP, OC_FPPACGEN, &instruction_section, &system_st);
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add_sym("STF", I_STF, OC_FPPACGEN, &instruction_section, &system_st);
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add_sym("STCDF", I_STCDF, OC_FPP_ACFDST, &instruction_section, &system_st);
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add_sym("STCDI", I_STCDI, OC_FPP_ACFDST, &instruction_section, &system_st);
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add_sym("STCDL", I_STCDL, OC_FPP_ACFDST, &instruction_section, &system_st);
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add_sym("STCFD", I_STCFD, OC_FPP_ACFDST, &instruction_section, &system_st);
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add_sym("STCFI", I_STCFI, OC_FPP_ACFDST, &instruction_section, &system_st);
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add_sym("STCFL", I_STCFL, OC_FPP_ACFDST, &instruction_section, &system_st);
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add_sym("STD", I_STD, OC_FPP_ACFDST, &instruction_section, &system_st);
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add_sym("STEXP", I_STEXP, OC_FPP_ACDST, &instruction_section, &system_st);
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add_sym("STF", I_STF, OC_FPP_ACFDST, &instruction_section, &system_st);
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add_sym("STFPS", I_STFPS, OC_1GEN, &instruction_section, &system_st);
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add_sym("STST", I_STST, OC_1GEN, &instruction_section, &system_st);
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add_sym("SUBD", I_SUBD, OC_FPPGENAC, &instruction_section, &system_st);
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add_sym("SUBF", I_SUBF, OC_FPPGENAC, &instruction_section, &system_st);
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add_sym("TSTD", I_TSTD, OC_FPPDST, &instruction_section, &system_st);
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add_sym("TSTF", I_TSTF, OC_FPPDST, &instruction_section, &system_st);
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add_sym("SUBD", I_SUBD, OC_FPP_FSRCAC, &instruction_section, &system_st);
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add_sym("SUBF", I_SUBF, OC_FPP_FSRCAC, &instruction_section, &system_st);
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add_sym("TSTD", I_TSTD, OC_FPP_FDST, &instruction_section, &system_st);
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add_sym("TSTF", I_TSTF, OC_FPP_FDST, &instruction_section, &system_st);
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/* The CIS instructions */
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add_sym("ADDNI", I_ADDN|I_CIS_I, OC_CIS3, &instruction_section, &system_st);
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25
symbols.h
25
symbols.h
@ -312,19 +312,22 @@ enum operand_codes { OC_MASK = 0xff00,
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/* FADD, FSUB, FMUL, FDIV, RTS */
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OC_SOB = 0x0800,
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/* SOB */
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OC_FPPGENAC = 0x0900,
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/* FPP (gen, floating ac 0-3) */
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OC_FPPACGEN = 0x0a00,
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/* FPP (floating ac 0-3, gen) */
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OC_FPPSRC = 0x0b00,
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/* FPP fp source: immediate or gen */
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OC_FPPDST = OC_1GEN,
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/* FPP general destination */
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OC_CIS2 = 0x0c00,
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OC_FPP_FSRCAC = 0x0900,
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/* FPP (fsrc gen, floating ac 0-3) */
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OC_FPP_SRCAC = 0x0a00,
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/* FPP (src gen, floating ac 0-3) */
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OC_FPP_ACFDST = 0x0b00,
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OC_FPP_ACDST = OC_FPP_ACFDST,
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/* FPP (floating ac 0-3, fdst gen) */
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/* OC_FPP_FSRC = 0x0c00, */
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/* FPP fp source: immediate or fsrc gen */
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OC_FPP_FDST = OC_1GEN,
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/* FPP fdst general destination */
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OC_CIS2 = 0x0d00,
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/* CIS with 2 parameter words */
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OC_CIS3 = 0x0d00,
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OC_CIS3 = 0x0e00,
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/* CIS with 3 parameter words */
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OC_CIS4 = 0x0e00,
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OC_CIS4 = 0x0f00,
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/* CIS with 4 parameter words */
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OC__LAST = 0xff00
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};
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@ -137,31 +137,74 @@
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114 000370 172227 041040 addf #^O41040,F2 ; taken literally
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115 000374 172127 040200 addf #1,ac1 ; as float
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116 000400 172127 040200 addf #1.,ac1 ; as float
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117 000404 172127 000001 addf #^D1,ac1 ; literally
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118 000410 172127 000002 addf #<1+1>,ac1 ; literally
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119 000414 172127 040300 addf #1.5,ac1 ; as float
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120 000420 172127 140263 addd #-1.4,ac1 ; as float
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121
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122 ; TODO: let parser check for junk at end of line
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test-float.mac:123: ***ERROR Junk at end of line ('5 ; bad: ')
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123 000424 170627 000002 absf #2.5 ; bad: operand is destination
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test-float.mac:124: ***ERROR Junk at end of line ('5 ; bad: ')
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124 000430 170527 000002 tstd #2.5 ; bad: operand is considered FDST by the arch handbook
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test-float.mac:125: ***ERROR Junk at end of line ('5 ; bad: junk')
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125 000434 174027 000002 stf ac0,#2.5 ; bad: junk at end of line
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126 000440 174027 000002 stf ac0,#2 ; doesn't makes sense but MACRO11 allows it
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127
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128
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129 .end
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129
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117 000404 172127 040200 addf #1.0,ac1 ; as float
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118 000410 172127 000001 addf #^D1,ac1 ; literally
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119 000414 173027 000001 subf #<1>,ac0 ; literally
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120 000420 172127 000002 addf #<1+1>,ac1 ; literally
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test-float.mac:121: ***ERROR Invalid addressing mode (1st operand, fsrc)
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121 subf #<1.0>,ac0 ; error
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122 000424 172127 040300 addf #1.5,ac1 ; as float
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123 000430 172127 140263 addd #-1.4,ac1 ; as float
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124 000434 173027 040200 subf #<^F 1.0>,ac0 ; as float
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test-float.mac:125: ***ERROR Invalid addressing mode (1st operand, fsrc)
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125 subf #<^D 1.0>,ac0 ; error
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126 000440 173027 000001 subf #<^D 1>,ac0 ; literally
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127 000444 173027 000002 subf #^D<1+1>,ac0 ; literally
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128 000450 173027 000002 subf #^D 1+1 ,ac0 ; literally
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129 000454 173027 042572 subf #1e3,ac0 ; as float
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test-float.mac:130: ***ERROR Invalid syntax (comma expected)
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130 subf #1e 3,ac0 ; TODO: accepted by MACRO11 as 1E3 (but not 1 e3, 1 e 3)
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131 000001 a = 1
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132 000003 e3 = 3
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133 000460 173027 000001 subf #a,ac0 ; a interpreted as bit pattern
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134 000464 173027 000001 subf #<a>,ac0 ; a interpreted as bit pattern
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135 000470 173027 000003 subf #e3,ac0 ; e3 is the label
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test-float.mac:136: ***ERROR Invalid addressing mode (1st operand, fsrc)
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136 subf #<1e3>,ac0 ; error N
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137
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test-float.mac:138: ***ERROR Junk at end of line ('5 ; bad: ')
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138 000474 170627 000002 absf #2.5 ; bad: operand is destination
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test-float.mac:139: ***ERROR Junk at end of line ('5 ; bad: ')
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139 000500 170527 000002 tstd #2.5 ; bad: operand is considered FDST by the arch handbook
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test-float.mac:140: ***ERROR Junk at end of line ('5 ; bad: junk')
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140 000504 174027 000002 stf ac0,#2.5 ; bad: junk at end of line
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141 000510 174027 000002 stf ac0,#2 ; doesn't makes sense but MACRO11 allows it
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142
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143 ; Test immediate source argument for instructions that have one (src or fsrc)
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144
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145 000514 172027 040200 addd #1,ac0 ; float
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146 000520 172027 040200 addf #1,ac0 ; float
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147 000524 173427 040200 cmpd #1,ac0 ; float
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148 000530 173427 040200 cmpf #1,ac0 ; float
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149 000534 174427 040200 divd #1,ac0 ; float
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150 000540 174427 040200 divf #1,ac0 ; float
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151 000544 177427 040200 ldcdf #1,ac0 ; float
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152 000550 177427 040200 ldcfd #1,ac0 ; float
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153 000554 177027 000001 ldcid #1,ac0 ; integer
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154 000560 177027 000001 ldcif #1,ac0 ; integer
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155 000564 177027 000001 ldcld #1,ac0 ; integer
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156 000570 177027 000001 ldclf #1,ac0 ; integer
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157 000574 172427 040200 ldd #1,ac0 ; float
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158 000600 172427 040200 ldf #1,ac0 ; float
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159 000604 176427 000001 ldexp #1,ac0 ; integer
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160 000610 171427 040200 modd #1,ac0 ; float
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161 000614 171427 040200 modf #1,ac0 ; float
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162 000620 171027 040200 muld #1,ac0 ; float
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163 000624 171027 040200 mulf #1,ac0 ; float
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164 000630 173027 040200 subd #1,ac0 ; float
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165 000634 173027 040200 subf #1,ac0 ; float
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166
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167 .end
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167
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Symbol table
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. ******R 001 AC0 =%000000 AC1 =%000001 F2 =%000002
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. ******R 001 AC0 =%000000 E3 = 000003
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A = 000001 AC1 =%000001 F2 =%000002
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Program sections:
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. ABS. 000000 000 (RW,I,GBL,ABS,OVR,NOSAV)
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000444 001 (RW,I,LCL,REL,CON,NOSAV)
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000640 001 (RW,I,LCL,REL,CON,NOSAV)
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@ -114,16 +114,54 @@ f2 = %2
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addf #^O41040,F2 ; taken literally
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addf #1,ac1 ; as float
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addf #1.,ac1 ; as float
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addf #1.0,ac1 ; as float
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addf #^D1,ac1 ; literally
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subf #<1>,ac0 ; literally
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addf #<1+1>,ac1 ; literally
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subf #<1.0>,ac0 ; error
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addf #1.5,ac1 ; as float
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addd #-1.4,ac1 ; as float
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subf #<^F 1.0>,ac0 ; as float
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subf #<^D 1.0>,ac0 ; error
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subf #<^D 1>,ac0 ; literally
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subf #^D<1+1>,ac0 ; literally
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subf #^D 1+1 ,ac0 ; literally
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subf #1e3,ac0 ; as float
|
||||
subf #1e 3,ac0 ; TODO: accepted by MACRO11 as 1E3 (but not 1 e3, 1 e 3)
|
||||
a = 1
|
||||
e3 = 3
|
||||
subf #a,ac0 ; a interpreted as bit pattern
|
||||
subf #<a>,ac0 ; a interpreted as bit pattern
|
||||
subf #e3,ac0 ; e3 is the label
|
||||
subf #<1e3>,ac0 ; error N
|
||||
|
||||
; TODO: let parser check for junk at end of line
|
||||
absf #2.5 ; bad: operand is destination
|
||||
tstd #2.5 ; bad: operand is considered FDST by the arch handbook
|
||||
stf ac0,#2.5 ; bad: junk at end of line
|
||||
stf ac0,#2 ; doesn't makes sense but MACRO11 allows it
|
||||
|
||||
; Test immediate source argument for instructions that have one (src or fsrc)
|
||||
|
||||
addd #1,ac0 ; float
|
||||
addf #1,ac0 ; float
|
||||
cmpd #1,ac0 ; float
|
||||
cmpf #1,ac0 ; float
|
||||
divd #1,ac0 ; float
|
||||
divf #1,ac0 ; float
|
||||
ldcdf #1,ac0 ; float
|
||||
ldcfd #1,ac0 ; float
|
||||
ldcid #1,ac0 ; integer
|
||||
ldcif #1,ac0 ; integer
|
||||
ldcld #1,ac0 ; integer
|
||||
ldclf #1,ac0 ; integer
|
||||
ldd #1,ac0 ; float
|
||||
ldf #1,ac0 ; float
|
||||
ldexp #1,ac0 ; integer
|
||||
modd #1,ac0 ; float
|
||||
modf #1,ac0 ; float
|
||||
muld #1,ac0 ; float
|
||||
mulf #1,ac0 ; float
|
||||
subd #1,ac0 ; float
|
||||
subf #1,ac0 ; float
|
||||
|
||||
.end
|
||||
|
||||
@ -118,9 +118,9 @@ test-operands.mac:75: ***ERROR Invalid addressing mode (2nd operand: register ex
|
||||
test-operands.mac:86: ***ERROR Junk at end of line (',ac1 ; bad
|
||||
')
|
||||
86 000112 171111 mulf (r1),ac1,ac1 ; bad
|
||||
test-operands.mac:87: ***ERROR Invalid addressing mode (1st operand)
|
||||
test-operands.mac:87: ***ERROR Invalid addressing mode (1st operand, fsrc)
|
||||
87 mulf ; bad
|
||||
test-operands.mac:88: ***ERROR Invalid addressing mode (1st operand)
|
||||
test-operands.mac:88: ***ERROR Invalid addressing mode (1st operand, fsrc)
|
||||
88 mulf ( ; bad
|
||||
test-operands.mac:89: ***ERROR Invalid syntax (comma expected)
|
||||
89 mulf (r1) ; bad
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user