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Commit Graph

23 Commits

Author SHA1 Message Date
Lars Asplund
07b89edd3c Setup CI.
Currently there are no testbenches provided with the project but the CI will still verify that each push and pull request to the project can be compiled. If/when tests are added they will also be executed with each push and PR.
2021-04-02 01:14:18 +02:00
Lars Asplund
8614f6800b Created VUnit run script.
VUnit performs dependency scanning to determine compile order. If an early compiled file has an used reference to a library for which no files have been compiled yet, that library is not recognized and leads to a compile error.
Such unused library reference have been removed.
2021-04-01 22:07:52 +02:00
Lars Asplund
fee9c135cc Added VHDL mocks for used UNIMACROs.
These mocks allow for a pure VHDL CI environment. The mocks are currently empty and provide no functionality. This is acceptable as long as no testbenches depend on them.
For now their primary purpose is to allow the project to be compiled by GHDL.

Some files also reference the UNISIM library. These references are not used and have been removed.
2021-03-13 22:54:24 +01:00
Lars Asplund
876f61a137 Removed type mismatch for recursive_synthesis attribute.
The attribute is defined as

attribute recursive_synthesis: boolean

but is frequently used with the integer value 1, for example

attribute recursive_synthesis of gate : function is 1;

These ones have been changed to true
2021-03-13 22:54:06 +01:00
openpowerwtf
d90fe419f6 Merge pull request #30 from openpowerwtf/master
A2L2_AXI updates
2020-10-01 17:06:51 -05:00
wtf
d74ff1d7c8 add rest of ld_queue_size changes from a2o 2020-10-01 17:27:22 -04:00
wtf
fc265d2448 updates for a2l2_axi 2020-10-01 12:58:20 -04:00
OpenPower Cores
11cb330995 Create a2_run_video.md 2020-09-14 19:22:31 -05:00
OpenPower Cores
4301c2e7a9 Create a2_build_video.md 2020-09-14 19:14:47 -05:00
openpowerwtf
08e7539f0a Merge pull request #12 from openpowerwtf/master
add comments
2020-08-28 10:18:46 -05:00
wtf
935fd41b8c add comments 2020-08-27 11:22:43 -04:00
Michael Neuling
b02fe50683 Merge pull request #10 from paulusmack/master
Add comments and clean up whitespace
2020-08-26 11:00:42 +10:00
Paul Mackerras
237bab9073 Add in selected comments from internal repository
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2020-08-25 11:58:35 +10:00
Paul Mackerras
6910c59944 Remove trailing carriage-return characters
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2020-08-25 11:58:06 +10:00
OpenPower Cores
65f5939ced Merge pull request #9 from olofk/fusesoc 2020-08-19 17:34:58 -05:00
Olof Kindgren
47c7f6a058 Add basic FuseSoC core description file
This is a basic core description file. It allows other FuseSoC
projects to depend on the a2i core and it defines a synth target
that can be used to run synthesis against different Xilinx devices.

If a2i is available to FuseSoC, the synthesis target can be run with

fusesoc run --target=synth a2i

In order to run synthesis against a specific device, add --part=<part>
as a core option, e.g.

fusesoc run --target=synth a2i --part=xc7a200tsbg484-1
2020-08-19 23:30:43 +02:00
Michael Neuling
8edbc6f2b8 Merge pull request #4 from tgingold/master
Translate off the unused global signals
2020-07-19 13:12:30 +10:00
Tristan Gingold
7e700ddc26 Translate off the unused global signals
So that a2x_axi can be imported into the open source yosys tool
using the ghdl frontend.

Signed-off-by: Tristan Gingold <tgingold@free.fr>
2020-07-18 21:20:59 +02:00
wtf
f270a43654 add attribute decls 2020-07-14 20:10:57 -04:00
Michael Neuling
826e092f03 Merge pull request #5 from mikey/dco
Add basic CONTRIBUTING.md
2020-07-08 09:02:38 +10:00
Michael Neuling
83f5907726 Add basic CONTRIBUTING.md
This adds a requirement that all contributed patches have the
Developer Certificate of Origin (ie a Signed-off-by)

Signed-off-by: Michael Neuling <mikey@neuling.org>
2020-07-08 08:57:31 +10:00
wtf
c54bbacfd9 remove latches,macros refs 2020-06-30 14:58:06 -04:00
wtf
7d9acfcad3 create 2020-06-28 18:40:39 -04:00