github.com/prirun.p50em
1
0
Fork 0
mirror of https://github.com/prirun/p50em.git synced 2026-02-26 08:13:56 +00:00
Code Issues Releases Wiki Activity

INCRP, ADDRP macros, code optimization

Browse Source 
added INCRP macro - now does 32-bit increments of RP for speed
added ADDRP macro to return RP incremented by n (CGT)
changed globals to static (didn't help speed much - thought it might)
moved around some functions
changed shift instructions to create bitmask at runtime (faster)
manually inlined mathexception (but used inline keyword in later revs)
This commit is contained in:
Jim
2007-08-25 00:00:00 -04:00
parent 8c0020d0dd
commit 7601dcb718
6 changed files with 532 additions and 502 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
ea32i.h
View File

@@ -1,6 +1,6 @@
#define IMM_EA 0x80000000
inline ea_t ea32i (ea_t earp, unsigned short inst, unsigned long *immu32, unsigned long long *immu64) {
static inline ea_t ea32i (ea_t earp, unsigned short inst, unsigned long *immu32, unsigned long long *immu64) {
int tm, sr, br, ring;
unsigned short d;

2
ea64v.h
View File

@@ -1,7 +1,7 @@
/* this version is derived from the flowchart in the preliminary P400
release notes */
inline ea_t ea64v (ea_t earp, unsigned short inst, short x, unsigned short *opcode) {
static inline ea_t ea64v (ea_t earp, unsigned short inst, short x, unsigned short *opcode) {
ea_t ea; /* full seg/word va */
unsigned short ea_s; /* eff address segno */

981
em.c
View File

File diff suppressed because it is too large Load Diff

1
emdev.h
View File

@@ -444,7 +444,6 @@ readasr:
savetraceflags = ~0;
} else {
TRACEA("\nTRACE DISABLED:\n\n");
dumpsegs();
savetraceflags = 0;
}
fflush(tracefile);

20
memtocrs.h Normal file
View File

@@ -0,0 +1,20 @@
/* define mapping between memory addresses and the current register set */
static unsigned short memtocrs[] = {
X, /* 0 = X */
A, /* 1 = A */
B, /* 2 = B */
Y, /* 3 = Y */
FLTH, /* 4 = FAC1/FLTH */
FLTL, /* 5 = FAC1/FLTL */
FEXP, /* 6 = FAC1/FEXP */
-1, /* 7 = PC (this is in the microcode scratch register set - TR7) */
32, /* 10 = unnamed */
FCODE, /* 11 = FCODE */
FADDR+1,/* 12 = FADDR (word) */
16, /* 13 = unnamed */
SBH, /* 14 = unnamed (SB seg) */
SBL, /* 15 = unnamed (SB word) */
LBH, /* 16 = unnamed (LB seg) */
LBL}; /* 17 = unnamed (LB word) */

28
regs.h
View File

@@ -84,7 +84,7 @@
#define FAC1 10
#define BR 12
union {
static union {
int rs[REGSETS][32];
unsigned short rs16[REGSETS][64];
@@ -133,7 +133,7 @@
#define RPH rpreg.s.rph
#define RPL rpreg.s.rpl
unsigned int grp; /* global RP for restore after longjmp */
static unsigned int grp; /* global RP for restore after longjmp */
register union {
struct {
unsigned short rph;
@@ -142,7 +142,7 @@ register union {
unsigned int ul;
} rpreg asm ("r29");
unsigned int *gcrsl; /* global crs pointer for restore after longjmp */
static unsigned int *gcrsl; /* global crs pointer for restore after longjmp */
register union {
short *i16;
unsigned short *u16;
@@ -162,7 +162,7 @@ register union {
#define grp RP /* turns grp assignments into dummies */
#define gcrsl crsl /* turns gcrsl assignments into dummies */
union {
static union {
short *i16;
unsigned short *u16;
int *i32;
@@ -175,26 +175,6 @@ union {
#define crs cr.u16
#define crsl cr.u32
/* define mapping between memory addresses and the current register set */
unsigned short memtocrs[] = {
X, /* 0 = X */
A, /* 1 = A */
B, /* 2 = B */
Y, /* 3 = Y */
FLTH, /* 4 = FAC1/FLTH */
FLTL, /* 5 = FAC1/FLTL */
FEXP, /* 6 = FAC1/FEXP */
-1, /* 7 = PC (this is in the microcode scratch register set - TR7) */
32, /* 10 = unnamed */
FCODE, /* 11 = FCODE */
FADDR+1,/* 12 = FADDR (word) */
16, /* 13 = unnamed */
SBH, /* 14 = unnamed (SB seg) */
SBL, /* 15 = unnamed (SB word) */
LBH, /* 16 = unnamed (LB seg) */
LBL}; /* 17 = unnamed (LB word) */
#define PCBLEV 0
#define PCBLINK 1
#define PCBWAIT 2