added IOTLB, mapio, and get/put16io macros so rev23 would boot
changed device drivers to go through IOTLB, not STLB
removed SVC Primos II emulation code
changed floating point register format to match memory
began PNC driver
put16r0 macro shortcuts like get16r0
branch instructions use inline code (macros) instead of gotos
devasr blocks when possible
lock disk files to prevent corruption from multiple emulators
devamlc select to ensure output socket buffer isn't full
devamlc partial write error is now a warning vs fatal
ECONNRESET test in devamlc (spurious emulator crashes)
lots of changes to PNC driver (not working yet)
added T_TERM for system terminal output tracing
added specific user tracing:
- 2-digit number after trace (user number)
- 6-digit octal number = OWNERL (for devices)
added specific procedure tracing
major bug in PCL: indirect bit offsets not working,
causing SAC JIM:PDALURW to be SAC JIM:PAUW
for R-mode MPY, do the math THEN generate the exception
DIV exception handling was wrong, code was wrong too
a few devasr changes
changed devamlc to always turn off parity instead of flipping it
writes tracing to a buffered log file instead of stderr
added clear of first 32K of physical memory to master clear
changed all exit() calls to fatal() calls
more changes to the devmt tape driver
need to restore interval timer when new process dispatched
process level was incorrect when new process dispatched
changes setting process abort flag in PCB when timer overflows
PX get/put must force R0 access for wait/ready list and PCB manipulations
restrict macro now accepts a program counter
get/put routines also accept a program counter (for ring #)
R-mode must use segment number in PBH for address calculations
more PCL work
more PX work
implemented direct ZCM
Primos load map handling to enhance traces
more PX/interrupt work
device initialization feature
standard/vectored interrupt handling
device polling
more C/L bit changes
work on BMxx instructions
lots of stupid work on JMP/JST - older DIAG routines are broken
tracing for address translation, disk I/O, and PCL
field address, field length, and load/store character instructions
queue instructions
more work on setting C & L bits correctly
added live register access flag to effective address calculations
first attempt at complete 64V address calculation
first RSAV/RRST, STAC/STLC, LPSW, LDLR/STLR, EIO
more shift instruction work
mem array is segment addressable
start of boot support
use CC macros and BCxx to emulate Bxyy (eg, BFLT)
use CC macros and LCxx to emulate Lxyy (eg, LFLT)
shift instruction work
