tracing for address translation, disk I/O, and PCL
field address, field length, and load/store character instructions
queue instructions
more work on setting C & L bits correctly
added live register access flag to effective address calculations
first attempt at complete 64V address calculation
first RSAV/RRST, STAC/STLC, LPSW, LDLR/STLR, EIO
more shift instruction work
mem array is segment addressable
start of boot support
use CC macros and BCxx to emulate Bxyy (eg, BFLT)
use CC macros and LCxx to emulate Lxyy (eg, LFLT)
shift instruction work