github.com/prirun.p50em
1
0
Fork 0
mirror of https://github.com/prirun/p50em.git synced 2026-01-30 13:06:33 +00:00
Code Issues Releases Wiki Activity
37 Commits 7 Branches 1 Tag
8f1833c8435afffc75be2c0a46f67b9950cd3bae
Commit Graph

31 Commits

Author SHA1 Message Date
Jim
8f1833c843 move instpermsec updating to devcp (clock device) 2007-02-22 00:00:00 -05:00
Jim
4b76c2ea1d changed fprintf(stderr... to TRACE macro 
writes tracing to a buffered log file instead of stderr
added clear of first 32K of physical memory to master clear
changed all exit() calls to fatal() calls
more changes to the devmt tape driver
 2007-02-18 00:00:00 -05:00
Jim
cad1dab3ee changed boot to handle tape devices, multiple disk controllers 
lots of changes to tape driver
added console log
 2007-02-15 00:00:00 -05:00
Jim
4703c0b8fd extensive changes to devmt tape controller emulation 
changed to use iget16 instead of get16 to fetch instructions
added test in notify for semaphore overflow - call fatal()
 2007-02-07 00:00:00 -05:00
Jim
55fc87a975 update instpermsec every 5 seconds to support varying host CPU speeds 
changes to support accurate real-time clock in devcp
changes to backstop idle instruction (BDX)
 2007-01-26 00:00:00 -05:00
Jim
292af061fc correct SSSN: actually an illegal shift opcode, add --nport option for PNC 2006-03-30 00:00:00 -05:00
Jim
03dedb4106 --tport option, support for physical queues (RTQ, ABQ) for DMQ (QAMLC) 2005-10-02 00:00:00 -04:00
Jim
09b9592915 WAIT register save shouldn't save all registers like PX does + 
need to restore interval timer when new process dispatched
process level was incorrect when new process dispatched
changes setting process abort flag in PCB when timer overflows
 2005-09-19 00:00:00 -04:00
Jim
e20a46e164 address trap changes, trace format change, added warn(), FP fixes 2005-09-12 00:00:00 -04:00
Jim
34e057b7b7 hacks for executing R-mode code in registers 
more PX work
reordered instructions (again!)
 2005-09-06 00:00:00 -04:00
Jim
c6a52800f0 32-bit page maps for access to more than 8MB of physical memory 
optimized ZMV
implemented LIOT, PTLB
optimized backstop BIX loop to just sleep instead
 2005-09-03 00:00:00 -04:00
Jim
5729bf7cc1 fault handling must force R0 access for concealed stack manipulations 
PX get/put must force R0 access for wait/ready list and PCB manipulations
restrict macro now accepts a program counter
get/put routines also accept a program counter (for ring #)
R-mode must use segment number in PBH for address calculations
more PCL work
more PX work
implemented direct ZCM
 2005-08-29 00:00:00 -04:00
Jim
42732b438e fault update 2005-08-26 00:00:00 -04:00
Jim
6146f076fc Enhanced load map routines to print nearest symbol 
Boots rev 20 (driveb) using --ss 14314, gets an uncorrected
disk read error, then hangs.
It also exhibits various failures in the file "fail".
 2005-08-25 00:00:00 -04:00
Jim
8c04dcdd8f STLB changes, ITLB instruction 2005-08-21 00:00:00 -04:00
Jim
99337af999 STLB added, boots rev20 up to DWRITE channel order 2005-08-19 00:00:00 -04:00
Jim
8648e7426b moved ea64v to an include file ea64v.h 
implemented stack extensions
more PCL/fault work
more PX work
more FP work
 2005-08-19 00:00:00 -04:00
Jim
b22a6c0e65 more PX, interrupt work, C/L/CC work 
on overflow, use mathexception to either set C or fault
 2005-07-31 00:00:00 -04:00
Jim
bbd311f048 more interrupt/fault work 
reordered switches to process more frequent instructions first
 2005-07-19 00:00:00 -04:00
Jim
7e68427b90 distinguish live register access in SR modes vs VI modes 
Primos load map handling to enhance traces
more PX/interrupt work
device initialization feature
standard/vectored interrupt handling
device polling
more C/L bit changes
work on BMxx instructions
lots of stupid work on JMP/JST - older DIAG routines are broken
 2005-07-11 00:00:00 -04:00
Jim
bdae5dede9 realtime clock, interrupts, process timer, LDC/STC, ZMV, ZMVD, ZFIL, PCL work 2005-06-25 00:00:00 -04:00
Jim
5ab1209f0a INCVA macro for segment wraparound, PX work, added --cpuid option 2005-06-16 00:00:00 -04:00
Jim
997332c487 first implementation of process exchange, WAIT, NFY + 
added restricted instruction checking
added CALF
more PCL work
 2005-06-13 00:00:00 -04:00
Jim
0b2994585c changed mem[] to be Prime physical memory array, removed direct references + 
more work on PCL
 2005-06-10 00:00:00 -04:00
Jim
22f4c22f8f virtual address translation, fault handling code + 
tracing for address translation, disk I/O, and PCL
field address, field length, and load/store character instructions
queue instructions
more work on setting C & L bits correctly
 2005-06-07 00:00:00 -04:00
Jim
c2c3e8f650 added trace feature and XEC instruction 2005-05-27 00:00:00 -04:00
Jim
3763da4cbe added live register access to memory get/put functions 
added live register access flag to effective address calculations
first attempt at complete 64V address calculation
first RSAV/RRST, STAC/STLC, LPSW, LDLR/STLR, EIO
more shift instruction work
 2005-05-24 00:00:00 -04:00
Jim
efc25712b5 defined register file with regs.h 
began using (get,put)16/32/64 functions to access memory instead of mem[]
began using crs[] to access current registers instead of mem[]
 2005-05-23 00:00:00 -04:00
Jim
655b35b0f9 added table of generic instructions to ignore & log 
initial disk controller support
began FP instruction work
 2005-04-23 00:00:00 -04:00
Jim
ff3fd68935 condition code macros 
mem array is segment addressable
start of boot support
use CC macros and BCxx to emulate Bxyy (eg, BFLT)
use CC macros and LCxx to emulate Lxyy (eg, LFLT)
shift instruction work
 2005-04-28 00:00:00 -04:00
Jim
ec56fd7a9e Initial version of Prime emulator for Mac OSX on PowerPC 2005-04-18 00:00:00 -04:00