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2fb2e1a348
changed EXPCL macro to set and clear bits - not just set changed shift instructions - made CLEARCL conditional; this means keys are only updated once per shift, not twice fixed prtn to update stack free pointer after values fetched in case a fault occurs and prtn is restarted changed prtn to invalidate brp cache only if ring changes changed prtn to inline, to avoid register save/restore changed argt to only update rp word offset in sf header added hack to pcl to correct wrapped RP for cpu.pcl case 42 added cgt inline proc, used in 2 places; generates better code (store to utempa is avoided altogether) added pimh (also used for pima) inline proc to avoid stores inlined invalidate_brp changed add16 implementation while looking at code generated ran faster according to Jeff's timers: 59/52 for old/new