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https://github.com/rcornwell/sims.git
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KA10: Updated to current sort of working code.
KI10 will now boot to login prompt. KA10 appears to be working correctly. 22Bit devices now working correctly.
This commit is contained in:
Richard Cornwell
parent
1a273eca6d
commit
222a105735
267
PDP10/ka10_cpu.c
267
PDP10/ka10_cpu.c
@ -158,7 +158,6 @@ char clk_en; /* Enable clock interrupts */
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int clk_irq; /* Clock interrupt */
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char pi_restore; /* Restore previous level */
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char pi_hold; /* Hold onto interrupt */
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int pi_cycle; /* Executing an interrupt */
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#if KI
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uint64 ARX; /* Extension to AR */
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uint64 BRX; /* Extension to BR */
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@ -264,11 +263,13 @@ MTAB cpu_mod[] = {
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{ UNIT_MSIZE, 8, "128K", "128K", &cpu_set_size },
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{ UNIT_MSIZE, 12, "196K", "196K", &cpu_set_size },
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{ UNIT_MSIZE, 16, "256K", "256K", &cpu_set_size },
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#if KI
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#if KI & KI_22BIT
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{ UNIT_MSIZE, 32, "512K", "512K", &cpu_set_size },
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{ UNIT_MSIZE, 64, "1024K", "1024K", &cpu_set_size },
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{ UNIT_MSIZE, 128, "2048K", "2048K", &cpu_set_size },
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{ UNIT_MSIZE, 256, "4096K", "4096K", &cpu_set_size },
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#endif
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#if KI
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{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "SERIAL", "SERIAL",
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&cpu_set_serial, &cpu_show_serial },
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#endif
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@ -718,10 +719,10 @@ t_stat dev_pag(uint32 dev, uint64 *data) {
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}
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if (res & SMASK) {
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ub_ptr = ((res >> 18) & 017777) << 9;
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user_addr_cmp = (res & 00020000000000LL) != 0;
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small_user = (res & 00040000000000LL) != 0;
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fm_sel = (res & 00300000000000LL) >> 29;
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}
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user_addr_cmp = (res & 00020000000000LL) != 0;
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small_user = (res & 00040000000000LL) != 0;
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fm_sel = (uint8)(res >> 29) & 060;
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sim_debug(DEBUG_DATAIO, &cpu_dev,
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"DATAO PAG %012llo ebr=%06o ubr=%06o\n",
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*data, eb_ptr, ub_ptr);
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@ -933,11 +934,11 @@ t_stat null_dev(uint32 dev, uint64 *data) {
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}
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#if KI
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int page_lookup(int addr, int flag, int *loc, int wr) {
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int page_lookup(int addr, int flag, int *loc, int wr, int fetch) {
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uint64 data;
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int base;
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int page = addr >> 9;
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int uf = 0;
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int uf = (FLAGS & USER) != 0;
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if (flag) {
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*loc = addr;
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@ -946,8 +947,7 @@ int page_lookup(int addr, int flag, int *loc, int wr) {
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if (page_fault)
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return 0;
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if (((FLAGS & USER) != 0) ||
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((xct_flag & 1) && ((wr == 0) || modify)) ||
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if (uf || ((xct_flag & 1) && !fetch && ((wr == 0) || modify)) ||
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((xct_flag & 2) && wr)) {
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base = ub_ptr;
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uf = 1;
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@ -985,13 +985,14 @@ int page_lookup(int addr, int flag, int *loc, int wr) {
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// fprintf(stderr, " -> %06llo wr=%o ", data, wr);
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*loc = ((data & 037777) << 9) + (addr & 0777);
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// fprintf(stderr, " -> %06o", *loc);
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if (!pi_cycle && ((FLAGS & PUBLIC) != 0) && ((data & 0200000) == 0)) {
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if (((FLAGS & PUBLIC) != 0) && ((data & 0200000) == 0)) {
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/* Handle public violation */
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fault_data = (((uint64)(page))<<18) | ((uint64)(uf) << 28) | 061LL;
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private_page = 1;
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// fprintf(stderr, " public");
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}
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public_access = (data & 0200000) != 0;
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if (fetch && ((data & 0200000) != 0))
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FLAGS |= PUBLIC;
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if ((data & LSIGN) == 0 || (wr & ((data & 0100000) == 0))) {
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fault_data = (((uint64)(page))<<18) | ((uint64)(uf) << 28) | 020LL;
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fault_data |= (data & 0400000) ? 010LL : 0LL; /* A */
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@ -1011,45 +1012,22 @@ int page_lookup(int addr, int flag, int *loc, int wr) {
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}
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uint64 get_reg(int reg) {
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if (FLAGS & USER) {
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if (FLAGS & USER)
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return FM[fm_sel|reg];
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} else if (xct_flag & 1) {
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if (FLAGS & USERIO) {
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if (fm_sel == 0) {
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int addr;
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if (page_lookup(reg, 0, &addr, 0))
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return M[addr];
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}
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return FM[fm_sel|reg];
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}
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return M[ub_ptr + ac_stack + reg];
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}
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return FM[reg];
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else
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return FM[reg];
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}
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void set_reg(int reg, uint64 value, int mem) {
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if (FLAGS & USER) {
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void set_reg(int reg, uint64 value) {
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if (FLAGS & USER)
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FM[fm_sel|reg] = value;
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} else if (((xct_flag & 1) && mem && modify) ||
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((xct_flag & 1) && !mem) || (xct_flag & 2)) {
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if (FLAGS & USERIO) {
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if (fm_sel == 0) {
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int addr;
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if (page_lookup(reg, 0, &addr, 1))
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M[addr] = value;
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} else
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FM[fm_sel|reg] = value;
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return;
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}
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M[ub_ptr + ac_stack + reg] = value;
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return;
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}
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FM[reg] = value;
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else
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FM[reg] = value;
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}
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#else
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int page_lookup(int addr, int flag, int *loc, int wr) {
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int page_lookup(int addr, int flag, int *loc, int wr, int fetch) {
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if (!flag && (FLAGS & USER) != 0) {
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if (addr <= ((Pl << 10) + 01777))
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*loc = (AB + (Rl << 10)) & RMASK;
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@ -1070,17 +1048,34 @@ int page_lookup(int addr, int flag, int *loc, int wr) {
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}
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#define get_reg(reg) FM[(reg) & 017]
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#define set_reg(reg, value, mem) FM[(reg) & 017] = value
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#define set_reg(reg, value) FM[(reg) & 017] = value
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#endif
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int Mem_read(int flag) {
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int Mem_read(int flag, int fetch) {
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int addr;
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if (AB < 020) {
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#if KI
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if (FLAGS & USER) {
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MB = get_reg(AB);
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return 0;
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} else if (xct_flag & 1 && !fetch) {
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if (FLAGS & USERIO) {
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if (fm_sel == 0)
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goto read;
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MB = FM[fm_sel|AB];
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return 0;
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}
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MB = M[ub_ptr + ac_stack + AB];
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return 0;
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}
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#endif
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MB = get_reg(AB);
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} else {
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int addr;
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read:
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sim_interval--;
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if (!page_lookup(AB, flag, &addr, 0))
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if (!page_lookup(AB, flag, &addr, 0, fetch))
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return 1;
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if (addr >= (int)MEMSIZE) {
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// fprintf(stderr, "NXM %06o read %06o\n\r", addr, PC);
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@ -1094,12 +1089,30 @@ int Mem_read(int flag) {
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}
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int Mem_write(int flag) {
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if (AB < 020)
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set_reg(AB, MB, 1);
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else {
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int addr;
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int addr;
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if (AB < 020) {
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#if KI
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if (FLAGS & USER) {
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set_reg(AB, MB);
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return 0;
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} else if (((xct_flag & 1) && modify) || (xct_flag & 2)) {
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if (FLAGS & USERIO) {
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if (fm_sel == 0)
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goto write;
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else
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FM[fm_sel|AB] = MB;
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return 0;
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}
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M[ub_ptr + ac_stack + AB] = MB;
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return 0;
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}
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#endif
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set_reg(AB, MB);
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} else {
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write:
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sim_interval--;
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if (!page_lookup(AB, flag, &addr, 1))
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if (!page_lookup(AB, flag, &addr, 1, 0))
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return 1;
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#if KI
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if (private_page)
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@ -1134,17 +1147,18 @@ int nlzero(uint64 w) {
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t_stat sim_instr (void)
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{
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t_stat reason;
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int f;
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int i_flags;
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int pi_rq;
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int pi_ov;
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int ind;
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int f_load_pc;
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int f_inst_fetch;
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int f_pc_inh;
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int nrf;
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int fxu_hold_set;
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int sac_inh;
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int i_flags; /* Instruction mode flags */
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int pi_rq; /* Interrupt request */
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int pi_ov; /* Overflow during PI cycle */
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int pi_cycle; /* Executing an interrupt */
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int ind; /* Indirect bit */
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int f_load_pc; /* Load AB from PC at start of instruction */
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int f_inst_fetch; /* Fetch new instruction */
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int f_pc_inh; /* Inhibit PC increment after instruction */
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int nrf; /* Normalize flag */
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int fxu_hold_set; /* Negitive exponent */
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int sac_inh; /* Inihibit saving AC after instruction */
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int f; /* Temporary variables */
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int flag1;
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int flag3;
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/* Restore register state */
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@ -1194,13 +1208,11 @@ fetch:
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private_page = 0;
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page_fault = 0;
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#endif
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Mem_read(pi_cycle | uuo_cycle);
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Mem_read(pi_cycle | uuo_cycle, 1);
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IR = (MB >> 27) & 0777;
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AC = (MB >> 23) & 017;
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i_flags = opflags[IR];
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#if KI
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if (public_access)
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FLAGS |= PUBLIC;
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FLAGS &= ~(TRP1|TRP2);
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#endif
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BYF5 = 0;
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@ -1213,14 +1225,14 @@ fetch:
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}
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/* Update history */
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if (hst_lnt) {
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if (hst_lnt && PC > 020 && (PC & 0777774) != 0472174) {
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hst_p = hst_p + 1;
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if (hst_p >= hst_lnt)
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hst_p = 0;
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hst[hst_p].pc = HIST_PC | ((BYF5)? (HIST_PC2|PC) : AB);
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hst[hst_p].ea = AB;
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hst[hst_p].ir = MB;
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hst[hst_p].flags = (FLAGS << 4) |(clk_flg << 3) |(mem_prot << 2) |
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hst[hst_p].flags = (FLAGS << 5) |(clk_flg << 3) |(mem_prot << 2) |
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(nxm_flag << 1) | (push_ovf);
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hst[hst_p].ac = get_reg(AC);
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}
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@ -1240,7 +1252,7 @@ fetch:
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if (IR != 0254)
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AR &= RMASK;
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if (ind & !pi_rq)
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if (Mem_read(pi_cycle | uuo_cycle))
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if (Mem_read(pi_cycle | uuo_cycle, 0))
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goto last;
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/* Handle events during a indirect loop */
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if (sim_interval-- <= 0) {
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@ -1284,7 +1296,7 @@ fetch_opr:
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#if KI
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modify = 1;
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#endif
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if (Mem_read(0))
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if (Mem_read(0, 0))
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goto last;
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AR = MB;
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}
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@ -1349,7 +1361,7 @@ unasign:
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AB |= 2;
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if (FLAGS & USER)
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AB |= 4;
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Mem_read(uuo_cycle);
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Mem_read(uuo_cycle, 0);
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FLAGS = (MB >> 23) & 017777;
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PC = MB & RMASK;
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f_pc_inh = 1;
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@ -1393,14 +1405,14 @@ unasign:
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/* AR,MQ = AC BR,MB = mem */
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/* AR High */
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AB = (AB + 1) & RMASK;
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if (Mem_read(0))
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if (Mem_read(0, 0))
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goto last;
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SC = GET_EXPO(BR);
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BR = SMEAR_SIGN(BR);
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SMEAR_SIGN(BR);
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BR <<= 35;
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BR |= MB & CMASK;
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FE = GET_EXPO(AR);
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AR = SMEAR_SIGN(AR);
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SMEAR_SIGN(AR);
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AR <<= 35;
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AR |= (MQ & CMASK);
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if (IR & 01) {
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@ -1480,14 +1492,14 @@ dpnorm:
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/* AR,MQ = AC BR,MB = mem */
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/* AR High */
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AB = (AB + 1) & RMASK;
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if (Mem_read(0))
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if (Mem_read(0, 0))
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goto last;
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SC = GET_EXPO(AR);
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AR = SMEAR_SIGN(AR);
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SMEAR_SIGN(AR);
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AR <<= 35;
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AR |= (MQ & CMASK);
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FE = GET_EXPO(BR);
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BR = SMEAR_SIGN(BR);
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SMEAR_SIGN(BR);
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BR <<= 35;
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BR |= MB & CMASK;
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flag1 = 0;
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@ -1517,14 +1529,14 @@ dpnorm:
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/* AR,MQ = AC BR,MB = mem */
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/* AR High */
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AB = (AB + 1) & RMASK;
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if (Mem_read(0))
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if (Mem_read(0, 0))
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goto last;
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SC = GET_EXPO(AR);
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AR = SMEAR_SIGN(AR);
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SMEAR_SIGN(AR);
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AR <<= 35;
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AR |= (MQ & CMASK);
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FE = GET_EXPO(BR);
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BR = SMEAR_SIGN(BR);
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SMEAR_SIGN(BR);
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BR <<= 35;
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BR |= MB & CMASK;
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flag1 = 0;
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@ -1576,14 +1588,14 @@ dpnorm:
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case 0120: /* DMOVE */
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AB = (AB + 1) & RMASK;
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if (Mem_read(0))
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if (Mem_read(0, 0))
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goto last;
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MQ = MB;
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break;
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case 0121: /* DMOVN */
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AB = (AB + 1) & RMASK;
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if (Mem_read(0))
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if (Mem_read(0, 0))
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goto last;
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MQ = ((MB & CMASK) ^ CMASK) + 1; /* Low */
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/* High */
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@ -1747,7 +1759,7 @@ unasign:
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SC = (SC + 1) & 0777;
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}
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AR &= MQ;
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set_reg(AC, AR, 0);
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set_reg(AC, AR);
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} else {
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BR = MB;
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AR = get_reg(AC) & MQ;
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@ -1949,7 +1961,7 @@ fxnorm:
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/* Handle UFA */
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if (IR == 0130) {
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set_reg((AC + 1) & 017, AR, 0);
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set_reg((AC + 1) & 017, AR);
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break;
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}
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break;
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@ -2173,7 +2185,7 @@ fxnorm:
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check_apr_irq();
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}
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#if KI
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if (AR == SMASK & !pi_cycle)
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if (AR == SMASK && !pi_cycle)
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FLAGS |= TRP1;
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#endif
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AR = AD & FMASK;
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@ -2414,7 +2426,7 @@ div:
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f_pc_inh = 1;
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SC = nlzero(AR);
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}
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set_reg(AC + 1, SC, 0);
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set_reg(AC + 1, SC);
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break;
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case 0244: /* ASHC */
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@ -2512,34 +2524,34 @@ div:
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/* Branch */
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case 0250: /* EXCH */
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set_reg(AC, BR, 0);
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set_reg(AC, BR);
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break;
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case 0251: /* BLT */
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BR = AB;
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do {
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if (sim_interval <= 0) {
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sim_process_event();
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}
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/* Allow for interrupt */
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if (pi_enable && pi_pending) {
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if (sim_interval <= 0) {
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sim_process_event();
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}
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/* Allow for interrupt */
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if (pi_enable && pi_pending) {
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pi_rq = check_irq_level();
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if (pi_rq) {
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f_pc_inh = 1;
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f_load_pc = 0;
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f_inst_fetch = 0;
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set_reg(AC, AR, 0);
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break;
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f_pc_inh = 1;
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f_load_pc = 0;
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f_inst_fetch = 0;
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set_reg(AC, AR);
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break;
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}
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}
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AB = (AR >> 18) & RMASK;
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if (Mem_read(0))
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break;
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AB = (AR & RMASK);
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if (Mem_write(0))
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break;
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AD = (AR & RMASK) + CM(BR) + 1;
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AR = (AR + 01000001LL);
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}
|
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AB = (AR >> 18) & RMASK;
|
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if (Mem_read(0, 0))
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break;
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AB = (AR & RMASK);
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if (Mem_write(0))
|
||||
break;
|
||||
AD = (AR & RMASK) + CM(BR) + 1;
|
||||
AR = AOB(AR);
|
||||
} while ((AD & C1) == 0);
|
||||
break;
|
||||
|
||||
@ -2652,8 +2664,8 @@ div:
|
||||
break;
|
||||
}
|
||||
}
|
||||
AB = AR + (f >> 1);
|
||||
if (Mem_read(0))
|
||||
AB = (AR + (f >> 1)) & RMASK;
|
||||
if (Mem_read(0, 0))
|
||||
goto last;
|
||||
AR = MB;
|
||||
if ((f & 1) == 0)
|
||||
@ -2679,7 +2691,7 @@ div:
|
||||
MB = ((uint64)(FLAGS) << 23) | ((PC + !pi_cycle) & RMASK);
|
||||
FLAGS &= ~ (BYTI|ADRFLT|TRP2|TRP1);
|
||||
if (uuo_cycle | pi_cycle) {
|
||||
FLAGS &= ~USER; /* Clear USER */
|
||||
FLAGS &= ~(USER|PUBLIC); /* Clear USER */
|
||||
}
|
||||
Mem_write(uuo_cycle | pi_cycle);
|
||||
PC = BR & RMASK;
|
||||
@ -2705,7 +2717,7 @@ div:
|
||||
|
||||
case 0262: /* POP */
|
||||
AB = AR & RMASK;
|
||||
if (Mem_read(0))
|
||||
if (Mem_read(0, 0))
|
||||
goto last;
|
||||
AR = SOB(AR);
|
||||
AB = BR & RMASK;
|
||||
@ -2724,7 +2736,7 @@ div:
|
||||
|
||||
case 0263: /* POPJ */
|
||||
AB = AR & RMASK;
|
||||
if (Mem_read(0))
|
||||
if (Mem_read(0, 0))
|
||||
goto last;
|
||||
PC = MB & RMASK;
|
||||
AR = SOB(AR);
|
||||
@ -2743,9 +2755,13 @@ div:
|
||||
case 0264: /* JSR */ /* AR Frm PC */
|
||||
AD = ((uint64)(FLAGS) << 23) |
|
||||
((PC + !pi_cycle) & RMASK);
|
||||
#if KI
|
||||
// FLAGS &= ~ 0420;
|
||||
#else
|
||||
FLAGS &= ~ 0434;
|
||||
#endif
|
||||
if (uuo_cycle | pi_cycle) {
|
||||
FLAGS &= ~USER; /* Clear USER */
|
||||
FLAGS &= ~(USER|PUBLIC); /* Clear USER */
|
||||
}
|
||||
PC = (AR + pi_cycle) & RMASK;
|
||||
AR = AD;
|
||||
@ -2754,9 +2770,13 @@ div:
|
||||
case 0265: /* JSP */ /* AR Frm PC */
|
||||
AD = ((uint64)(FLAGS) << 23) |
|
||||
((PC + !pi_cycle) & RMASK);
|
||||
#if KI
|
||||
// FLAGS &= ~ 0420;
|
||||
#else
|
||||
FLAGS &= ~ 0434;
|
||||
#endif
|
||||
if (uuo_cycle | pi_cycle) {
|
||||
FLAGS &= ~USER; /* Clear USER */
|
||||
FLAGS &= ~(USER|PUBLIC); /* Clear USER */
|
||||
}
|
||||
PC = AR & RMASK;
|
||||
AR = AD;
|
||||
@ -2764,9 +2784,9 @@ div:
|
||||
break;
|
||||
|
||||
case 0266: /* JSA */ /* AR Frm PC */
|
||||
set_reg(AC, (AR << 18) | ((PC + 1) & RMASK), 0);
|
||||
set_reg(AC, (AR << 18) | ((PC + 1) & RMASK));
|
||||
if (uuo_cycle | pi_cycle) {
|
||||
FLAGS &= ~USER; /* Clear USER */
|
||||
FLAGS &= ~(USER|PUBLIC); /* Clear USER */
|
||||
}
|
||||
PC = AR & RMASK;
|
||||
AR = BR;
|
||||
@ -2774,10 +2794,10 @@ div:
|
||||
|
||||
case 0267: /* JRA */
|
||||
AD = AB; /* Not in hardware */
|
||||
AB = (get_reg(AC) >> 18) & RMASK;
|
||||
if (Mem_read(uuo_cycle | pi_cycle))
|
||||
AB = (get_reg(AC) >> 18, 0) & RMASK;
|
||||
if (Mem_read(uuo_cycle | pi_cycle, 0))
|
||||
goto last;
|
||||
set_reg(AC, MB, 0);
|
||||
set_reg(AC, MB);
|
||||
PC = AD & RMASK;
|
||||
f_pc_inh = 1;
|
||||
break;
|
||||
@ -3284,7 +3304,7 @@ test_op:
|
||||
switch(AC & 07) {
|
||||
case 0: /* 00 BLKI */
|
||||
case 2: /* 10 BLKO */
|
||||
if (Mem_read(pi_cycle))
|
||||
if (Mem_read(pi_cycle, 0))
|
||||
break;
|
||||
AR = MB;
|
||||
if (hst_lnt) {
|
||||
@ -3312,7 +3332,7 @@ test_op:
|
||||
Mem_write(pi_cycle);
|
||||
break;
|
||||
case 3: /* 14 DATAO */
|
||||
if (Mem_read(pi_cycle))
|
||||
if (Mem_read(pi_cycle, 0))
|
||||
break;
|
||||
AR = MB;
|
||||
dev_tab[d](DATAO|(d<<2), &AR);
|
||||
@ -3347,10 +3367,10 @@ test_op:
|
||||
goto last;
|
||||
}
|
||||
if (!sac_inh && ((i_flags & SAC) || ((i_flags & SACZ) && AC != 0)))
|
||||
set_reg(AC, AR, 0); /* blank, I, B */
|
||||
set_reg(AC, AR); /* blank, I, B */
|
||||
|
||||
if (!sac_inh && (i_flags & SAC2))
|
||||
set_reg((AC+1) & 017, MQ, 0);
|
||||
set_reg((AC+1) & 017, MQ);
|
||||
|
||||
if (hst_lnt) {
|
||||
hst[hst_p].fmb = AR;
|
||||
@ -3364,7 +3384,6 @@ last:
|
||||
if (page_enable && (page_fault || private_page || (FLAGS & (TRP1|TRP2)))) {
|
||||
f_pc_inh = 1;
|
||||
f_load_pc = 0;
|
||||
uuo_cycle = 1;
|
||||
trap_flag = 1;
|
||||
if (page_fault || private_page) {
|
||||
page_fault = private_page = 0;
|
||||
@ -3372,13 +3391,13 @@ last:
|
||||
inout_fail = 1;
|
||||
AB = ub_ptr + (FLAGS & USER) ? 0427 : 0426;
|
||||
MB = fault_data;
|
||||
Mem_write(uuo_cycle);
|
||||
Mem_write(1);
|
||||
AB = 0420;
|
||||
} else {
|
||||
AB = 0420 + ((FLAGS & (TRP1|TRP2)) >> 2);
|
||||
}
|
||||
AB += (FLAGS & USER) ? ub_ptr : eb_ptr;
|
||||
fprintf(stderr, "Trap %06o\n\r", AB);
|
||||
//fprintf(stderr, "Trap %06o\n\r", AB);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
@ -43,7 +43,7 @@
|
||||
#endif
|
||||
|
||||
#ifndef KI_22BIT
|
||||
#define KI_22BIT 0
|
||||
#define KI_22BIT KI
|
||||
#endif
|
||||
|
||||
/* Digital Equipment Corporation's 36b family had six implementations:
|
||||
@ -104,32 +104,32 @@ extern DEBTAB dev_debug[];
|
||||
#define Q_IDLE (sim_idle_enab)
|
||||
|
||||
/* Device information block */
|
||||
#define LMASK 00777777000000LL
|
||||
#define RMASK 00000000777777LL
|
||||
#define FMASK 00777777777777LL
|
||||
#define CMASK 00377777777777LL
|
||||
#define SMASK 00400000000000LL
|
||||
#define C1 01000000000000LL
|
||||
#define LSIGN 00000000400000LL
|
||||
#define PMASK 00007777777777LL
|
||||
#define XMASK 03777777777777LL
|
||||
#define EMASK 00777000000000LL
|
||||
#define MMASK 00000777777777LL
|
||||
#define BIT1 00200000000000LL
|
||||
#define BIT8 00001000000000LL
|
||||
#define BIT9 00000400000000LL
|
||||
#define BIT10_35 0000377777777LL
|
||||
#define MANT 00000777777777LL
|
||||
#define EXPO 00377000000000LL
|
||||
#define DFMASK 01777777777777777777777LL
|
||||
#define DSMASK 01000000000000000000000LL
|
||||
#define DCMASK 0777777777777777777777LL
|
||||
#define DNMASK 0400000000000000000000LL
|
||||
#define DXMASK 0200000000000000000000LL
|
||||
#define FPSMASK 040000000000000000000LL
|
||||
#define FPNMASK 01000000000000000000LL
|
||||
#define FPFMASK 077777777777777777777LL
|
||||
#define FPCMASK 000777777777777777777LL
|
||||
#define LMASK 00777777000000LL
|
||||
#define RMASK 00000000777777LL
|
||||
#define FMASK 00777777777777LL
|
||||
#define CMASK 00377777777777LL
|
||||
#define SMASK 00400000000000LL
|
||||
#define C1 01000000000000LL
|
||||
#define LSIGN 00000000400000LL
|
||||
#define PMASK 00007777777777LL
|
||||
#define XMASK 03777777777777LL
|
||||
#define EMASK 00777000000000LL
|
||||
#define MMASK 00000777777777LL
|
||||
#define BIT1 00200000000000LL
|
||||
#define BIT8 00001000000000LL
|
||||
#define BIT9 00000400000000LL
|
||||
#define BIT10_35 00000377777777LL
|
||||
#define MANT 00000777777777LL
|
||||
#define EXPO 00377000000000LL
|
||||
#define DFMASK 01777777777777777777777LL
|
||||
#define DSMASK 01000000000000000000000LL
|
||||
#define DCMASK 00777777777777777777777LL
|
||||
#define DNMASK 00400000000000000000000LL
|
||||
#define DXMASK 00200000000000000000000LL
|
||||
#define FPSMASK 00040000000000000000000LL
|
||||
#define FPNMASK 00001000000000000000000LL
|
||||
#define FPFMASK 00077777777777777777777LL
|
||||
#define FPCMASK 00000777777777777777777LL
|
||||
|
||||
#define CM(x) (FMASK ^ (x))
|
||||
|
||||
@ -161,6 +161,7 @@ extern DEBTAB dev_debug[];
|
||||
#define TRP1 000004
|
||||
#define TRP2 000010
|
||||
#define ADRFLT 000020
|
||||
//#define PUBLIC 000000
|
||||
#define PUBLIC 000040
|
||||
#else
|
||||
#define TRP1 000000
|
||||
|
||||
@ -60,37 +60,37 @@
|
||||
|
||||
|
||||
/* CONI/CONO Flags */
|
||||
#define SUF_ERR 0000000000100
|
||||
#define SEC_ERR 0000000000200
|
||||
#define ILL_CMD 0000000000400
|
||||
#define ILL_WR 0000000001000
|
||||
#define NOT_RDY 0000000002000 /* Clear CXR */
|
||||
#define PRT_ERR 0000000004000 /* 14-17 Clear CCPE, DSPE, DISK WDPE, CDPE */
|
||||
#define NXM_ERR 0000000010000
|
||||
#define SLW_CHN 0000000020000
|
||||
#define SRC_ERR 0000000040000
|
||||
#define PWR_FAIL_10 0000000100000
|
||||
#define END_CYL 0000000200000 /* No effect */
|
||||
#define SRC_DONE 0000000400000 /* No effect */
|
||||
#define DSK_PRTY 0000001000000 /* No effect */
|
||||
#define CHN_PRTY 0000002000000 /* No effect */
|
||||
#define SEC_PRTY 0000004000000 /* No effect */
|
||||
#define CCW_PRTY 0000010000000 /* No effect */
|
||||
#define B22_FLAG
|
||||
#define SUF_ERR 0000000000100LL
|
||||
#define SEC_ERR 0000000000200LL
|
||||
#define ILL_CMD 0000000000400LL
|
||||
#define ILL_WR 0000000001000LL
|
||||
#define NOT_RDY 0000000002000LL /* Clear CXR */
|
||||
#define PRT_ERR 0000000004000LL /* 14-17 Clear CCPE, DSPE, DISK WDPE, CDPE */
|
||||
#define NXM_ERR 0000000010000LL
|
||||
#define SLW_CHN 0000000020000LL
|
||||
#define SRC_ERR 0000000040000LL
|
||||
#define PWR_FAIL_10 0000000100000LL
|
||||
#define END_CYL 0000000200000LL /* No effect */
|
||||
#define SRC_DONE 0000000400000LL /* No effect */
|
||||
#define DSK_PRTY 0000001000000LL /* No effect */
|
||||
#define CHN_PRTY 0000002000000LL /* No effect */
|
||||
#define SEC_PRTY 0000004000000LL /* No effect */
|
||||
#define CCW_PRTY 0000010000000LL /* No effect */
|
||||
#define B22_FLAG 0000020000000LL
|
||||
|
||||
#define CLRMSK 0000000177710
|
||||
#define CLRMSK2 0000176000000
|
||||
#define CLRMSK 0000000177710LL
|
||||
#define CLRMSK2 0000176000000LL
|
||||
|
||||
/* DATAI/DATAO */
|
||||
#define DWPE_STOP 0000000001000
|
||||
#define SPARE 0000000002000
|
||||
#define DSPE_STOP 0000000004000
|
||||
#define SECTOR 0000000170000
|
||||
#define CYL256 0000000200000
|
||||
#define SURFACE 0000017400000
|
||||
#define CYL 0007760000000
|
||||
#define DRIVE 0070000000000
|
||||
#define OP 0700000000000
|
||||
#define DWPE_STOP 0000000001000LL
|
||||
#define SPARE 0000000002000LL
|
||||
#define DSPE_STOP 0000000004000LL
|
||||
#define SECTOR 0000000170000LL
|
||||
#define CYL256 0000000200000LL
|
||||
#define SURFACE 0000017400000LL
|
||||
#define CYL 0007760000000LL
|
||||
#define DRIVE 0070000000000LL
|
||||
#define OP 0700000000000LL
|
||||
|
||||
#define RD 0
|
||||
#define WR 1
|
||||
@ -101,21 +101,21 @@
|
||||
#define NO 6
|
||||
#define RC 7
|
||||
|
||||
#define ATTN 0000000000776
|
||||
#define DEFECT 0000000001000
|
||||
#define SEL_RP03 0000000002000
|
||||
#define SEL_CYL256 0000000004000
|
||||
#define SEL_SPARE 0000000010000
|
||||
#define SEL_SEC 0000000760000
|
||||
#define WR_HD_LK 0000001000000
|
||||
#define RD_ONLY 0000002000000
|
||||
#define NO_DRIVE 0000004000000
|
||||
#define FILE_UNSAFE 0000010000000
|
||||
#define DRV_ONLINE 0000020000000
|
||||
#define ON_CYL 0000040000000
|
||||
#define SEEK_INC 0000100000000
|
||||
#define SEL_CYL 0077600000000
|
||||
#define SEL_DRIVE 0700000000000
|
||||
#define ATTN 0000000000776LL
|
||||
#define DEFECT 0000000001000LL
|
||||
#define SEL_RP03 0000000002000LL
|
||||
#define SEL_CYL256 0000000004000LL
|
||||
#define SEL_SPARE 0000000010000LL
|
||||
#define SEL_SEC 0000000760000LL
|
||||
#define WR_HD_LK 0000001000000LL
|
||||
#define RD_ONLY 0000002000000LL
|
||||
#define NO_DRIVE 0000004000000LL
|
||||
#define FILE_UNSAFE 0000010000000LL
|
||||
#define DRV_ONLINE 0000020000000LL
|
||||
#define ON_CYL 0000040000000LL
|
||||
#define SEEK_INC 0000100000000LL
|
||||
#define SEL_CYL 0077600000000LL
|
||||
#define SEL_DRIVE 0700000000000LL
|
||||
|
||||
#define RP01_DTYPE 0
|
||||
#define RP01_SECT 5
|
||||
@ -337,12 +337,12 @@ t_stat dp_devio(uint32 dev, uint64 *data) {
|
||||
uptr = &dp_unit[(ctlr * NUM_UNITS_DP) + unit];
|
||||
switch(dev & 3) {
|
||||
case CONI:
|
||||
*data = df10->status | uptr->STATUS;
|
||||
#if KI10_22BIT
|
||||
*data = (uint64)(df10->status | uptr->STATUS);
|
||||
#if KI_22BIT
|
||||
*data |= B22_FLAG;
|
||||
#endif
|
||||
sim_debug(DEBUG_CONI, dptr, "DP %03o CONI %06o %d PC=%o\n", dev,
|
||||
(uint32)*data, ctlr, PC);
|
||||
sim_debug(DEBUG_CONI, dptr, "DP %03o CONI %012llo %d PC=%o\n", dev,
|
||||
*data, ctlr, PC);
|
||||
return SCPE_OK;
|
||||
|
||||
case CONO:
|
||||
|
||||
@ -257,7 +257,7 @@ t_stat mt_devio(uint32 dev, uint64 *data) {
|
||||
res = status;
|
||||
if ((dptr->flags & MTDF_MOTION) == 0)
|
||||
res |= IDLE_UNIT;
|
||||
#if KI10_22BIT
|
||||
#if KI_22BIT
|
||||
res |= B22_FLAG;
|
||||
#endif
|
||||
*data = res;
|
||||
|
||||
@ -52,39 +52,38 @@
|
||||
#define UFLAGS u5 /* Function */
|
||||
|
||||
|
||||
#define DISK_SEL 0600000000000
|
||||
#define TRACK 0177600000000
|
||||
#define SEGMENT 0000177000000
|
||||
#define INIT_PAR 0000000770000 // Read
|
||||
#define DPE_STOP 0000000004000
|
||||
#define CPE_STOP 0000000002000
|
||||
#define WRITE 0000000001000
|
||||
#define ICWA 0000000000776
|
||||
#define EPAR 0000000000001
|
||||
#define SEC_SEL 0000000001400 // Read
|
||||
#define SECT_CNT 0000000000377 // Read
|
||||
#define DISK_SEL 0600000000000LL
|
||||
#define TRACK 0177600000000LL
|
||||
#define SEGMENT 0000177000000LL
|
||||
#define INIT_PAR 0000000770000LL /* Read */
|
||||
#define DPE_STOP 0000000004000LL
|
||||
#define CPE_STOP 0000000002000LL
|
||||
#define WRITE 0000000001000LL
|
||||
#define EPAR 0000000000001LL
|
||||
#define SEC_SEL 0000000001400LL /* Read */
|
||||
#define SECT_CNT 0000000000377LL /* Read */
|
||||
|
||||
#define PI 0000007
|
||||
#define WCW 0000040
|
||||
#define SEC_SCTR 0600000
|
||||
|
||||
#define RST_MSK 0000000177710 /* CONO reset bits */
|
||||
#define B22_FLAG 0040000000000 /* 22 bit controller. */
|
||||
#define MAINT_SEG 0010000000000
|
||||
#define PRTLT 0004000000000 /* Protected area less then bounds */
|
||||
#define STS 0003777000000
|
||||
#define SCRCHCMP 0000000400000 /* Tranfer in progress. */
|
||||
#define S_ERROR 0000000200000 /* Segment not found */
|
||||
#define DSK_DES_E 0000000100000 /* Duplicate disk */
|
||||
#define TRK_SEL_E 0000000040000 /* Track not BCD number */
|
||||
#define NOT_RDY 0000000020000 /* Drive not ready */
|
||||
#define PSW_FAIL 0000000010000 /* Power supply fail */
|
||||
#define DSK_PAR_E 0000000004000 /* Disk Parity Error */
|
||||
#define CH_PAR_D 0000000002000 /* Channel Data Parity Error */
|
||||
#define CH_PAR_C 0000000001000 /* Channel Control Parity Error */
|
||||
#define NXM_ERR 0000000000400 /* Non existant memory */
|
||||
#define ILL_WR 0000000000200 /* Write to protected area */
|
||||
#define OVRRUN 0000000000100 /* Over run */
|
||||
#define RST_MSK 0000000177710LL /* CONO reset bits */
|
||||
#define B22_FLAG 0040000000000LL /* 22 bit controller. */
|
||||
#define MAINT_SEG 0010000000000LL
|
||||
#define PRTLT 0004000000000LL /* Protected area less then bounds */
|
||||
#define STS 0003777000000LL
|
||||
#define SCRCHCMP 0000000400000LL /* Tranfer in progress. */
|
||||
#define S_ERROR 0000000200000LL /* Segment not found */
|
||||
#define DSK_DES_E 0000000100000LL /* Duplicate disk */
|
||||
#define TRK_SEL_E 0000000040000LL /* Track not BCD number */
|
||||
#define NOT_RDY 0000000020000LL /* Drive not ready */
|
||||
#define PSW_FAIL 0000000010000LL /* Power supply fail */
|
||||
#define DSK_PAR_E 0000000004000LL /* Disk Parity Error */
|
||||
#define CH_PAR_D 0000000002000LL /* Channel Data Parity Error */
|
||||
#define CH_PAR_C 0000000001000LL /* Channel Control Parity Error */
|
||||
#define NXM_ERR 0000000000400LL /* Non existant memory */
|
||||
#define ILL_WR 0000000000200LL /* Write to protected area */
|
||||
#define OVRRUN 0000000000100LL /* Over run */
|
||||
|
||||
#define RD10_DTYPE 0
|
||||
#define RD10_WDS 32
|
||||
@ -209,7 +208,7 @@ t_stat rc_devio(uint32 dev, uint64 *data) {
|
||||
switch(dev & 3) {
|
||||
case CONI:
|
||||
*data = df10->status;
|
||||
#if KI10_22BIT
|
||||
#if KI_22BIT
|
||||
*data |= B22_FLAG;
|
||||
#endif
|
||||
sim_debug(DEBUG_CONI, dptr, "HK %03o CONI %06o PC=%o\n", dev,
|
||||
|
||||
@ -476,7 +476,7 @@ t_stat rp_devio(uint32 dev, uint64 *data) {
|
||||
*data |= IADR_ATTN;
|
||||
if (rp_rae[ctlr] != 0 && (df10->status & IARD_RAE))
|
||||
*data |= IARD_RAE;
|
||||
#if KI10_22BIT
|
||||
#if KI_22BIT
|
||||
*data |= B22_FLAG;
|
||||
#endif
|
||||
sim_debug(DEBUG_CONI, dptr, "RP %03o CONI %06o PC=%o %o\n",
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user