mirror of
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KA10: Auto number RH10 devices.
This commit is contained in:
Richard Cornwell
parent
cf34c5a4dd
commit
84bd673bcd
@ -47,7 +47,7 @@ KA10 = ${KA10D}ka10_cpu.c ${KA10D}ka10_sys.c ${KA10D}ka10_df.c \
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${KA10D}ka10_lp.c ${KA10D}ka10_pt.c ${KA10D}ka10_dc.c \
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${KA10D}ka10_rp.c ${KA10D}ka10_rc.c ${KA10D}ka10_dt.c \
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${KA10D}ka10_dk.c ${KA10D}ka10_cr.c ${KA10D}ka10_cp.c \
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${KA10D}ka10_rs.c ${KA10D}ka10_tu.c
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${KA10D}ka10_rs.c ${KA10D}ka10_tu.c ${KA10D}ka10_pd.c
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KA10_OPT = -I.. -DUSE_INT64 -DKA=1 -DUSE_SIM_CARD
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KI10D = ./
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@ -203,6 +203,7 @@ uint32 qua_time; /* Quantum clock value */
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char dev_irq[128]; /* Pending irq by device */
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t_stat (*dev_tab[128])(uint32 dev, uint64 *data);
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int (*dev_irqv[128])(uint32 dev, int addr);
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t_stat rtc_srv(UNIT * uptr);
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int32 rtc_tps = 60;
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#if ITS
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@ -211,6 +212,35 @@ int32 qua_tps = 125000;
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#endif
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int32 tmxr_poll = 10000;
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DEVICE *rh_devs[] = {
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#if (NUM_DEVS_RS > 0)
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&rsa_dev,
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#endif
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#if (NUM_DEVS_RP > 0)
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&rpa_dev,
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#if (NUM_DEVS_RP > 1)
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&rpb_dev,
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#if (NUM_DEVS_RP > 2)
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&rpc_dev,
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#if (NUM_DEVS_RP > 3)
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&rpd_dev,
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#endif
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#endif
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#endif
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#endif
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#if (NUM_DEVS_TU > 0)
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&tua_dev,
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#endif
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NULL,
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};
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struct rh_dev rh[4] = {
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{ 0270, NULL, },
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{ 0274, NULL, },
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{ 0360, NULL, },
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{ 0364, NULL, },
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};
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typedef struct {
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uint32 pc;
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uint32 ea;
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@ -221,9 +251,9 @@ typedef struct {
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uint64 fmb;
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} InstHistory;
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int32 hst_p = 0; /* history pointer */
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int32 hst_lnt = 0; /* history length */
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InstHistory *hst = NULL; /* instruction history */
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int32 hst_p = 0; /* history pointer */
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int32 hst_lnt = 0; /* history length */
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InstHistory *hst = NULL; /* instruction history */
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/* Forward and external declarations */
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@ -252,7 +282,7 @@ t_bool build_dev_tab (void);
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cpu_mod CPU modifier list
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*/
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UNIT cpu_unit[] = { { UDATA (&rtc_srv, UNIT_IDLE|UNIT_FIX|UNIT_BINK|UNIT_TWOSEG, MAXMEMSIZE) },
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UNIT cpu_unit[] = { { UDATA (&rtc_srv, UNIT_IDLE|UNIT_FIX|UNIT_BINK|UNIT_TWOSEG, 256 * 1024 * 1024) },
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#if ITS
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{ UDATA (&qua_srv, UNIT_IDLE|UNIT_DIS, 0) }
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#endif
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@ -2015,19 +2045,10 @@ st_pi:
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* Scan through the devices and allow KI devices to have first
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* hit at a given level.
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*/
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for (f = 0; sim_devices[f] != NULL; f++) {
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DEVICE *dptr = sim_devices[f];
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DIB *dibp = (DIB *) dptr->ctxt;
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if (dibp) {
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if (dibp->irq) { /* Check if KI device */
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int dev = dibp->dev_num >> 2;
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/* Check if this device actually posted IRQ */
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if (dev_irq[dev] & (0200 >> pi_enc)) {
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AB = dibp->irq(dev << 2, AB);
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break;
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}
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}
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for (f = 0; f < 128; f++) {
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if (dev_irqv[f] != 0 && dev_irq[f] & (0200 >> pi_enc)) {
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AB = dev_irqv[f](f << 2, AB);
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break;
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}
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}
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AB |= eb_ptr;
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@ -4816,11 +4837,15 @@ return SCPE_OK;
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t_bool build_dev_tab (void)
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{
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DEVICE *dptr;
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DIB *dibp;
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uint32 i, j;
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DIB *dibp;
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uint32 i, j, d;
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for (i = 0; i < 128; i++)
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/* Clear device and interrupt table */
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for (i = 0; i < 128; i++) {
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dev_tab[i] = &null_dev;
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dev_irqv[i] = NULL;
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}
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dev_tab[0] = &dev_apr;
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dev_tab[1] = &dev_pi;
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#if KI | KL
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@ -4830,18 +4855,43 @@ dev_tab[2] = &dev_pag;
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if (QBBN)
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dev_tab[024] = &dev_pag;
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#endif
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/* Assign all RH10 devices */
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for (j = i = 0; (dptr = rh_devs[i]) != NULL; i++) {
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dibp = (DIB *) dptr->ctxt;
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if (dibp && !(dptr->flags & DEV_DIS)) { /* enabled? */
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if (j == 4)
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break;
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d = rh[j].dev_num;
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dev_tab[(d >> 2)] = dibp->io;
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dev_irqv[(d >> 2)] = dibp->irq;
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rh[j].dev = dptr;
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j++;
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}
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}
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/* Make sure all are assigned */
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if (j == 4 && rh_devs[i] != NULL) {
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sim_printf ("To many RH10 devices %s\n", sim_dname (dptr));
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return TRUE;
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}
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/* Assign all remaining devices */
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for (i = 0; (dptr = sim_devices[i]) != NULL; i++) {
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dibp = (DIB *) dptr->ctxt;
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if (dibp && !(dptr->flags & DEV_DIS)) { /* enabled? */
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for (j = 0; j < dibp->num_devs; j++) { /* loop thru disp */
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if (dibp->io) { /* any dispatch? */
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if (dev_tab[(dibp->dev_num >> 2) + j] != &null_dev) {
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d = dibp->dev_num;
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if (d & RH10_DEV) /* Skip RH10 devices */
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continue;
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if (dev_tab[(d >> 2) + j] != &null_dev) {
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/* already filled? */
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sim_printf ("%s device number conflict at %02o\n",
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sim_dname (dptr), dibp->dev_num + (j << 2));
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sim_dname (dptr), d + (j << 2));
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return TRUE;
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}
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dev_tab[(dibp->dev_num >> 2) + j] = dibp->io; /* fill */
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dev_tab[(d >> 2) + j] = dibp->io; /* fill */
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dev_irqv[(d >> 2) + j] = dibp->irq;
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} /* end if dsp */
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} /* end for j */
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} /* end if enb */
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@ -316,6 +316,7 @@ extern t_stat (*dev_tab[128])(uint32 dev, uint64 *data);
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#define VEC_DEVMAX 8 /* max device vec */
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/* Device context block */
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struct pdp_dib {
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uint32 dev_num; /* device address */
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uint32 num_devs; /* length */
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@ -323,6 +324,12 @@ struct pdp_dib {
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int (*irq)(uint32 dev, int addr);
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};
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struct rh_dev {
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uint32 dev_num;
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DEVICE *dev;
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};
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typedef struct pdp_dib DIB;
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@ -360,14 +367,18 @@ int df10_write(struct df10 *df);
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#define NUM_DEVS_RC 1
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#define NUM_DEVS_DT 1
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#define NUM_DEVS_DK 1
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#define NUM_DEVS_RP 2
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#define NUM_DEVS_RS 0
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#define NUM_DEVS_RP 4
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#define NUM_DEVS_RS 1
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#define NUM_DEVS_TU 1
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#define NUM_DEVS_PD ITS
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/* Global data */
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#define RH10_DEV 01000
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extern t_bool sim_idle_enab;
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struct rh_dev rh[4];
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#endif
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163
PDP10/ka10_rp.c
163
PDP10/ka10_rp.c
@ -26,9 +26,6 @@
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#ifndef NUM_DEVS_RP
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#define NUM_DEVS_RP 0
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#endif
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#ifndef NUM_DEVS_RS
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#define NUM_DEVS_RS 0
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#endif
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#if (NUM_DEVS_RP > 0)
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#define BUF_EMPTY(u) (u->hwmark == 0xFFFFFFFF)
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@ -111,80 +108,80 @@
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/* u3 low */
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/* RPC - 00 - control */
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#define CS1_GO CR_GO /* go */
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#define CS1_V_FNC 1 /* function pos */
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#define CS1_M_FNC 037 /* function mask */
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#define CS1_GO CR_GO /* go */
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#define CS1_V_FNC 1 /* function pos */
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#define CS1_M_FNC 037 /* function mask */
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#define CS1_FNC (CS1_M_FNC << CS1_V_FNC)
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#define FNC_NOP 000 /* no operation */
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#define FNC_UNLOAD 001 /* unload */
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#define FNC_SEEK 002 /* seek */
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#define FNC_RECAL 003 /* recalibrate */
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#define FNC_DCLR 004 /* drive clear */
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#define FNC_RELEASE 005 /* port release */
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#define FNC_OFFSET 006 /* offset */
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#define FNC_RETURN 007 /* return to center */
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#define FNC_PRESET 010 /* read-in preset */
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#define FNC_PACK 011 /* pack acknowledge */
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#define FNC_SEARCH 014 /* search */
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#define FNC_XFER 024 /* >=? data xfr */
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#define FNC_WCHK 024 /* write check */
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#define FNC_WCHKH 025 /* write check headers */
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#define FNC_WRITE 030 /* write */
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#define FNC_WRITEH 031 /* write w/ headers */
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#define FNC_READ 034 /* read */
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#define FNC_READH 035 /* read w/ headers */
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#define CS1_DVA 0004000 /* drive avail NI */
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#define FNC_NOP 000 /* no operation */
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#define FNC_UNLOAD 001 /* unload */
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#define FNC_SEEK 002 /* seek */
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#define FNC_RECAL 003 /* recalibrate */
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#define FNC_DCLR 004 /* drive clear */
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#define FNC_RELEASE 005 /* port release */
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#define FNC_OFFSET 006 /* offset */
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#define FNC_RETURN 007 /* return to center */
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#define FNC_PRESET 010 /* read-in preset */
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#define FNC_PACK 011 /* pack acknowledge */
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#define FNC_SEARCH 014 /* search */
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#define FNC_XFER 024 /* >=? data xfr */
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#define FNC_WCHK 024 /* write check */
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#define FNC_WCHKH 025 /* write check headers */
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#define FNC_WRITE 030 /* write */
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#define FNC_WRITEH 031 /* write w/ headers */
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#define FNC_READ 034 /* read */
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#define FNC_READH 035 /* read w/ headers */
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#define CS1_DVA 0004000 /* drive avail NI */
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#define GET_FNC(x) (((x) >> CS1_V_FNC) & CS1_M_FNC)
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/* u3 low */
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/* RPDS - 01 - drive status */
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#define DS_OFF 0000001 /* offset mode */
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#define DS_VV 0000100 /* volume valid */
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#define DS_DRY 0000200 /* drive ready */
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#define DS_DPR 0000400 /* drive present */
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#define DS_PGM 0001000 /* programable NI */
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#define DS_LST 0002000 /* last sector */
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#define DS_WRL 0004000 /* write locked */
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#define DS_MOL 0010000 /* medium online */
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#define DS_PIP 0020000 /* pos in progress */
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#define DS_ERR 0040000 /* error */
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#define DS_ATA 0100000 /* attention active */
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#define DS_OFF 0000001 /* offset mode */
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#define DS_VV 0000100 /* volume valid */
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#define DS_DRY 0000200 /* drive ready */
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#define DS_DPR 0000400 /* drive present */
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#define DS_PGM 0001000 /* programable NI */
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#define DS_LST 0002000 /* last sector */
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#define DS_WRL 0004000 /* write locked */
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#define DS_MOL 0010000 /* medium online */
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#define DS_PIP 0020000 /* pos in progress */
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#define DS_ERR 0040000 /* error */
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#define DS_ATA 0100000 /* attention active */
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#define DS_MBZ 0000076
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/* u3 high */
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/* RPER1 - 02 - error status 1 */
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#define ER1_ILF 0000001 /* illegal func */
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#define ER1_ILR 0000002 /* illegal register */
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#define ER1_RMR 0000004 /* reg mod refused */
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#define ER1_PAR 0000010 /* parity err */
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#define ER1_FER 0000020 /* format err NI */
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#define ER1_WCF 0000040 /* write clk fail NI */
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#define ER1_ECH 0000100 /* ECC hard err NI */
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#define ER1_HCE 0000200 /* hdr comp err NI */
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#define ER1_HCR 0000400 /* hdr CRC err NI */
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#define ER1_AOE 0001000 /* addr ovflo err */
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#define ER1_IAE 0002000 /* invalid addr err */
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#define ER1_WLE 0004000 /* write lock err */
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#define ER1_DTE 0010000 /* drive time err NI */
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#define ER1_OPI 0020000 /* op incomplete */
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#define ER1_UNS 0040000 /* drive unsafe */
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#define ER1_DCK 0100000 /* data check NI */
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#define ER1_ILF 0000001 /* illegal func */
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#define ER1_ILR 0000002 /* illegal register */
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#define ER1_RMR 0000004 /* reg mod refused */
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#define ER1_PAR 0000010 /* parity err */
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#define ER1_FER 0000020 /* format err NI */
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#define ER1_WCF 0000040 /* write clk fail NI */
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#define ER1_ECH 0000100 /* ECC hard err NI */
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#define ER1_HCE 0000200 /* hdr comp err NI */
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#define ER1_HCR 0000400 /* hdr CRC err NI */
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#define ER1_AOE 0001000 /* addr ovflo err */
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#define ER1_IAE 0002000 /* invalid addr err */
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#define ER1_WLE 0004000 /* write lock err */
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#define ER1_DTE 0010000 /* drive time err NI */
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#define ER1_OPI 0020000 /* op incomplete */
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#define ER1_UNS 0040000 /* drive unsafe */
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#define ER1_DCK 0100000 /* data check NI */
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/* RPMR - 03 - maintenace register */
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/* RPAS - 04 - attention summary */
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#define AS_U0 0000001 /* unit 0 flag */
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#define AS_U0 0000001 /* unit 0 flag */
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/* u4 high */
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/* RPDC - 05 - desired sector */
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#define DA_V_SC 16 /* sector pos */
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#define DA_M_SC 077 /* sector mask */
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#define DA_V_SF 24 /* track pos */
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#define DA_M_SF 077 /* track mask */
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#define DA_V_SC 16 /* sector pos */
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#define DA_M_SC 077 /* sector mask */
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#define DA_V_SF 24 /* track pos */
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#define DA_M_SF 077 /* track mask */
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#define DA_MBZ 0140300
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#define GET_SC(x) (((x) >> DA_V_SC) & DA_M_SC)
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#define GET_SF(x) (((x) >> DA_V_SF) & DA_M_SF)
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@ -386,12 +383,10 @@ UNIT rp_unit[] = {
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};
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DIB rp_dib[] = {
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#if NUM_DEVS_RS == 0
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{RP_DEVNUM+0000, 1, &rp_devio, &rp_devirq},
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#endif
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{RP_DEVNUM+0004, 1, &rp_devio, &rp_devirq},
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{RP_DEVNUM+0070, 1, &rp_devio, &rp_devirq},
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{RP_DEVNUM+0074, 1, &rp_devio, &rp_devirq}};
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{RH10_DEV, 1, &rp_devio, &rp_devirq},
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{RH10_DEV, 1, &rp_devio, &rp_devirq},
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{RH10_DEV, 1, &rp_devio, &rp_devirq},
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{RH10_DEV, 1, &rp_devio, &rp_devirq}};
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MTAB rp_mod[] = {
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{UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL},
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@ -424,7 +419,7 @@ DEVICE rpc_dev = {
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"RPC", &rp_unit[020], NULL, rp_mod,
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NUM_UNITS_RP, 8, 18, 1, 8, 36,
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NULL, NULL, &rp_reset, &rp_boot, &rp_attach, &rp_detach,
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&rp_dib[2], DEV_DISABLE | DEV_DEBUG, 0, dev_debug,
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&rp_dib[2], DEV_DISABLE | DEV_DIS | DEV_DEBUG, 0, dev_debug,
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NULL, NULL, &rp_help, NULL, NULL, &rp_description
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};
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@ -433,7 +428,7 @@ DEVICE rpd_dev = {
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"RPD", &rp_unit[030], NULL, rp_mod,
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NUM_UNITS_RP, 8, 18, 1, 8, 36,
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NULL, NULL, &rp_reset, &rp_boot, &rp_attach, &rp_detach,
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&rp_dib[3], DEV_DISABLE | DEV_DEBUG, 0, dev_debug,
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&rp_dib[3], DEV_DISABLE | DEV_DIS | DEV_DEBUG, 0, dev_debug,
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NULL, NULL, &rp_help, NULL, NULL, &rp_description
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};
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@ -457,19 +452,22 @@ DEVICE *rp_devs[] = {
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t_stat rp_devio(uint32 dev, uint64 *data) {
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int ctlr = -1;
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DEVICE *dptr;
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DEVICE *dptr = NULL;
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struct df10 *df10;
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int drive;
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for (drive = 0; drive < NUM_DEVS_RP; drive++) {
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if (rp_dib[drive].dev_num == (dev & 0774)) {
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ctlr = drive;
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for (drive = 0; drive < 4; drive++) {
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if (rh[drive].dev_num == (dev & 0774)) {
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dptr = rh[drive].dev;
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break;
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}
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}
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if (ctlr < 0)
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if (dptr == NULL)
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return SCPE_OK;
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dptr = rp_devs[ctlr];
|
||||
for (ctlr = 0; ctlr < NUM_DEVS_RP; ctlr++) {
|
||||
if (dptr == rp_devs[ctlr])
|
||||
break;
|
||||
}
|
||||
df10 = &rp_df10[ctlr];
|
||||
switch(dev & 3) {
|
||||
case CONI:
|
||||
@ -597,12 +595,19 @@ t_stat rp_devio(uint32 dev, uint64 *data) {
|
||||
/* Handle KI and KL style interrupt vectors */
|
||||
int
|
||||
rp_devirq(uint32 dev, int addr) {
|
||||
int drive;
|
||||
DEVICE *dptr = NULL;
|
||||
int drive;
|
||||
|
||||
for (drive = 0; drive < NUM_DEVS_RP; drive++) {
|
||||
if (rp_dib[drive].dev_num == (dev & 0774))
|
||||
return (rp_imode[drive] ? rp_ivect[drive] : addr);
|
||||
}
|
||||
for (drive = 0; drive < 4; drive++) {
|
||||
if (rh[drive].dev_num == (dev & 0774)) {
|
||||
dptr = rh[drive].dev;
|
||||
break;
|
||||
}
|
||||
}
|
||||
for (drive = 0; drive < NUM_DEVS_RP; drive++) {
|
||||
if (dptr == rp_devs[drive])
|
||||
return (rp_imode[drive] ? rp_ivect[drive] : addr);
|
||||
}
|
||||
return addr;
|
||||
}
|
||||
|
||||
@ -813,9 +818,9 @@ t_stat rp_svc (UNIT *uptr)
|
||||
dptr = rp_devs[ctlr];
|
||||
unit = uptr - dptr->units;
|
||||
df = &rp_df10[ctlr];
|
||||
if ((uptr->flags & UNIT_ATT) == 0) { /* not attached? */
|
||||
uptr->u3 |= (ER1_UNS << 16) | DS_ATA|DS_ERR; /* set drive error */
|
||||
if (GET_FNC(uptr->u3) >= FNC_XFER) { /* xfr? set done */
|
||||
if ((uptr->flags & UNIT_ATT) == 0) { /* not attached? */
|
||||
uptr->u3 |= (ER1_UNS << 16) | DS_ATA|DS_ERR; /* set drive error */
|
||||
if (GET_FNC(uptr->u3) >= FNC_XFER) { /* xfr? set done */
|
||||
df->status &= ~BUSY;
|
||||
df10_setirq(df);
|
||||
}
|
||||
|
||||
123
PDP10/ka10_rs.c
123
PDP10/ka10_rs.c
@ -28,7 +28,6 @@
|
||||
#endif
|
||||
|
||||
#if (NUM_DEVS_RS > 0)
|
||||
#define RS_DEVNUM 0270 /* First device number */
|
||||
|
||||
#define RS_NUMWD 128 /* 36bit words/sec */
|
||||
#define NUM_UNITS_RS 8
|
||||
@ -107,69 +106,69 @@
|
||||
/* u3 low */
|
||||
/* RSC - 00 - control */
|
||||
|
||||
#define CS1_GO CR_GO /* go */
|
||||
#define CS1_V_FNC 1 /* function pos */
|
||||
#define CS1_M_FNC 037 /* function mask */
|
||||
#define CS1_GO CR_GO /* go */
|
||||
#define CS1_V_FNC 1 /* function pos */
|
||||
#define CS1_M_FNC 037 /* function mask */
|
||||
#define CS1_FNC (CS1_M_FNC << CS1_V_FNC)
|
||||
#define FNC_NOP 000 /* no operation */
|
||||
#define FNC_DCLR 004 /* drive clear */
|
||||
#define FNC_PRESET 010 /* read-in preset */
|
||||
#define FNC_SEARCH 014 /* search */
|
||||
#define FNC_XFER 024 /* >=? data xfr */
|
||||
#define FNC_WCHK 024 /* write check */
|
||||
#define FNC_WRITE 030 /* write */
|
||||
#define FNC_READ 034 /* read */
|
||||
#define CS1_DVA 0004000 /* drive avail NI */
|
||||
#define FNC_NOP 000 /* no operation */
|
||||
#define FNC_DCLR 004 /* drive clear */
|
||||
#define FNC_PRESET 010 /* read-in preset */
|
||||
#define FNC_SEARCH 014 /* search */
|
||||
#define FNC_XFER 024 /* >=? data xfr */
|
||||
#define FNC_WCHK 024 /* write check */
|
||||
#define FNC_WRITE 030 /* write */
|
||||
#define FNC_READ 034 /* read */
|
||||
#define CS1_DVA 0004000 /* drive avail NI */
|
||||
#define GET_FNC(x) (((x) >> CS1_V_FNC) & CS1_M_FNC)
|
||||
|
||||
/* u3 low */
|
||||
/* RSDS - 01 - drive status */
|
||||
|
||||
#define DS_VV 0000000 /* volume valid */
|
||||
#define DS_DRY 0000200 /* drive ready */
|
||||
#define DS_DPR 0000400 /* drive present */
|
||||
#define DS_PGM 0001000 /* programable NI */
|
||||
#define DS_LST 0002000 /* last sector */
|
||||
#define DS_WRL 0004000 /* write locked */
|
||||
#define DS_MOL 0010000 /* medium online */
|
||||
#define DS_PIP 0020000 /* pos in progress */
|
||||
#define DS_ERR 0040000 /* error */
|
||||
#define DS_ATA 0100000 /* attention active */
|
||||
#define DS_VV 0000000 /* volume valid */
|
||||
#define DS_DRY 0000200 /* drive ready */
|
||||
#define DS_DPR 0000400 /* drive present */
|
||||
#define DS_PGM 0001000 /* programable NI */
|
||||
#define DS_LST 0002000 /* last sector */
|
||||
#define DS_WRL 0004000 /* write locked */
|
||||
#define DS_MOL 0010000 /* medium online */
|
||||
#define DS_PIP 0020000 /* pos in progress */
|
||||
#define DS_ERR 0040000 /* error */
|
||||
#define DS_ATA 0100000 /* attention active */
|
||||
#define DS_MBZ 0000076
|
||||
|
||||
/* u3 high */
|
||||
/* RSER1 - 02 - error status 1 */
|
||||
|
||||
#define ER1_ILF 0000001 /* illegal func */
|
||||
#define ER1_ILR 0000002 /* illegal register */
|
||||
#define ER1_RMR 0000004 /* reg mod refused */
|
||||
#define ER1_PAR 0000010 /* parity err */
|
||||
#define ER1_FER 0000020 /* format err NI */
|
||||
#define ER1_WCF 0000040 /* write clk fail NI */
|
||||
#define ER1_ECH 0000100 /* ECC hard err NI */
|
||||
#define ER1_HCE 0000200 /* hdr comp err NI */
|
||||
#define ER1_HCR 0000400 /* hdr CRC err NI */
|
||||
#define ER1_AOE 0001000 /* addr ovflo err */
|
||||
#define ER1_IAE 0002000 /* invalid addr err */
|
||||
#define ER1_WLE 0004000 /* write lock err */
|
||||
#define ER1_DTE 0010000 /* drive time err NI */
|
||||
#define ER1_OPI 0020000 /* op incomplete */
|
||||
#define ER1_UNS 0040000 /* drive unsafe */
|
||||
#define ER1_DCK 0100000 /* data check NI */
|
||||
#define ER1_ILF 0000001 /* illegal func */
|
||||
#define ER1_ILR 0000002 /* illegal register */
|
||||
#define ER1_RMR 0000004 /* reg mod refused */
|
||||
#define ER1_PAR 0000010 /* parity err */
|
||||
#define ER1_FER 0000020 /* format err NI */
|
||||
#define ER1_WCF 0000040 /* write clk fail NI */
|
||||
#define ER1_ECH 0000100 /* ECC hard err NI */
|
||||
#define ER1_HCE 0000200 /* hdr comp err NI */
|
||||
#define ER1_HCR 0000400 /* hdr CRC err NI */
|
||||
#define ER1_AOE 0001000 /* addr ovflo err */
|
||||
#define ER1_IAE 0002000 /* invalid addr err */
|
||||
#define ER1_WLE 0004000 /* write lock err */
|
||||
#define ER1_DTE 0010000 /* drive time err NI */
|
||||
#define ER1_OPI 0020000 /* op incomplete */
|
||||
#define ER1_UNS 0040000 /* drive unsafe */
|
||||
#define ER1_DCK 0100000 /* data check NI */
|
||||
|
||||
/* RSMR - 03 - maintenace register */
|
||||
|
||||
/* RSAS - 04 - attention summary */
|
||||
|
||||
#define AS_U0 0000001 /* unit 0 flag */
|
||||
#define AS_U0 0000001 /* unit 0 flag */
|
||||
|
||||
/* u4 high */
|
||||
/* RSDC - 05 - desired sector */
|
||||
|
||||
#define DA_V_SC 0 /* sector pos */
|
||||
#define DA_M_SC 077 /* sector mask */
|
||||
#define DA_V_SF 6 /* track pos */
|
||||
#define DA_M_SF 077 /* track mask */
|
||||
#define DA_V_SC 0 /* sector pos */
|
||||
#define DA_M_SC 077 /* sector mask */
|
||||
#define DA_V_SF 6 /* track pos */
|
||||
#define DA_M_SF 077 /* track mask */
|
||||
#define DA_MBZ 0170000
|
||||
#define GET_SC(x) (((x) >> DA_V_SC) & DA_M_SC)
|
||||
#define GET_SF(x) (((x) >> DA_V_SF) & DA_M_SF)
|
||||
@ -273,7 +272,7 @@ UNIT rs_unit[] = {
|
||||
};
|
||||
|
||||
DIB rs_dib[] = {
|
||||
{RS_DEVNUM, 1, &rs_devio, &rs_devirq}
|
||||
{RH10_DEV, 1, &rs_devio, &rs_devirq}
|
||||
};
|
||||
|
||||
MTAB rs_mod[] = {
|
||||
@ -288,7 +287,7 @@ DEVICE rsa_dev = {
|
||||
"FSA", rs_unit, NULL, rs_mod,
|
||||
NUM_UNITS_RS, 8, 18, 1, 8, 36,
|
||||
NULL, NULL, &rs_reset, &rs_boot, &rs_attach, &rs_detach,
|
||||
&rs_dib[0], DEV_DISABLE | DEV_DEBUG, 0, dev_debug,
|
||||
&rs_dib[0], DEV_DISABLE | DEV_DIS | DEV_DEBUG, 0, dev_debug,
|
||||
NULL, NULL, &rs_help, NULL, NULL, &rs_description
|
||||
};
|
||||
|
||||
@ -299,19 +298,22 @@ DEVICE *rs_devs[] = {
|
||||
|
||||
t_stat rs_devio(uint32 dev, uint64 *data) {
|
||||
int ctlr = -1;
|
||||
DEVICE *dptr;
|
||||
DEVICE *dptr = NULL;
|
||||
struct df10 *df10;
|
||||
int drive;
|
||||
|
||||
for (drive = 0; drive < NUM_DEVS_RS; drive++) {
|
||||
if (rs_dib[drive].dev_num == (dev & 0774)) {
|
||||
ctlr = drive;
|
||||
for (drive = 0; drive < 4; drive++) {
|
||||
if (rh[drive].dev_num == (dev & 0774)) {
|
||||
dptr = rh[drive].dev;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (ctlr < 0)
|
||||
if (dptr == NULL)
|
||||
return SCPE_OK;
|
||||
dptr = rs_devs[ctlr];
|
||||
for (ctlr = 0; ctlr < NUM_DEVS_RS; ctlr++) {
|
||||
if (dptr == rs_devs[ctlr])
|
||||
break;
|
||||
}
|
||||
df10 = &rs_df10[ctlr];
|
||||
switch(dev & 3) {
|
||||
case CONI:
|
||||
@ -440,12 +442,19 @@ t_stat rs_devio(uint32 dev, uint64 *data) {
|
||||
/* Handle KI and KL style interrupt vectors */
|
||||
int
|
||||
rs_devirq(uint32 dev, int addr) {
|
||||
int drive;
|
||||
DEVICE *dptr = NULL;
|
||||
int drive;
|
||||
|
||||
for (drive = 0; drive < NUM_DEVS_RS; drive++) {
|
||||
if (rs_dib[drive].dev_num == (dev & 0774))
|
||||
return (rs_imode[drive] ? rs_ivect[drive] : addr);
|
||||
}
|
||||
for (drive = 0; drive < 4; drive++) {
|
||||
if (rh[drive].dev_num == (dev & 0774)) {
|
||||
dptr = rh[drive].dev;
|
||||
break;
|
||||
}
|
||||
}
|
||||
for (drive = 0; drive < NUM_DEVS_RS; drive++) {
|
||||
if (dptr == rs_devs[drive])
|
||||
return (rs_imode[drive] ? rs_ivect[drive] : addr);
|
||||
}
|
||||
return addr;
|
||||
}
|
||||
|
||||
|
||||
@ -93,6 +93,9 @@ DEVICE *sim_devices[] = {
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#if (NUM_DEVS_RS > 0)
|
||||
&rsa_dev,
|
||||
#endif
|
||||
#if (NUM_DEVS_RP > 0)
|
||||
&rpa_dev,
|
||||
#if (NUM_DEVS_RP > 1)
|
||||
@ -105,9 +108,6 @@ DEVICE *sim_devices[] = {
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#if (NUM_DEVS_RS > 0)
|
||||
&rsa_dev,
|
||||
#endif
|
||||
#if (NUM_DEVS_TU > 0)
|
||||
&tua_dev,
|
||||
#endif
|
||||
|
||||
170
PDP10/ka10_tu.c
170
PDP10/ka10_tu.c
@ -27,27 +27,8 @@
|
||||
#ifndef NUM_DEVS_TU
|
||||
#define NUM_DEVS_TU 0
|
||||
#endif
|
||||
#ifndef NUM_DEVS_RP
|
||||
#define NUM_DEVS_RP 0
|
||||
#endif
|
||||
#ifndef NUM_DEVS_RS
|
||||
#define NUM_DEVS_RS 0
|
||||
#endif
|
||||
|
||||
#if (NUM_DEVS_TU > 0)
|
||||
#define NUM_DEV (NUM_DEVS_RP + NUM_DEVS_RS)
|
||||
|
||||
#if (NUM_DEV == 0)
|
||||
#define TU_DEVNUM 0270 /* First device number */
|
||||
#elif (NUM_DEV == 1)
|
||||
#define TU_DEVNUM 0274 /* Second device number */
|
||||
#elif (NUM_DEV == 2)
|
||||
#define TU_DEVNUM 0360 /* Third device number */
|
||||
#elif (NUM_DEV == 3)
|
||||
#define TU_DEVNUM 0364 /* Fourth device number */
|
||||
#else
|
||||
#error "Only 4 RH10 devices allowed"
|
||||
#endif
|
||||
|
||||
#define NUM_UNITS_TU 8
|
||||
#define TU_NUMFR (64*1024)
|
||||
@ -119,78 +100,78 @@
|
||||
/* u3 low */
|
||||
/* TUC - 00 - control */
|
||||
|
||||
#define CS1_GO CR_GO /* go */
|
||||
#define CS1_V_FNC 1 /* function pos */
|
||||
#define CS1_M_FNC 037 /* function mask */
|
||||
#define CS1_GO CR_GO /* go */
|
||||
#define CS1_V_FNC 1 /* function pos */
|
||||
#define CS1_M_FNC 037 /* function mask */
|
||||
#define CS1_FNC (CS1_M_FNC << CS1_V_FNC)
|
||||
#define FNC_NOP 000 /* no operation */
|
||||
#define FNC_UNLOAD 001 /* unload */
|
||||
#define FNC_REWIND 003 /* rewind */
|
||||
#define FNC_DCLR 004 /* drive clear */
|
||||
#define FNC_PRESET 010 /* read-in preset */
|
||||
#define FNC_ERASE 012 /* Erase */
|
||||
#define FNC_WTM 013 /* Write Tape Mark */
|
||||
#define FNC_SPACEF 014 /* Space record forward */
|
||||
#define FNC_SPACEB 015 /* Space record backward */
|
||||
#define FNC_XFER 024 /* >=? data xfr */
|
||||
#define FNC_WCHK 024 /* write check */
|
||||
#define FNC_WCHKREV 027 /* write check reverse */
|
||||
#define FNC_WRITE 030 /* write */
|
||||
#define FNC_READ 034 /* read */
|
||||
#define FNC_READREV 037 /* read reverse */
|
||||
#define CS1_DVA 0004000 /* drive avail NI */
|
||||
#define FNC_NOP 000 /* no operation */
|
||||
#define FNC_UNLOAD 001 /* unload */
|
||||
#define FNC_REWIND 003 /* rewind */
|
||||
#define FNC_DCLR 004 /* drive clear */
|
||||
#define FNC_PRESET 010 /* read-in preset */
|
||||
#define FNC_ERASE 012 /* Erase */
|
||||
#define FNC_WTM 013 /* Write Tape Mark */
|
||||
#define FNC_SPACEF 014 /* Space record forward */
|
||||
#define FNC_SPACEB 015 /* Space record backward */
|
||||
#define FNC_XFER 024 /* >=? data xfr */
|
||||
#define FNC_WCHK 024 /* write check */
|
||||
#define FNC_WCHKREV 027 /* write check reverse */
|
||||
#define FNC_WRITE 030 /* write */
|
||||
#define FNC_READ 034 /* read */
|
||||
#define FNC_READREV 037 /* read reverse */
|
||||
#define CS1_DVA 0004000 /* drive avail NI */
|
||||
#define GET_FNC(x) (((x) >> CS1_V_FNC) & CS1_M_FNC)
|
||||
#define CS_TM 001000 /* Tape mark sensed */
|
||||
#define CS_MOTION 002000 /* Tape moving */
|
||||
#define CS_PIP 004000 /* Tape Position command */
|
||||
#define CS_ATA 010000 /* Tape signals attention */
|
||||
#define CS_CHANGE 020000 /* Status changed */
|
||||
#define CS_TM 001000 /* Tape mark sensed */
|
||||
#define CS_MOTION 002000 /* Tape moving */
|
||||
#define CS_PIP 004000 /* Tape Position command */
|
||||
#define CS_ATA 010000 /* Tape signals attention */
|
||||
#define CS_CHANGE 020000 /* Status changed */
|
||||
|
||||
/* u5 low */
|
||||
/* TUDS - 01 - drive status */
|
||||
|
||||
#define DS_SLA 0000001 /* Drive has become ready */
|
||||
#define DS_BOT 0000002 /* Beginning of tape */
|
||||
#define DS_TM 0000004 /* Tape mark */
|
||||
#define DS_IDB 0000010 /* Identification burst */
|
||||
#define DS_SDWN 0000020 /* Tape stoped */
|
||||
#define DS_PES 0000040 /* Phase Encoding */
|
||||
#define DS_SSC 0000100 /* Status change */
|
||||
#define DS_DRY 0000200 /* drive ready */
|
||||
#define DS_DPR 0000400 /* drive present */
|
||||
#define DS_PGM 0001000 /* programable NI */
|
||||
#define DS_EOT 0002000 /* end of tape */
|
||||
#define DS_WRL 0004000 /* write locked */
|
||||
#define DS_MOL 0010000 /* medium online */
|
||||
#define DS_PIP 0020000 /* pos in progress */
|
||||
#define DS_ERR 0040000 /* error */
|
||||
#define DS_ATA 0100000 /* attention active */
|
||||
#define DS_SLA 0000001 /* Drive has become ready */
|
||||
#define DS_BOT 0000002 /* Beginning of tape */
|
||||
#define DS_TM 0000004 /* Tape mark */
|
||||
#define DS_IDB 0000010 /* Identification burst */
|
||||
#define DS_SDWN 0000020 /* Tape stoped */
|
||||
#define DS_PES 0000040 /* Phase Encoding */
|
||||
#define DS_SSC 0000100 /* Status change */
|
||||
#define DS_DRY 0000200 /* drive ready */
|
||||
#define DS_DPR 0000400 /* drive present */
|
||||
#define DS_PGM 0001000 /* programable NI */
|
||||
#define DS_EOT 0002000 /* end of tape */
|
||||
#define DS_WRL 0004000 /* write locked */
|
||||
#define DS_MOL 0010000 /* medium online */
|
||||
#define DS_PIP 0020000 /* pos in progress */
|
||||
#define DS_ERR 0040000 /* error */
|
||||
#define DS_ATA 0100000 /* attention active */
|
||||
|
||||
/* u5 high */
|
||||
/* TUER1 - 02 - error status 1 */
|
||||
|
||||
#define ER1_ILF 0000001 /* illegal func */
|
||||
#define ER1_ILR 0000002 /* illegal register */
|
||||
#define ER1_RMR 0000004 /* reg mod refused */
|
||||
#define ER1_CPAR 0000010 /* control parity err NI */
|
||||
#define ER1_FMT 0000020 /* format err */
|
||||
#define ER1_DPAR 0000040 /* data parity error */
|
||||
#define ER1_INC 0000100 /* Incorrectable data */
|
||||
#define ER1_PEF 0000200 /* format error */
|
||||
#define ER1_NSG 0000400 /* Nonstandard gap NI */
|
||||
#define ER1_FCE 0001000 /* Frame count error */
|
||||
#define ER1_ITM 0002000 /* Illegal tape mark */
|
||||
#define ER1_NEF 0004000 /* Non executable function */
|
||||
#define ER1_DTE 0010000 /* drive time err NI */
|
||||
#define ER1_OPI 0020000 /* op incomplete */
|
||||
#define ER1_UNS 0040000 /* drive unsafe */
|
||||
#define ER1_DCK 0100000 /* data check NI */
|
||||
#define ER1_ILF 0000001 /* illegal func */
|
||||
#define ER1_ILR 0000002 /* illegal register */
|
||||
#define ER1_RMR 0000004 /* reg mod refused */
|
||||
#define ER1_CPAR 0000010 /* control parity err NI */
|
||||
#define ER1_FMT 0000020 /* format err */
|
||||
#define ER1_DPAR 0000040 /* data parity error */
|
||||
#define ER1_INC 0000100 /* Incorrectable data */
|
||||
#define ER1_PEF 0000200 /* format error */
|
||||
#define ER1_NSG 0000400 /* Nonstandard gap NI */
|
||||
#define ER1_FCE 0001000 /* Frame count error */
|
||||
#define ER1_ITM 0002000 /* Illegal tape mark */
|
||||
#define ER1_NEF 0004000 /* Non executable function */
|
||||
#define ER1_DTE 0010000 /* drive time err NI */
|
||||
#define ER1_OPI 0020000 /* op incomplete */
|
||||
#define ER1_UNS 0040000 /* drive unsafe */
|
||||
#define ER1_DCK 0100000 /* data check NI */
|
||||
|
||||
/* TUMR - 03 - maintenace register */
|
||||
|
||||
/* TUAS - 04 - attention summary */
|
||||
|
||||
#define AS_U0 0000001 /* unit 0 flag */
|
||||
#define AS_U0 0000001 /* unit 0 flag */
|
||||
|
||||
/* TUDC - 05 - frame count */
|
||||
|
||||
@ -270,7 +251,7 @@ UNIT tu_unit[] = {
|
||||
};
|
||||
|
||||
DIB tu_dib[] = {
|
||||
{TU_DEVNUM, 1, &tu_devio, &tu_devirq}
|
||||
{RH10_DEV, 1, &tu_devio, &tu_devirq}
|
||||
};
|
||||
|
||||
MTAB tu_mod[] = {
|
||||
@ -301,19 +282,23 @@ DEVICE *tu_devs[] = {
|
||||
|
||||
t_stat tu_devio(uint32 dev, uint64 *data) {
|
||||
int ctlr = -1;
|
||||
DEVICE *dptr;
|
||||
DEVICE *dptr = NULL;
|
||||
struct df10 *df10;
|
||||
int drive;
|
||||
|
||||
for (drive = 0; drive < NUM_DEVS_TU; drive++) {
|
||||
if (tu_dib[drive].dev_num == (dev & 0774)) {
|
||||
ctlr = drive;
|
||||
for (drive = 0; drive < 4; drive++) {
|
||||
if (rh[drive].dev_num == (dev & 0774)) {
|
||||
dptr = rh[drive].dev;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (ctlr < 0)
|
||||
return SCPE_OK;
|
||||
dptr = tu_devs[ctlr];
|
||||
|
||||
if (dptr == NULL)
|
||||
return SCPE_OK;
|
||||
for (ctlr = 0; ctlr < NUM_DEVS_TU; ctlr++) {
|
||||
if (dptr == tu_devs[ctlr])
|
||||
break;
|
||||
}
|
||||
df10 = &tu_df10[ctlr];
|
||||
switch(dev & 3) {
|
||||
case CONI:
|
||||
@ -448,12 +433,19 @@ t_stat tu_devio(uint32 dev, uint64 *data) {
|
||||
/* Handle KI and KL style interrupt vectors */
|
||||
int
|
||||
tu_devirq(uint32 dev, int addr) {
|
||||
int drive;
|
||||
DEVICE *dptr = NULL;
|
||||
int drive;
|
||||
|
||||
for (drive = 0; drive < NUM_DEVS_TU; drive++) {
|
||||
if (tu_dib[drive].dev_num == (dev & 0774))
|
||||
return (tu_imode[drive] ? tu_ivect[drive] : addr);
|
||||
}
|
||||
for (drive = 0; drive < 4; drive++) {
|
||||
if (rh[drive].dev_num == (dev & 0774)) {
|
||||
dptr = rh[drive].dev;
|
||||
break;
|
||||
}
|
||||
}
|
||||
for (drive = 0; drive < NUM_DEVS_TU; drive++) {
|
||||
if (dptr == tu_devs[drive])
|
||||
return (tu_imode[drive] ? tu_ivect[drive] : addr);
|
||||
}
|
||||
return addr;
|
||||
}
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user