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SEL32: Added test cases, more devices.
This commit is contained in:
Richard Cornwell
File diff suppressed because it is too large
Load Diff
4294
SEL32/sel32_cpu.c
4294
SEL32/sel32_cpu.c
File diff suppressed because it is too large
Load Diff
@@ -1,6 +1,6 @@
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/* sel32_defs.h: Gould Concept/32 (orignal SEL32) simulator definitions
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Copyright (c) 2018, Richard Cornwell
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Copyright (c) 2017, Richard Cornwell
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Copyright (c) 2018, James C. Bevier
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Permission is hereby granted, free of charge, to any person obtaining a
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@@ -16,244 +16,172 @@
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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RICHARD CORNWELL OR JAMES BEVIER BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "sim_defs.h" /* simulator defns */
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#include "sim_defs.h" /* simulator defns */
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/* Simulator stop codes */
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#define STOP_IONRDY 1 /* I/O dev not ready */
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#define STOP_HALT 2 /* HALT */
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#define STOP_IBKPT 3 /* breakpoint */
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#define STOP_UUO 4 /* invalid opcode */
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#define STOP_INVINS 5 /* invalid instr */
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#define STOP_INVIOP 6 /* invalid I/O op */
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#define STOP_INDLIM 7 /* indirect limit */
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#define STOP_XECLIM 8 /* XEC limit */
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#define STOP_IOCHECK 9 /* IOCHECK */
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#define STOP_MMTRP 10 /* mm in trap */
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#define STOP_TRPINS 11 /* trap inst not BRM */
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#define STOP_RTCINS 12 /* rtc inst not MIN/SKR */
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#define STOP_ILLVEC 13 /* zero vector */
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#define STOP_CCT 14 /* runaway CCT */
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#define STOP_IONRDY 1 /* I/O dev not ready */
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#define STOP_HALT 2 /* HALT */
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#define STOP_IBKPT 3 /* breakpoint */
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#define STOP_UUO 4 /* invalid opcode */
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#define STOP_INVINS 5 /* invalid instr */
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#define STOP_INVIOP 6 /* invalid I/O op */
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#define STOP_INDLIM 7 /* indirect limit */
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#define STOP_XECLIM 8 /* XEC limit */
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#define STOP_IOCHECK 9 /* IOCHECK */
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#define STOP_MMTRP 10 /* mm in trap */
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#define STOP_TRPINS 11 /* trap inst not BRM */
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#define STOP_RTCINS 12 /* rtc inst not MIN/SKR */
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#define STOP_ILLVEC 13 /* zero vector */
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#define STOP_CCT 14 /* runaway CCT */
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/* I/O equates */
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/* Channel sense bytes */
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#define SNS_ATTN 0x80 /* Unit attention */
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#define SNS_SMS 0x40 /* Status modifier */
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#define SNS_CTLEND 0x20 /* Control unit end */
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#define SNS_BSY 0x10 /* Unit Busy */
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#define SNS_CHNEND 0x08 /* Channel end */
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#define SNS_DEVEND 0x04 /* Device end */
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#define SNS_UNITCHK 0x02 /* Unit check */
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#define SNS_UNITEXP 0x01 /* Unit exception */
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/* Command masks */
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#define CCMDMSK 0xff000000 /* Mask for command */
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#define CMD_CHAN 0x00 /* Channel control */
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#define CMD_SENSE 0x04 /* Sense channel command */
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#define CMD_TIC 0x08 /* Transfer in channel */
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#define CMD_RDBWD 0x0c /* Read backward (not used) */
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/* operation types */
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#define CMD_TYPE 0x03 /* Type mask */
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#define CMD_WRITE 0x01 /* Write command */
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#define CMD_READ 0x02 /* Read command */
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#define CMD_CTL 0x03 /* Control command */
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#define STATUS_ATTN 0x8000 /* Device raised attention */
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#define STATUS_MOD 0x4000 /* Status modifier */
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#define STATUS_CTLEND 0x2000 /* Control end */
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#define STATUS_BUSY 0x1000 /* Device busy */
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#define STATUS_CEND 0x0800 /* Channel end */
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#define STATUS_DEND 0x0400 /* Device end */
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#define STATUS_CHECK 0x0200 /* Unit check */
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#define STATUS_EXPT 0x0100 /* Unit excpetion */
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#define STATUS_PCI 0x0080 /* Program interupt */
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#define STATUS_LENGTH 0x0040 /* Incorrect lenght */
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#define STATUS_PCHK 0x0020 /* Program check */
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#define STATUS_PROT 0x0010 /* Protection check */
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#define STATUS_CDATA 0x0008 /* Channel data check */
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#define STATUS_CCNTL 0x0004 /* Channel control check */
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#define STATUS_INTER 0x0002 /* Channel interface check */
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#define STATUS_CHAIN 0x0001 /* Channel chain check */
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/* Class F channel bits */
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/* bit 32 - 37 of IOCD word 2 (0-5) */
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#define FLAG_DC 0x8000 /* Data chain */
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#define FLAG_CC 0x4000 /* Chain command */
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#define FLAG_SLI 0x2000 /* Suppress length indicator */
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#define FLAG_SKIP 0x1000 /* Suppress memory write */
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#define FLAG_PCI 0x0800 /* Program controlled interrupt */
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#define FLAG_RTO 0x0400 /* Real-Time Option */
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#if 0
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#define CCMDMSK 0xff000000 /* Mask for command */
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#define CDADRMSK 0x00ffffff /* Mask for data address */
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#define CCNTMSK 0x0000ffff /* Mask for data count */
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#define CHD 0x80000000 /* Chain data */
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#define CHC 0x40000000 /* Chain command */
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#define SLI 0x20000000 /* Suppress length indication */
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#define SKIP 0x10000000 /* Skip flag */
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#define PCI 0x08000000 /* Program controlled interuption */
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#endif
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#define BUFF_EMPTY 0x4 /* Buffer is empty */
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#define BUFF_DIRTY 0x8 /* Buffer is dirty flag */
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#define BUFF_NEWCMD 0x10 /* Channel ready for new command */
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#define BUFF_CHNEND 0x20 /* Channel end */
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#define MAX_CHAN 128 /* max channels that can be defined */
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#define SUB_CHANS 256 /* max sub channels that can be defined */
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#define MAX_DEV (MAX_CHAN * SUB_CHANS) /* max possible */
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/* simulator devices configuration */
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#define NUM_DEVS_MT 1 /* mag tape units */
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#define NUM_UNITS_MT 8 /* 8 devices */
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#define NUM_DEVS_DISK 2 /* disk drive devices */
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#define NUM_UNITS_DISK 2 /* 2 devices */
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extern DEVICE cpu_dev; /* cpu device */
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extern UNIT cpu_unit; /* the cpu unit */
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#ifdef NUM_DEVS_MT
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extern DEVICE mta_dev;
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#endif
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#if NUM_DEVS_MT > 1
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extern DEVICE mtb_dev;
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#endif
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#ifdef NUM_DEVS_DISK
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extern DEVICE dda_dev;
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#endif
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#if NUM_DEVS_DISK > 1
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extern DEVICE ddb_dev;
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#endif
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/* Conditional error returns */
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/* Memory */
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#define MAXMEMSIZE ((16*1024*1024)/4) /* max memory size */
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#define PAMASK (MAXMEMSIZE - 1) /* physical addr mask */
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#define MEMSIZE (cpu_unit.capac) /* actual memory size */
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#define MEM_ADDR_OK(x) (((x)) < MEMSIZE)
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#define MAXMEMSIZE ((16*1024*1024)/4) /* max memory size */
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#define PAMASK (MAXMEMSIZE - 1) /* physical addr mask */
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#define MEMSIZE (cpu_unit.capac) /* actual memory size */
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#define MEM_ADDR_OK(x) (((x)) < MEMSIZE)
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/* Device information block */
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typedef struct dib {
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uint8 dev_addr; /* Device address */
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uint8 dev_class; /* Device class */
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/* Start I/O */
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uint8 (*start_io)(UNIT *uptr, uint16 chan);
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/* Start a command */
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uint8 (*start_cmd)(UNIT *uptr, uint16 chan, uint8 cmd);
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/* Stop I/O */
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uint8 (*halt_io)(UNIT *uptr);
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uint8 mask; /* device mask */
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uint8 numunits; /* number of units */
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/* Start I/O */
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uint8 (*start_io)(UNIT *uptr, uint16 chan);
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/* Start a command */
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uint8 (*start_cmd)(UNIT *uptr, uint16 chan, uint8 cmd);
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/* Stop I/O */
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uint8 (*halt_io)(UNIT *uptr);
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UNIT *units; /* Pointer to units structure */
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void (*dev_ini)(UNIT *, t_bool); /* init function */
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uint8 dev_addr; /* Device address */
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uint8 dev_class; /* Device class */
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} DIB;
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/* DEV 0x7F000000 UNIT 0x00ff0000 */
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#define DEV_V_ADDR DEV_V_UF /* Pointer to device address (16) */
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#define DEV_V_DADDR (DEV_V_UF + 8) /* Device address */
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#define DEV_ADDR_MASK (0x7f << DEV_V_DADDR) /* 24 bits shift */
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#define DEV_V_UADDR (DEV_V_UF) /* Device address in Unit */
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#define DEV_UADDR (1 << DEV_V_UADDR)
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#define GET_DADDR(x) (0x7f & ((x) >> DEV_V_ADDR))
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#define DEV_ADDR(x) ((x) << DEV_V_ADDR)
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/* Opcode definitions */
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#define OP_HALT 0x0000 /* Halt # * */
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#define OP_WAIT 0x0001 /* Wait # * */
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#define OP_NOP 0x0002 /* Nop # */
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#define OP_LCS 0x0003 /* Load Control Switches */
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#define OP_ES 0x0004 /* Extend Sign # */
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#define OP_RND 0x0005 /* Round Register # */
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#define OP_BEI 0x0006 /* Block External Interrupts # */
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#define OP_UEI 0x0007 /* Unblock External Interrupts # */
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#define OP_EAE 0x0008 /* Enable Arithmetic Exception Trap # */
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#define OP_RDSTS 0x0009 /* Read CPU Status Word * */
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#define OP_SIPU 0x000A /* Signal IPU # */
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#define OP_SEA 0x000D /* Set Extended Addressing # NBR */
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#define OP_DAE 0x000E /* Disable Arithmetic Exception Trap # */
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#define OP_CEA 0x000F /* Clear Extended Addressing # NBR */
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#define OP_ANR 0x0400 /* And Register # */
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#define OP_CMC 0x040A /* Cache Memory Control # */
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#define OP_SMC 0x0407 /* Shared Memory Control # */
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#define OP_RPSWT 0x040B /* Read Processor Status Word two # */
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#define OP_ORR 0x0800 /* Or Register # */
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#define OP_ORRM 0x0808 /* Or Register Masked # */
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#define OP_ZR 0x0C00 /* Zero Register # */
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#define OP_EOR 0x0C00 /* Exclusive Or Register # */
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#define OP_EORM 0x0C08 /* Exclusive Or Register Masked # */
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#define OP_CAR 0x1000 /* Compare Register # */
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#define OP_SACZ 0x1008 /* Shift and Count Zeros # BR */
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#define OP_CMR 0x1400 /* Compare masked with register */
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#define OP_SBR 0x1800 /* Set Bit in Register # */
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#define OP_ZBR 0x1804 /* Zero Bit In register # BR */
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#define OP_ABR 0x1808 /* Add Bit In Register # BR */
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#define OP_TBR 0x180C /* Test Bit in Register # BR */
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#define OP_SRABR 0x1C00 /* Shift Right Arithmetic # BR */
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#define OP_SRLBR 0x1C20 /* Shift Right Logical # BR */
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#define OP_SLABR 0x1C40 /* Shift Left Arithmetic # BR */
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#define OP_SLLBR 0x1C60 /* Shift Left Logical # BR */
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#define OP_SRADBR 0x2000 /* Shift Right Arithmetic Double # BR */
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#define OP_SRLDBR 0x2020 /* Shift Left Logical Double # BR */
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#define OP_SLADBR 0x2040 /* Shift Right Arithmetic Double # BR */
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#define OP_SLLDBR 0x2060 /* Shift Left Logical Double # BR */
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#define OP_SRCBR 0x2400 /* Shift Right Circular # BR */
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#define OP_ZBM 0x1C00 /* Zero Bit in Register # NBR */
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#define OP_ABR 0x2000 /* Add Bit in Register # NBR */
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#define OP_TBR 0x2400 /* Test Bit in Register # NBR */
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#define OP_TRSW 0x2800 /* Transfer GPR to PSD */
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#define OP_TRBR 0x2801 /* Transfer GPR to BR # BR */
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#define OP_XCBR 0x2802 /* Exchange Base Registers # BR */
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#define OP_TCCR 0x2802 /* Transfer CC to GPR # BR */
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#define OP_TRCC 0x2804 /* Transfer GPR to CC # BR */
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#define OP_BSUB 0x2805 /* Branch Subroutine # BR */
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#define OP_CALL 0x2808 /* Procedure Call # BR */
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#define OP_TPCBR 0x280C /* Transfer Program Counter to Base # BR */
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#define OP_RETURN 0x280E /* Procedure Return # BR */
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#define OP_TRR 0x2C00 /* Transfer Register to Register # */
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#define OP_TRDR 0x2C01 /* Transfer GPR to BR # */
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#define OP_TBRR 0x2C02 /* Transfer BR to GPR BR # */
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#define OP_TRC 0x2C03 /* Transfer Register Complement # */
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#define OP_TRN 0x2C04 /* Transfer Register Negative # */
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#define OP_XCR 0x2C05 /* Exchange Registers # */
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#define OP_LMAP 0x2C07 /* Load MAP * */
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#define OP_TRRM 0x2C08 /* Transfer Register to Register Masked # */
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#define OP_SETCPU 0x2C09 /* Set CPU Mode # * */
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#define OP_TMAPR 0x2C0A /* Transfer MAP to Register # * */
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#define OP_XCRM 0x2C0D /* Exchange Registers Masked # */
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#define OP_TRCM 0x2C0B /* Transfer Register Complement Masked # */
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#define OP_TRNM 0x2C0C /* Transfer Register Negative Masked # */
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#define OP_TRSC 0x2C0E /* Transfer Register to Scratchpad # * */
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#define OP_TSCR 0x2C0F /* Transfer Scratchpad to Register # * */
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#define OP_CALM 0x3000 /* Call Monitor # */
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#define OP_LA 0x3400 /* Load Address NBR */
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#define OP_ADR 0x3800 /* Add Register to Register # */
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#define OP_ADRFW 0x3801 /* Add Floating Point to Register # BR? */
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#define OP_MPRBR 0x3802 /* Multiply Register BR # */
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#define OP_SURFW 0x3803 /* Subtract Floating Point Register BR? # */
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#define OP_DVRFW 0x3804 /* Divide Floating Point Register BR? # */
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#define OP_FIXW 0x3805 /* Fix Floating Point Register BR? # */
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#define OP_MPRFW 0x3806 /* Multiply Floating Point Register BR? # */
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#define OP_FLTW 0x3807 /* Float Floating Point Register BR? # */
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#define OP_ADRM 0x3808 /* Add Register to Register Masked # */
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#define OP_DVRBR 0x380A /* Divide Register by Registier BR # */
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#define OP_SURFD 0x380B /* Subtract Floating Point Double # BR? */
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#define OP_DVRFD 0x380C /* Divide Floating Point Double # BR? */
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#define OP_FIXD 0x380D /* Fix Double Register # BR? */
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#define OP_MPRFD 0x380E /* Multiply Double Register # BR? */
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#define OP_FLTD 0x380F /* Float Double # BR? */
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#define OP_SUR 0x3C00 /* Subtract Register to Register # */
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#define OP_SURM 0x3C08 /* Subtract Register to Register Masked # */
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#define OP_MPR 0x4000 /* Multiply Register to Register # NBR */
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#define OP_DVR 0x4400 /* Divide Register to Register # NBR */
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#define OP_LA 0x5000 /* Load Address BR */
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#define OP_STWBR 0x5400 /* Store Base Register BR */
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#define OP_SUABR 0x5800 /* Subtract Base Register BR */
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#define OP_LABR 0x5808 /* Load Address Base Register BR */
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#define OP_LWBR 0x5C00 /* Load Base Register BR */
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#define OP_BSUBM 0x5C08 /* Branch Subroutine Memory BR */
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#define OP_CALLM 0x5C08 /* Call Memory BR */
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#define OP_NOR 0x6000 /* Normalize # NBR */
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#define OP_NORD 0x6400 /* Normalize Double # NBR*/
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#define OP_SCZ 0x6800 /* Shift and Count Zeros # */
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#define OP_SRA 0x6C00 /* Shift Right Arithmetic # NBR */
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#define OP_SLA 0x6C40 /* Shift Left Arithmetic # NBR */
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#define OP_SRL 0x7000 /* Shift Right Logical # NBR */
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#define OP_SLL 0x7040 /* Shift Left Logical # NBR */
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#define OP_SRC 0x7400 /* Shift Right Circular # NBR */
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#define OP_SLC 0x7440 /* Shift Left Circular # NBR */
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#define OP_SRAD 0x7800 /* Shift Right Arithmetic Double # NBR */
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#define OP_SLAD 0x7840 /* Shift Left Arithmetic Double # NBR */
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#define OP_SRLD 0x7C00 /* Shift Right Logical Double # NBR */
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#define OP_SLLD 0x7C40 /* Shift Left Logical Double # NBR */
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#define OP_LEAR 0x8000 /* Load Effective Address Real * */
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#define OP_ANMx 0x8400 /* And Memory B,H,W,D */
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#define OP_ORMx 0x8800 /* Or Memory B,H,W,D */
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#define OP_EOMx 0x8C00 /* Exclusive Or Memory */
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#define OP_CAMx 0x9000 /* Compare Arithmetic with Memory */
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#define OP_CMMx 0x9400 /* Compare Masked with Memory */
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#define OP_SBM 0x9800 /* Set Bit in Memory */
|
||||
#define OP_ZBM 0x9C00 /* Zero Bit in Memory */
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#define OP_ABM 0xA000 /* Add Bit in Memory */
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#define OP_TBM 0xA400 /* Test Bit in Memory */
|
||||
#define OP_EXM 0xA800 /* Execute Memory */
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#define OP_Lx 0xAC00 /* Load B,H,W,D */
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#define OP_LMx 0xB000 /* Load Masked B,H,W,D */
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#define OP_LNx 0xB400 /* Load Negative B,H,W,D */
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#define OP_ADMx 0xB800 /* Add Memory B,H,W,D */
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#define OP_SUMx 0xBC00 /* Subtract Memory B,H,W,D */
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#define OP_MPMx 0xC000 /* Multiply Memory B,H,W,D */
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#define OP_DVMx 0xC400 /* Divide Memory B,H,W,D */
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#define OP_LI 0xC800 /* Load Immediate */
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||||
#define OP_ADI 0xC801 /* Add Immediate */
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||||
#define OP_SUI 0xC802 /* Subtract Immediate */
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#define OP_MPI 0xC803 /* Multiply Immediate */
|
||||
#define OP_DVI 0xC804 /* Divide Immediate */
|
||||
#define OP_CI 0xC805 /* Compare Immediate */
|
||||
#define OP_SVC 0xC806 /* Supervisor Call */
|
||||
#define OP_EXR 0xC807 /* Execute Register/ Right */
|
||||
#define OP_SEM 0xC808 /* Store External Map * */
|
||||
#define OP_LEM 0xC809 /* Load External Map * */
|
||||
#define OP_CEMA 0xC80A /* Convert External Map * */
|
||||
#define OP_LF 0xCC00 /* Load File */
|
||||
#define OP_LEA 0xD000 /* Load Effective Address */
|
||||
#define OP_STx 0xD400 /* Store B,H,W,D */
|
||||
#define OP_STMx 0xD800 /* Store Masked B,H,W,D */
|
||||
#define OP_ADFx 0xE008 /* Add Floating Memory D,W */
|
||||
#define OP_SUFx 0xE000 /* Subtract Floating Memory D,W */
|
||||
#define OP_MPFx 0xE408 /* Multiply Floating Memory D,W */
|
||||
#define OP_DVFx 0xE400 /* Divide Floating Memory D,W */
|
||||
#define OP_ARMx 0xE800 /* Add Register to Memory B,H,W,D */
|
||||
#define OP_BU 0xEC00 /* Branch Unconditional */
|
||||
#define OP_BCT 0xEC00 /* Branch Condition True */
|
||||
#define OP_BCF 0xF000 /* Branch Condition False */
|
||||
#define OP_BIB 0xF400 /* Branch after Incrementing Byte */
|
||||
#define OP_BIW 0xF420 /* Branch after Incrementing Word */
|
||||
#define OP_BIH 0xF440 /* Branch after Incrementing Half */
|
||||
#define OP_BID 0xF460 /* Branch after Incrementing Double */
|
||||
#define OP_ZMx 0xF800 /* Zero Memory B,H,W,D */
|
||||
#define OP_BL 0xF880 /* Branch and Link */
|
||||
#define OP_BRI 0xF900 /* Branch and Reset Interrupt * */
|
||||
#define OP_LPSD 0xF980 /* Load Program Status Double * */
|
||||
#define OP_LPSDCM 0xFA80 /* LPSD and Change Map * */
|
||||
#define OP_TPR 0xFB80 /* Transfer Protect Register to Register */
|
||||
#define OP_TRP 0xFB00 /* Transfer Register to Protect Register */
|
||||
#define OP_EI 0xFC00 /* Enable Interrupt */
|
||||
#define OP_DI 0xFC01 /* Disable Interrupt */
|
||||
#define OP_RI 0xFC02 /* Request Interrupt */
|
||||
#define OP_AI 0xFC03 /* Activate Interrupt */
|
||||
#define OP_DAI 0xFC04 /* Deactivate Interrupt */
|
||||
#define OP_TD 0xFC05 /* Test Device */
|
||||
#define OP_CD 0xFC06 /* Command Device */
|
||||
#define OP_SIO 0xFC17 /* Start I/O */
|
||||
#define OP_TIO 0xFC1F /* Test I/O */
|
||||
#define OP_STPIO 0xFC27 /* Stop I/O */
|
||||
#define OP_RSCHNL 0xFC2F /* Reset Channel */
|
||||
#define OP_HIO 0xFC37 /* Halt I/O */
|
||||
#define OP_GRIO 0xFC3F /* Grab Controller */
|
||||
#define OP_RSCTL 0xFC47 /* Reset Controller */
|
||||
#define OP_ECI 0xFC67 /* Enable Channel Interrupt */
|
||||
#define OP_DCI 0xFC6F /* Disable Channel Interrupt */
|
||||
#define OP_ACI 0xFC77 /* Activate Channel Interrupt */
|
||||
#define OP_DACI 0xFC7F /* Deactivate Channel Interrupt */
|
||||
#define UNIT_V_ADDR 16
|
||||
#define UNIT_ADDR_MASK (0x7fff << UNIT_V_ADDR)
|
||||
#define GET_UADDR(x) ((UNIT_ADDR_MASK & x) >> UNIT_V_ADDR)
|
||||
#define UNIT_ADDR(x) ((x) << UNIT_V_ADDR)
|
||||
|
||||
#define PROTECT_V UNIT_V_UF+15
|
||||
#define PROTECT (1 << PROTECT_V)
|
||||
|
||||
|
||||
/* Debuging controls */
|
||||
/* Debugging controls */
|
||||
#define DEBUG_CMD 0x0000001 /* Show device commands */
|
||||
#define DEBUG_DATA 0x0000002 /* Show data transfers */
|
||||
#define DEBUG_DETAIL 0x0000004 /* Show details */
|
||||
#define DEBUG_EXP 0x0000008 /* Show error conditions */
|
||||
#define DEBUG_CONI 0x0000020 /* Show CONI instructions */
|
||||
#define DEBUG_CONO 0x0000040 /* Show CONO instructions */
|
||||
#define DEBUG_DATAIO 0x0000080 /* Show DATAI/O instructions */
|
||||
#define DEBUG_IRQ 0x0000100 /* Show IRQ requests */
|
||||
#define DEBUG_INST 0x0000010 /* Show instructions */
|
||||
#define DEBUG_DATAIO 0x0000020 /* Show DATA I/O instructions */
|
||||
#define DEBUG_IRQ 0x0000040 /* Show IRQ requests */
|
||||
#define DEBUG_TRAP 0x0000080 /* Show TRAP requests */
|
||||
#define DEBUG_POS 0x0000080 /* Show disk position data */
|
||||
|
||||
extern DEBTAB dev_debug[];
|
||||
|
||||
@@ -292,7 +220,14 @@ extern DEBTAB dev_debug[];
|
||||
#define MODEL_V6 6 /* V6 CPU */
|
||||
#define MODEL_V9 7 /* V9 CPU */
|
||||
|
||||
DEVICEC1 0x40 /* CC1 in CC */
|
||||
#define TMR_RTC 1
|
||||
|
||||
#define HIST_MIN 64
|
||||
#define HIST_MAX 10000
|
||||
#define HIST_PC 0x80000000
|
||||
|
||||
/* CC defs Held in CC */
|
||||
#define CC1 0x40 /* CC1 in CC */
|
||||
#define CC2 0x20 /* CC2 in CC */
|
||||
#define CC3 0x10 /* CC3 in CC */
|
||||
#define CC4 0x08 /* CC4 in CC */
|
||||
@@ -341,7 +276,6 @@ extern DEBTAB dev_debug[];
|
||||
#define PRIVHALT_TRAP 0xB8 /* Privlege Mode Halt Trap */
|
||||
#define AEXPCEPT_TRAP 0xBC /* Arithmetic Exception Trap */
|
||||
|
||||
|
||||
/* Errors returned from various functions */
|
||||
#define ALLOK 0x0000 /* no error, all is OK */
|
||||
#define MAPFLT MAPFAULT_TRAP /* map fault error */
|
||||
|
||||
1287
SEL32/sel32_mt.c
Normal file
1287
SEL32/sel32_mt.c
Normal file
File diff suppressed because it is too large
Load Diff
1982
SEL32/sel32_sys.c
1982
SEL32/sel32_sys.c
File diff suppressed because it is too large
Load Diff
25
SEL32/tests/cpu.icl
Normal file
25
SEL32/tests/cpu.icl
Normal file
@@ -0,0 +1,25 @@
|
||||
# Example ICL file for 32/7x
|
||||
# this line ignored
|
||||
*DEV04=0E150400,02 Cartridge disc with two platters
|
||||
*DEV08=0E160800,04 Moving head disc
|
||||
*DEV10=0E181000,04 9-Track magnetic tape
|
||||
*DEV20=0E1A2000,10 GPMC with 16 terminals
|
||||
*DEV60=0E1E6000,08 ADS
|
||||
*DEV78=01207800 Primary card reader
|
||||
*DEV7A=00217802 Primary line printer
|
||||
*DEV7E=02237801 Primary Teletype
|
||||
*INT00=1F Power fail/Auto restart
|
||||
*INT01=1E System Overide
|
||||
*INT12=1D Memory parity
|
||||
*INT13=1C Console Interrupt
|
||||
*INT24=1B Nonpresent memory
|
||||
*INT25=1A Undefined instruction trap
|
||||
*INT26=19 Privlege violation
|
||||
*INT27=18 Call Monitor
|
||||
*INT28=16 Real-time clock
|
||||
*INT29=17 Arithmetic exception
|
||||
*INT2A=15 External interrupt
|
||||
*INT2B=14 External interrupt
|
||||
*INT2C=13 External interrupt
|
||||
*INT2D=12 External interrupt
|
||||
*END
|
||||
BIN
SEL32/tests/testcode.mem
Normal file
BIN
SEL32/tests/testcode.mem
Normal file
Binary file not shown.
1009
SEL32/tests/testcode0.l
Normal file
1009
SEL32/tests/testcode0.l
Normal file
File diff suppressed because it is too large
Load Diff
BIN
SEL32/tests/testcode0.mem
Normal file
BIN
SEL32/tests/testcode0.mem
Normal file
Binary file not shown.
25
SEL32/tests/testcpu.l
Normal file
25
SEL32/tests/testcpu.l
Normal file
@@ -0,0 +1,25 @@
|
||||
00001 00000 ABS
|
||||
00002 P00000 DSECT
|
||||
00003 P00000 ORG 0
|
||||
00004 P00000 START EQU $
|
||||
00005 P00000 0002 NOP
|
||||
00006 P00002 0002 NOP
|
||||
00007 P00004 0103 LCS 2
|
||||
00008 P00006 0289 RDSTS 5
|
||||
00009 P00008 0006 BEI
|
||||
00010 P0000A 0007 UEI
|
||||
00011 P0000C F9800020 P00020 LPSD L20
|
||||
00012 P00010 AC800004 00004 LW 1,4
|
||||
00013 P00014 AD000009 00008 LH 2,8
|
||||
00014 P00018 AF000022 P00020 LD 6,L20
|
||||
00015 P0001C EC000029 P00028 BU GON
|
||||
00016 P00020 BOUND 1D
|
||||
00017 P00020 80000010 L20 DATAW X'80000010'
|
||||
00018 P00024 00004000 DATAW X'00004000'
|
||||
00019 P00028 CA0000FF GON LI 4,X'FF'
|
||||
00020 P0002C D6000100 00100 STW 4,X'100'
|
||||
00021 P00030 D6000103 00102 STH 4,X'102'
|
||||
00022 P00034 D700010A 00108 STD 6,X'108'
|
||||
00023 P00038 EC000001 P00000 BU START
|
||||
00024 P0003C P00000 END START
|
||||
* 0000 ERRORS IN MAIN
|
||||
24
SEL32/tests/testcpu.s
Normal file
24
SEL32/tests/testcpu.s
Normal file
@@ -0,0 +1,24 @@
|
||||
ABS
|
||||
DSECT
|
||||
ORG 0
|
||||
START EQU $
|
||||
NOP
|
||||
NOP
|
||||
LCS 2
|
||||
RDSTS 5
|
||||
BEI
|
||||
UEI
|
||||
LPSD L20
|
||||
LW 1,4
|
||||
LH 2,8
|
||||
LD 6,L20
|
||||
BU GON
|
||||
BOUND 1D
|
||||
L20 DATAW X'80000010'
|
||||
DATAW X'00004000'
|
||||
GON LI 4,X'FF'
|
||||
STW 4,X'100'
|
||||
STH 4,X'102'
|
||||
STD 6,X'108'
|
||||
BU START
|
||||
END START
|
||||
2293
SEL32/util/makecode.c
Normal file
2293
SEL32/util/makecode.c
Normal file
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user