github.com/rdolbeau.SBusFPGA
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move blit_goblin to common

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This commit is contained in:
Romain Dolbeau
2022-10-31 16:38:07 +01:00
parent b47cc4a54e
commit 02b1b7fced
2 changed files with 2 additions and 2 deletions
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2
sbus-to-ztex-gateware-migen/VintageBusFPGA_Common

Submodule sbus-to-ztex-gateware-migen/VintageBusFPGA_Common updated: 1a0d113e8b...de495473a9

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sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py
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@@ -560,7 +560,7 @@ class SBusFPGA(SoCCore):
self.bus.add_slave("goblin_accel", self.goblin_accel.bus, SoCRegion(origin=self.mem_map.get("jareth", None), size=0x1000, cached=False))
self.bus.add_master(name="goblin_accel_r5_i", master=self.goblin_accel.ibus)
self.bus.add_master(name="goblin_accel_r5_d", master=self.goblin_accel.dbus)
goblin_rom_file = "blit_goblin.raw"
goblin_rom_file = "VintageBusFPGA_Common/blit_goblin_sbus.raw"
goblin_rom_data = soc_core.get_mem_data(filename_or_regions=goblin_rom_file, endianness="little")
goblin_rom_len = 4*len(goblin_rom_data);
rounded_goblin_rom_len = 2**log2_int(goblin_rom_len, False)