More prep; splits CSR includes per-device
This commit is contained in:
Romain Dolbeau
@@ -298,32 +298,7 @@ sbusfpga_curve25519engine_attach(device_t parent, device_t self, void *aux)
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}
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#define CONFIG_CSR_DATA_WIDTH 32
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// define CSR_LEDS_BASE & others to avoid defining the CSRs of HW we don't handle
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#define CSR_LEDS_BASE
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//#define CSR_CURVE25519ENGINE_BASE
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#define CSR_DDRPHY_BASE
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#define CSR_EXCHANGE_WITH_MEM_BASE
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#define CSR_SBUS_BUS_STAT_BASE
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#define CSR_SDRAM_BASE
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#define CSR_SDBLOCK2MEM_BASE
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#define CSR_SDCORE_BASE
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#define CSR_SDIRQ_BASE
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#define CSR_SDMEM2BLOCK_BASE
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#define CSR_SDPHY_BASE
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#define CSR_TRNG_BASE
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#include "dev/sbus/litex_csr.h"
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#undef CSR_LEDS_BASE
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//#undef CSR_CURVE25519ENGINE_BASE
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#undef CSR_DDRPHY_BASE
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#undef CSR_EXCHANGE_WITH_MEM_BASE
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#undef CSR_SBUS_BUS_STAT_BASE
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#undef CSR_SDRAM_BASE
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#undef CSR_SDBLOCK2MEM_BASE
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#undef CSR_SDCORE_BASE
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#undef CSR_SDIRQ_BASE
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#undef CSR_SDMEM2BLOCK_BASE
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#undef CSR_SDPHY_BASE
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#undef CSR_TRNG_BASE
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#include "dev/sbus/sbusfpga_csr_curve25519engine.h"
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#define REG_BASE(reg) (base + (reg * 32))
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#define SUBREG_ADDR(reg, off) (REG_BASE(reg) + (off)*4)
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@@ -540,37 +540,12 @@ sbusfpga_sdram_diskstart(device_t self, struct buf *bp)
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#define CONFIG_CSR_DATA_WIDTH 32
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// define CSR_LEDS_BASE & others to avoid defining the CSRs of HW we don't handle
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#define CSR_LEDS_BASE
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#define CSR_CURVE25519ENGINE_BASE
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//#define CSR_DDRPHY_BASE
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//#define CSR_SDRAM_BASE
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//#define CSR_EXCHANGE_WITH_MEM_BASE
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#define CSR_SBUS_BUS_STAT_BASE
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#define CSR_SDBLOCK2MEM_BASE
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#define CSR_SDCORE_BASE
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#define CSR_SDIRQ_BASE
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#define CSR_SDMEM2BLOCK_BASE
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#define CSR_SDPHY_BASE
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#define CSR_TRNG_BASE
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/* grrr */
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#define sbusfpga_exchange_with_mem_softc sbusfpga_sdram_softc
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#define sbusfpga_ddrphy_softc sbusfpga_sdram_softc
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#include "dev/sbus/litex_csr.h"
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#undef CSR_LEDS_BASE
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#undef CSR_CURVE25519ENGINE_BASE
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//#undef CSR_DDRPHY_BASE
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//#undef CSR_SDRAM_BASE
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//#undef CSR_EXCHANGE_WITH_MEM_BASE
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#undef CSR_SBUS_BUS_STAT_BASE
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#undef CSR_SDBLOCK2MEM_BASE
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#undef CSR_SDCORE_BASE
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#undef CSR_SDIRQ_BASE
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#undef CSR_SDMEM2BLOCK_BASE
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#undef CSR_SDPHY_BASE
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#undef CSR_TRNG_BASE
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#include "dev/sbus/sbusfpga_csr_exchange_with_mem.h"
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#include "dev/sbus/sbusfpga_csr_ddrphy.h"
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#include "dev/sbus/sbusfpga_csr_sdram.h"
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/* not yet generated */
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static inline void exchange_with_mem_checksum_read(struct sbusfpga_sdram_softc *sc, uint32_t* data) {
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@@ -106,33 +106,7 @@ sbusfpga_stat_match(device_t parent, cfdata_t cf, void *aux)
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}
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#define CONFIG_CSR_DATA_WIDTH 32
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// define CSR_LEDS_BASE & others to avoid defining the CSRs of HW we don't handle
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#define CSR_LEDS_BASE
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#define CSR_CURVE25519ENGINE_BASE
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#define CSR_DDRPHY_BASE
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#define CSR_EXCHANGE_WITH_MEM_BASE
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// #define CSR_SBUS_BUS_STAT_BASE
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#define CSR_SDRAM_BASE
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#define CSR_SDBLOCK2MEM_BASE
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#define CSR_SDCORE_BASE
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#define CSR_SDIRQ_BASE
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#define CSR_SDMEM2BLOCK_BASE
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#define CSR_SDPHY_BASE
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#define CSR_TRNG_BASE
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#include "dev/sbus/litex_csr.h"
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#undef CSR_LEDS_BASE
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#undef CSR_CURVE25519ENGINE_BASE
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#undef CSR_DDRPHY_BASE
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#undef CSR_EXCHANGE_WITH_MEM_BASE
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// #undef CSR_SBUS_BUS_STAT_BASE
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#undef CSR_SDRAM_BASE
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#undef CSR_SDBLOCK2MEM_BASE
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#undef CSR_SDCORE_BASE
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#undef CSR_SDIRQ_BASE
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#undef CSR_SDMEM2BLOCK_BASE
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#undef CSR_SDPHY_BASE
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//#undef CSR_TRNG_BASE
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#include "dev/sbus/sbusfpga_csr_sbus_bus_stat.h"
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static void sbusfpga_stat_display(void *);
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@@ -107,32 +107,7 @@ sbusfpga_trng_match(device_t parent, cfdata_t cf, void *aux)
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}
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#define CONFIG_CSR_DATA_WIDTH 32
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// define CSR_LEDS_BASE & others to avoid defining the CSRs of HW we don't handle
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#define CSR_LEDS_BASE
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#define CSR_CURVE25519ENGINE_BASE
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#define CSR_DDRPHY_BASE
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#define CSR_EXCHANGE_WITH_MEM_BASE
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#define CSR_SBUS_BUS_STAT_BASE
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#define CSR_SDRAM_BASE
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#define CSR_SDBLOCK2MEM_BASE
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#define CSR_SDCORE_BASE
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#define CSR_SDIRQ_BASE
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#define CSR_SDMEM2BLOCK_BASE
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#define CSR_SDPHY_BASE
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//#define CSR_TRNG_BASE
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#include "dev/sbus/litex_csr.h"
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#undef CSR_LEDS_BASE
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#undef CSR_CURVE25519ENGINE_BASE
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#undef CSR_DDRPHY_BASE
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#undef CSR_EXCHANGE_WITH_MEM_BASE
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#undef CSR_SBUS_BUS_STAT_BASE
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#undef CSR_SDRAM_BASE
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#undef CSR_SDBLOCK2MEM_BASE
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#undef CSR_SDCORE_BASE
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#undef CSR_SDIRQ_BASE
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#undef CSR_SDMEM2BLOCK_BASE
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#undef CSR_SDPHY_BASE
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//#undef CSR_TRNG_BASE
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#include "dev/sbus/sbusfpga_csr_trng.h"
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static void
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sbusfpga_trng_getentropy(size_t nbytes, void *cookie) {
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File diff suppressed because it is too large
Load Diff
@@ -131,3 +131,58 @@ def get_csr_forth_header(csr_regions, mem_regions, constants, csr_base=None):
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for name, region in mem_regions.items():
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r += "h# " + hex(region.origin).replace("0x", "") + " constant " + "sbusfpga_regionaddr_{}".format(name) + "\n"
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return r
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def get_csr_header_split(regions, constants, csr_base=None, with_access_functions=True):
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alignment = constants.get("CONFIG_CSR_ALIGNMENT", 32)
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ar = dict()
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for name, region in regions.items():
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r = generated_banner("//")
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r += "#ifndef __GENERATED_{}_CSR_H\n#define __GENERATED_{}_CSR_H\n".format(name.upper(), name.upper())
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csr_base = csr_base if csr_base is not None else regions[next(iter(regions))].origin
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origin = region.origin - csr_base
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r += "\n/* "+name+" */\n"
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r += "#ifndef CSR_BASE\n"
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r += "#define CSR_BASE {}L\n".format(hex(csr_base))
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r += "#endif\n"
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r += "#ifndef CSR_"+name.upper()+"_BASE\n"
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r += "#define CSR_"+name.upper()+"_BASE (CSR_BASE + "+hex(origin)+"L)\n"
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if not isinstance(region.obj, Memory):
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for csr in region.obj:
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nr = (csr.size + region.busword - 1)//region.busword
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r += _get_rw_functions_c(name, csr.name, origin, region.origin - csr_base, nr, region.busword, alignment,
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getattr(csr, "read_only", False), with_access_functions)
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origin += alignment//8*nr
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if hasattr(csr, "fields"):
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for field in csr.fields.fields:
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offset = str(field.offset)
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size = str(field.size)
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r += "#define CSR_"+name.upper()+"_"+csr.name.upper()+"_"+field.name.upper()+"_OFFSET "+offset+"\n"
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r += "#define CSR_"+name.upper()+"_"+csr.name.upper()+"_"+field.name.upper()+"_SIZE "+size+"\n"
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if with_access_functions and csr.size <= 32: # FIXME: Implement extract/read functions for csr.size > 32-bit.
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reg_name = name + "_" + csr.name.lower()
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field_name = reg_name + "_" + field.name.lower()
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r += "static inline uint32_t " + field_name + "_extract(struct sbusfpga_" + name + "_softc *sc, uint32_t oldword) {\n"
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r += "\tuint32_t mask = ((1 << " + size + ")-1);\n"
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r += "\treturn ( (oldword >> " + offset + ") & mask );\n}\n"
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r += "static inline uint32_t " + field_name + "_read(struct sbusfpga_" + name + "_softc *sc) {\n"
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r += "\tuint32_t word = " + reg_name + "_read(sc);\n"
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r += "\treturn " + field_name + "_extract(sc, word);\n"
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r += "}\n"
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if not getattr(csr, "read_only", False):
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r += "static inline uint32_t " + field_name + "_replace(struct sbusfpga_" + name + "_softc *sc, uint32_t oldword, uint32_t plain_value) {\n"
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r += "\tuint32_t mask = ((1 << " + size + ")-1);\n"
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r += "\treturn (oldword & (~(mask << " + offset + "))) | (mask & plain_value)<< " + offset + " ;\n}\n"
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r += "static inline void " + field_name + "_write(struct sbusfpga_" + name + "_softc *sc, uint32_t plain_value) {\n"
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r += "\tuint32_t oldword = " + reg_name + "_read(sc);\n"
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r += "\tuint32_t newword = " + field_name + "_replace(sc, oldword, plain_value);\n"
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r += "\t" + reg_name + "_write(sc, newword);\n"
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r += "}\n"
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r += "#endif // CSR_"+name.upper()+"_BASE\n"
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r += "\n#endif\n"
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ar[name] = r
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return ar
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@@ -349,6 +349,14 @@ def main():
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csr_base = soc.mem_regions['csr'].origin)
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write_to_file(os.path.join("netbsd_csr.h"), csr_contents)
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csr_contents_dict = sbus_to_fpga_export.get_csr_header_split(
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regions = soc.csr_regions,
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constants = soc.constants,
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csr_base = soc.mem_regions['csr'].origin)
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for name in csr_contents_dict.keys():
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write_to_file(os.path.join("sbusfpga_csr_{}.h".format(name)), csr_contents_dict[name])
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# tells the prom where to find what
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# just one, as that is board-specific
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# BEWARE! then need to run 'forth_to_migen_rom.sh' *and* regenerate the bitstream with the proper PROM built-in!
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