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fix checksum-less building

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This commit is contained in:
Romain Dolbeau 2021-11-06 10:18:23 +01:00
parent ef9d16507b
commit 3c96a56dfb
1 changed files with 2 additions and 2 deletions
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4
sbus-to-ztex-gateware-migen/sbus_to_fpga_blk_dma.py
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@ -79,8 +79,8 @@ class ExchangeWithMem(Module, AutoCSR):
])
self.wr_tosdram = CSRStatus(32, description = "Last address written to SDRAM")
if (do_checksum):
self.checksum = CSRStorage(data_width_bits, write_from_dev=True, description = "checksum (XOR)");
#if (do_checksum):
self.checksum = CSRStorage(data_width_bits, write_from_dev=True, description = "checksum (XOR)");
self.submodules.req_r_fsm = req_r_fsm = FSM(reset_state="Reset")
self.submodules.req_w_fsm = req_w_fsm = FSM(reset_state="Reset")