fix sdram prom config fix, drop DMA from the sdram DMA and talk to a native SDRAM port instead
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Romain Dolbeau
parent
9ff265446d
commit
3e7bd4c8ab
@ -37,7 +37,7 @@ A ROM, a SDRAM controller ([litedram](https://github.com/enjoy-digital/litedram)
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Master access to the SBus by the host are routed to the Wishbone to access the various CSRs / control registers of the devices.
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The ROM doesn't do much beyond exposing the devices' existence and specifications to the host.
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The ROM exposes the devices' existence and specifications to the host, initializes the embedded SDRAM controller (but assuming known values, the NetBSD driver can also optionally initialize the SDRAM via proper calibration), enables FB support on the bw2/cg3/cg6 (last one with accelerated scrolling), and has support for RO access to the sdcard such enabling booting.
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The USB OHCI DMA (USB 1.1) is bridged from the Wishbone to the SBus by having the physical addresses of the Wishbone (that match the virtual addresses from NetBSD DVMA allocations) to the bridge. Reads are buffered by block of 16 bytes; currently writes are unbuffered (and somewhat slow, as they need a full SBus master cycle for every transaction of 32 bits or less). The standard NetBSD OHCI driver is used, with just a small custom SBus-OHCI driver mirroring the PCI-OHCI one. It uses the interrupt level 4 by default. It connects to the micro-B USB connector, an a cable such as [this one](https://www.startech.com/en-us/cables/uusbotgra) allows to expose a conventional USB type A connector for either an external (preferably self-powered) USB Hub or a single low-power device.
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@ -11,14 +11,14 @@ from litex.soc.interconnect import wishbone
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# the blk_addr does the round-trip to accompany the data
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# mem_size in MiB, might be weird if some space is reserved for other use (e.g. FrameBuffer)
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class ExchangeWithMem(Module, AutoCSR):
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def __init__(self, soc, platform, tosbus_fifo, fromsbus_fifo, fromsbus_req_fifo, dram_dma_writer, dram_dma_reader, mem_size=256, burst_size = 8, do_checksum = False):
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def __init__(self, soc, platform, tosbus_fifo, fromsbus_fifo, fromsbus_req_fifo, dram_native_r, dram_native_w, mem_size=256, burst_size = 8, do_checksum = False):
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#self.wishbone_r_slave = wishbone.Interface(data_width=soc.bus.data_width)
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#self.wishbone_w_slave = wishbone.Interface(data_width=soc.bus.data_width)
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self.tosbus_fifo = tosbus_fifo
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self.fromsbus_fifo = fromsbus_fifo
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self.fromsbus_req_fifo = fromsbus_req_fifo
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self.dram_dma_writer = dram_dma_writer
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self.dram_dma_reader = dram_dma_reader
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self.dram_native_r = dram_native_r
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self.dram_native_w = dram_native_w
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tosbus_fifo_din = Record(soc.tosbus_layout)
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self.comb += self.tosbus_fifo.din.eq(tosbus_fifo_din.raw_bits())
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@ -33,8 +33,12 @@ class ExchangeWithMem(Module, AutoCSR):
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data_width_bits = burst_size * 32
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blk_addr_width = 32 - log2_int(data_width) # 27 for burst_size == 8
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assert(len(self.dram_dma_writer.sink.data) == data_width_bits)
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assert(len(self.dram_dma_reader.source.data) == data_width_bits)
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assert(len(self.dram_native_r.rdata.data) == data_width_bits)
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assert(len(self.dram_native_r.wdata.data) == data_width_bits)
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#assert(len(self.dram_native_r.cmd.addr) == (blk_addr_width - 4))
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assert(len(self.dram_native_w.rdata.data) == data_width_bits)
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assert(len(self.dram_native_w.wdata.data) == data_width_bits)
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#assert(len(self.dram_native_w.cmd.addr) == (blk_addr_width - 4))
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#self.wishbone_r_master = wishbone.Interface(data_width=data_width_bits)
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#self.wishbone_w_master = wishbone.Interface(data_width=data_width_bits)
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@ -42,7 +46,7 @@ class ExchangeWithMem(Module, AutoCSR):
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#self.submodules += wishbone.Converter(self.wishbone_r_master, self.wishbone_r_slave)
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#self.submodules += wishbone.Converter(self.wishbone_w_master, self.wishbone_w_slave)
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print("ExchangeWithMem: data_width = {}, data_width_bits = {}, blk_addr_width = {}\n".format(data_width, data_width_bits, blk_addr_width))
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print("ExchangeWithMem: data_width = {}, data_width_bits = {}, blk_addr_width = {} dram_native_r.cmd.addr bits = {} \n".format(data_width, data_width_bits, blk_addr_width, len(self.dram_native_r.cmd.addr)))
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print("ExchangeWithMem: tosbus_fifo width = {}, fromsbus_fifo width = {}, fromsbus_req_fifo width = {}\n".format(len(tosbus_fifo.din), len(fromsbus_fifo.dout), len(fromsbus_req_fifo.din)))
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local_r_addr = Signal(blk_addr_width)
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@ -50,8 +54,8 @@ class ExchangeWithMem(Module, AutoCSR):
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#local_r_widx = Signal(log2_int(burst_size)) # so width is 3 for burst_size == 8
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#local_r_buffer = Signal(data_width_bits)
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local_w_addr = Signal(blk_addr_width)
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dma_w_addr = Signal(32)
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#local_w_addr = Signal(blk_addr_width)
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#dma_w_addr = Signal(32)
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#local_w_widx = Signal(log2_int(burst_size)) # so width is 3 for burst_size == 8
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#local_w_buffer = Signal(data_width_bits)
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@ -164,6 +168,12 @@ class ExchangeWithMem(Module, AutoCSR):
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#self.comb += self.dma_status.status[26:27].eq(self.wishbone_r_master.we)
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#self.comb += self.dma_status.status[27:28].eq(self.wishbone_r_master.ack)
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#self.comb += self.dma_status.status[28:29].eq(self.wishbone_r_master.err)
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self.comb += [ self.dram_native_r.rdata.ready.eq(self.tosbus_fifo.writable),
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self.dram_native_r.cmd.we.eq(0),
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self.dram_native_w.rdata.ready.eq(0),
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self.dram_native_w.cmd.we.eq(1),
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self.dram_native_w.wdata.we.eq(Replicate(1, data_width)), ]
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req_r_fsm.act("Reset",
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NextState("Idle")
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@ -184,22 +194,21 @@ class ExchangeWithMem(Module, AutoCSR):
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)
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)
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req_r_fsm.act("ReqFromMemory",
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self.dram_dma_reader.sink.address.eq(local_r_addr),
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self.dram_dma_reader.sink.valid.eq(1),
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If(self.dram_dma_reader.sink.ready,
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self.dram_native_r.cmd.addr.eq(local_r_addr),
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self.dram_native_r.cmd.valid.eq(1),
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If(self.dram_native_r.cmd.ready,
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NextState("WaitForData")
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)
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)
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req_r_fsm.act("WaitForData",
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If(self.dram_dma_reader.source.valid & self.tosbus_fifo.writable,
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If(self.dram_native_r.rdata.valid & self.tosbus_fifo.writable,
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self.tosbus_fifo.we.eq(1),
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tosbus_fifo_din.address.eq(dma_r_addr),
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tosbus_fifo_din.data.eq(self.dram_dma_reader.source.data),
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tosbus_fifo_din.data.eq(self.dram_native_r.rdata.data),
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If(do_checksum,
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self.checksum.we.eq(1),
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self.checksum.dat_w.eq(self.checksum.storage ^ self.dram_dma_reader.source.data),
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self.checksum.dat_w.eq(self.checksum.storage ^ self.dram_native_r.rdata.data),
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),
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self.dram_dma_reader.source.ready.eq(1),
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NextValue(self.last_blk.status, local_r_addr),
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NextValue(self.last_dma.status, dma_r_addr),
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NextValue(self.blk_rem.status, self.blk_rem.status - 1),
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@ -266,17 +275,24 @@ class ExchangeWithMem(Module, AutoCSR):
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)
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req_w_fsm.act("Idle",
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If(self.fromsbus_fifo.readable,
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self.dram_dma_writer.sink.address.eq(fromsbus_fifo_dout.blkaddress),
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self.dram_dma_writer.sink.data.eq(fromsbus_fifo_dout.data),
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self.dram_dma_writer.sink.valid.eq(1),
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self.dram_native_w.cmd.addr.eq(fromsbus_fifo_dout.blkaddress),
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self.dram_native_w.cmd.valid.eq(1),
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NextValue(self.wr_tosdram.status, fromsbus_fifo_dout.blkaddress),
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If(self.dram_dma_writer.sink.ready,
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self.fromsbus_fifo.re.eq(1),
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NextValue(self.dma_wrdone.status, self.dma_wrdone.status + 1),
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If(do_checksum,
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self.checksum.we.eq(1),
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self.checksum.dat_w.eq(self.checksum.storage ^ fromsbus_fifo_dout.data),
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)
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If(self.dram_native_w.cmd.ready,
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NextState("Write"),
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)
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)
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)
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req_w_fsm.act("Write",
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self.dram_native_w.wdata.data.eq(fromsbus_fifo_dout.data),
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self.dram_native_w.wdata.valid.eq(1),
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If(self.dram_native_w.wdata.ready,
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self.fromsbus_fifo.re.eq(1),
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NextValue(self.dma_wrdone.status, self.dma_wrdone.status + 1),
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If(do_checksum,
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self.checksum.we.eq(1),
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self.checksum.dat_w.eq(self.checksum.storage ^ fromsbus_fifo_dout.data),
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),
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NextState("Idle"),
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)
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)
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@ -158,6 +158,19 @@ def get_prom(soc,
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r += "\" RDOL,sdram\" device-name\n"
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r += get_header_mapx_stuff("mregs", [ "ddrphy", "sdram", "exchange_with_mem" ], [ 4096, 4096, 4096 ], [ "csr", "csr", "csr" ])
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r += "sbusfpga_irq_sdram encode-int \" interrupts\" property\n"
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if (sys_clk_freq == 100e6):
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r += "h# 19 constant m0_delay\n"
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r += "h# 19 constant m1_delay\n"
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r += "h# 1 constant m0_bitslip\n"
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r += "h# 1 constant m1_bitslip\n"
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elif (sys_clk_freq == 90e6):
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r += "h# 1c constant m0_delay\n"
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r += "h# 1c constant m1_delay\n"
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r += "h# 1 constant m0_bitslip\n"
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r += "h# 1 constant m1_bitslip\n"
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else:
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print("UNCALIBRATED FREQUENCY for SDRAM!")
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assert(False)
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r += "fload sdram_init.fth\ninit!\n"
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else:
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r += "\" RDOL,hidden_sdram\" device-name\n"
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@ -217,19 +230,6 @@ def get_prom(soc,
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if (sdcard):
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r += "\" LITEX,sdcard\" device-name\n"
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r += get_header_mapx_stuff("sdcard", ["sdcore", "sdirq", "sdphy", "sdblock2mem", "sdmem2block" ], [ 4096, 4096, 4096, 4096, 4096 ], [ "csr", "csr", "csr", "csr", "csr" ] )
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if (sys_clq_freq == 100e6):
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r += "25 constant m0_delay\n"
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r += "25 constant m1_delay\n"
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r += "1 constant m0_bitslip\n"
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r += "1 constant m1_bitslip\n"
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elif (sys_clq_freq == 90e6):
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r += "28 constant m0_delay\n"
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r += "28 constant m1_delay\n"
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r += "1 constant m0_bitslip\n"
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r += "1 constant m1_bitslip\n"
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else:
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print("UNCALIBRATED FREQUENCY for SDRAM!")
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assert(False)
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r += ": sdcard-init!\n"
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r += " map-in-sdcard\n"
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r += " 0 sdirq-virt h# 8 + l! ( disable irqs )\n"
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@ -418,21 +418,23 @@ class SBusFPGA(SoCCore):
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self.submodules.fromsbus_fifo = ClockDomainsRenamer({"write": "sbus", "read": "sys"})(AsyncFIFOBuffered(width=layout_len(self.fromsbus_layout), depth=burst_size))
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self.submodules.fromsbus_req_fifo = ClockDomainsRenamer({"read": "sbus", "write": "sys"})(AsyncFIFOBuffered(width=layout_len(self.fromsbus_req_layout), depth=burst_size))
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if (sdram):
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self.submodules.dram_dma_writer = LiteDRAMDMAWriter(port=self.sdram.crossbar.get_port(mode="write", data_width=data_width_bits),
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fifo_depth=4,
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fifo_buffered=True)
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#self.submodules.dram_dma_writer = LiteDRAMDMAWriter(port=self.sdram.crossbar.get_port(mode="write", data_width=data_width_bits),
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# fifo_depth=4,
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# fifo_buffered=True)
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#
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#self.submodules.dram_dma_reader = LiteDRAMDMAReader(port=self.sdram.crossbar.get_port(mode="read", data_width=data_width_bits),
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# fifo_depth=4,
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# fifo_buffered=True)
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self.submodules.dram_dma_reader = LiteDRAMDMAReader(port=self.sdram.crossbar.get_port(mode="read", data_width=data_width_bits),
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fifo_depth=4,
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fifo_buffered=True)
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self.submodules.exchange_with_mem = ExchangeWithMem(soc=self,
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platform=platform,
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tosbus_fifo=self.tosbus_fifo,
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fromsbus_fifo=self.fromsbus_fifo,
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fromsbus_req_fifo=self.fromsbus_req_fifo,
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dram_dma_writer=self.dram_dma_writer,
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dram_dma_reader=self.dram_dma_reader,
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#dram_dma_writer=self.dram_dma_writer,
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#dram_dma_reader=self.dram_dma_reader,
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dram_native_r=self.sdram.crossbar.get_port(mode="read", data_width=data_width_bits),
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dram_native_w=self.sdram.crossbar.get_port(mode="write", data_width=data_width_bits),
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mem_size=avail_sdram//1048576,
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burst_size=burst_size,
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do_checksum = False)
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@ -624,7 +626,7 @@ def main():
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csr_base = soc.mem_regions['csr'].origin)
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write_to_file(os.path.join(f"prom_csr_{version_for_filename}.fth"), csr_forth_contents)
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prom_content = sbus_to_fpga_prom.get_prom(soc=soc, version=args.version, sys_clk_freq=sys_clk_freq,
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prom_content = sbus_to_fpga_prom.get_prom(soc=soc, version=args.version, sys_clk_freq=int(float(args.sys_clk_freq)),
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trng=args.trng,
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usb=args.usb,
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sdram=args.sdram,
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